URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
Subversion Repositories bustap-jtag
Compare Revisions
- This comparison shows the changes necessary to convert path
/bustap-jtag/trunk/sim/altera
- from Rev 10 to Rev 9
- ↔ Reverse comparison
Rev 10 → Rev 9
/virtual_jtag_stimulus.tcl
380,7 → 380,6
set trig_sim_num [expr $trig_sim_num+1] |
set trig_sim_len [expr $trig_sim_len+2] |
$log delete 1.0 end |
$log insert end "`define USE_SIM_STIMULUS\n\n" |
$log insert end "`define FIFO_SLD_SIM_ACTION $fifo_sim_act\n" |
$log insert end "`define FIFO_SLD_SIM_N_SCAN $fifo_sim_num\n" |
$log insert end "`define FIFO_SLD_SIM_T_LENG $fifo_sim_len\n\n" |
391,7 → 390,7
$log insert end "`define TRIG_SLD_SIM_N_SCAN $trig_sim_num\n" |
$log insert end "`define TRIG_SLD_SIM_T_LENG $trig_sim_len\n\n" |
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set fileId [open ../../rtl/altera/jtag_sim_define.h w] |
set fileId [open jtag_sim_define.h w] |
puts $fileId [$log get 1.0 end] |
close $fileId |
} |
/sim.do
11,9 → 11,9
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# compile altera virtual jtag files |
source virtual_jtag_stimulus.tcl |
vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v +incdir+../../rtl/altera |
vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v +incdir+../../rtl/altera |
vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v +incdir+../../rtl/altera |
vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v |
vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v |
vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v |
vlog -work work altera_mf.v |
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# compile testbench files |
35,7 → 35,7
up_bfm_sv.obj -L $::env(MODEL_TECH) -lmtipli |
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# compile jtag bfms files |
vlog -work work -sv jtag_bfm_sv.v +incdir+../../rtl/altera |
vlog -work work -sv jtag_bfm_sv.v |
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vsim -novopt \ |
-sv_lib up_bfm_c \ |
/jtag_sim_define.h
0,0 → 1,14
`define FIFO_SLD_SIM_ACTION "((1,1,1,2))" |
`define FIFO_SLD_SIM_N_SCAN 1 |
`define FIFO_SLD_SIM_T_LENG 2 |
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`define ADDR_SLD_SIM_ACTION "((0,1,1,2),(0,2,0Dffff0000,28),(0,1,1,2),(0,2,1Cffff0000,28),(0,1,1,2),(0,2,2Cffff0000,28),(0,1,1,2),(0,2,3Cffff0000,28),(0,1,1,2),(0,2,4Cffff0000,28),(0,1,1,2),(0,2,5Cffff0000,28),(0,1,1,2),(0,2,6Cffff0000,28),(0,1,1,2),(0,2,7Cffff0000,28),(0,1,1,2),(0,2,8D00000000,28),(0,1,1,2),(0,2,9C00000000,28),(0,1,1,2),(0,2,AC00000000,28),(0,1,1,2),(0,2,BC00000000,28),(0,1,1,2),(0,2,CC00000000,28),(0,1,1,2),(0,2,DC00000000,28),(0,1,1,2),(0,2,EC00000000,28),(0,1,1,2),(0,2,FC00000000,28),(1,1,1,2))" |
`define ADDR_SLD_SIM_N_SCAN 33 |
`define ADDR_SLD_SIM_T_LENG 674 |
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`define TRIG_SLD_SIM_ACTION "((0,1,1,2),(0,2,06ffffa5a5a5a5,38),(0,1,1,2),(0,2,07ffffa5a5a5a5,38),(1,1,1,2))" |
`define TRIG_SLD_SIM_N_SCAN 5 |
`define TRIG_SLD_SIM_T_LENG 118 |
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