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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

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  • This comparison shows the changes necessary to convert path 
    /bustap-jtag
    from Rev 10 to Rev 11
    ↔ Reverse comparison
  •

Rev 10 → Rev 11

/trunk/rtl/up_monitor.v
54,6 → 54,12
// for capture storage
wire [49:0] capture_in;
wire capture_wr;
// for pretrigger capture
wire [9:0] pretrig_num;
reg [9:0] pretrig_cnt;
wire pretrig_full;
wire pretrig_wr;
reg pretrig_wr_d1,pretrig_rd;
 
/////////////////////////////////////////////////
// Capture logic main
118,10 → 124,32
end
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr-in
// generate capture wr_in
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
 
// generate pre-trigger wr_in
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
always @(posedge clk)
begin
if (!trig_en || (trig_en && !trig_set)) begin
pretrig_cnt <= 10'd0;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (!pretrig_full) begin
pretrig_cnt <= pretrig_cnt + addr_mask_ok;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (pretrig_full) begin
pretrig_cnt <= pretrig_cnt;
pretrig_wr_d1<= pretrig_wr;
pretrig_rd <= pretrig_wr_d1;
end
end
 
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
129,8 → 157,9
// index 0, instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
.wr_in(capture_wr || pretrig_wr),
.data_in(capture_in),
.rd_in(pretrig_rd)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 50,
167,9 → 196,11
 
// index 2, instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_cond)
.trig_out(trig_cond),
.pnum_out(pretrig_num)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 56;
u_virtual_jtag_adda_trig.trig_width = 56,
u_virtual_jtag_adda_trig.pnum_width = 10;
 
endmodule
/trunk/rtl/altera/virtual_jtag_adda_fifo.v
16,7 → 16,7
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_fifo(clk,wr_en,data_in);
module virtual_jtag_adda_fifo(clk,wr_in,data_in,rd_in);
 
parameter data_width = 32,
fifo_depth = 256,
25,7 → 25,7
al_empt_val = 0;
 
input clk;
input wr_en;
input wr_in, rd_in;
input [data_width-1:0] data_in;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
50,7 → 50,8
reg read_instr_d1;
reg read_instr_d2;
reg read_instr_d3;
wire rd_en = read_instr_d2 & !read_instr_d3;
wire rd_en = rd_in | (read_instr_d2 & !read_instr_d3);
wire wr_en = wr_in;
always @(posedge clk or posedge reset)
begin
if (reset)
/trunk/rtl/altera/virtual_jtag_adda_trig.v
16,21 → 16,26
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_trig(trig_out);
module virtual_jtag_adda_trig(trig_out, pnum_out);
 
parameter trig_width = 32;
parameter pnum_width = 10;
 
output [trig_width-1:0] trig_out;
output [pnum_width-1:0] pnum_out;
 
reg [trig_width-1:0] trig_out;
reg [pnum_width-1:0] pnum_out;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [trig_width-1:0] trig_instr_reg;
reg [pnum_width-1:0] pnum_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
wire pnum_instr = ir_in[1] & ~ir_in[0]; // 2
 
always @(posedge tck)
begin
38,6 → 43,12
trig_out <= trig_instr_reg;
end
 
always @(posedge tck)
begin
if (pnum_instr && e1dr)
pnum_out <= pnum_instr_reg;
end
 
/* trig_instr Instruction Handler */
always @ (posedge tck)
if ( trig_instr && cdr )
45,15 → 56,24
else if ( trig_instr && sdr )
trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
 
/* pnum_instr Instruction Handler */
always @ (posedge tck)
if ( pnum_instr && cdr )
pnum_instr_reg <= pnum_instr_reg;
else if ( pnum_instr && sdr )
pnum_instr_reg <= {tdi, pnum_instr_reg[pnum_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg <= tdi;
 
/* Node TDO Output */
always @ ( trig_instr, trig_instr_reg, bypass_reg )
always @ ( trig_instr, trig_instr_reg, pnum_instr, pnum_instr_reg, bypass_reg )
begin
if (trig_instr)
if (trig_instr)
tdo <= trig_instr_reg[0];
else if (pnum_instr)
tdo <= pnum_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
/trunk/cmd/altera/virtual_jtag_console.tcl
53,7 → 53,7
}
}
 
proc config_trig {{jtag_index_2 2} {trig 00000000000000}} {
proc config_trig {{jtag_index_2 2} {trig 00000000000000} {pnum 0}} {
global log
set trig_leng [string length $trig]
if {$trig_leng!=14} {
62,6 → 62,8
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig -length 56 -value_in_hex]
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 2 -no_captured_ir_value
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $pnum -length 10]
device_unlock
return $addr_trig
}
185,16 → 187,36
global address_span15
global address_span16
for {set i 1} {$i<=8} {incr i} {
set address_span$i ffff0000
if {[set address_span$i]==""} {
set address_span$i ffff0000
}
}
for {set i 9} {$i<=16} {incr i} {
set address_span$i 00000000
if {[set address_span$i]==""} {
set address_span$i 00000000
}
}
}
 
proc initTrigConfig {} {
global triggerAddr
global triggerData
global triggerPnum
if {[set triggerAddr]==""} {
set triggerAddr ffff
}
if {[set triggerData]==""} {
set triggerData a5a5a5a5
}
if {[set triggerPnum]==""} {
set triggerPnum 0
}
}
 
proc updateTrigger {{trigCmd 0}} {
global triggerAddr
global triggerData
global triggerPnum
global trig_wren
global trig_rden
global trig_aden
203,7 → 225,7
append triggerValue [format "%1X" [expr $trig_wren*8+$trig_rden*4+$trigCmd]]
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
config_trig 2 $triggerValue $triggerPnum
}
 
proc startTrigger {} {
357,7 → 379,6
.console.f2.address_span_en15 .console.f2.address_span15 \
.console.f2.address_span_en16 .console.f2.address_span16 \
-side left -ipadx 0
 
initAddrConfig
 
# set the address configuration buttons
374,18 → 395,20
pack .console.trig
button .console.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger}
entry .console.trig.trigvalue_addr -textvar triggerAddr -width 4
set triggerAddr ffff
entry .console.trig.trigvalue_data -textvar triggerData -width 8
set triggerData a5a5a5a5
checkbutton .console.trig.trigaddr -text {@Addr:} -variable trig_aden
checkbutton .console.trig.trigdata -text {@Data:} -variable trig_daen
checkbutton .console.trig.wren -text {@WR} -variable trig_wren
checkbutton .console.trig.rden -text {@RD} -variable trig_rden
pack .console.trig.wren .console.trig.rden \
label .console.trig.pnum -text {Pre-Capture:}
entry .console.trig.trigvalue_pnum -textvar triggerPnum -width 4
pack .console.trig.pnum .console.trig.trigvalue_pnum \
.console.trig.wren .console.trig.rden \
.console.trig.trigaddr .console.trig.trigvalue_addr \
.console.trig.trigdata .console.trig.trigvalue_data \
.console.trig.starttrig \
-side left -ipadx 0
initTrigConfig
 
# set the control buttons
frame .console.fifo -relief groove -borderwidth 5
/trunk/sim/altera/virtual_jtag_stimulus.tcl
114,7 → 114,7
}
}
 
proc config_trig {{jtag_index_2 2} {trig 00000000000000}} {
proc config_trig {{jtag_index_2 2} {trig 00000000000000} {pnum 0}} {
global log
set trig_leng [string length $trig]
if {$trig_leng!=14} {
123,6 → 123,8
#device_lock -timeout 5
#device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value
#set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig -length 56 -value_in_hex]
#device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 2 -no_captured_ir_value
#set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $pnum -length 10]
#device_unlock
global trig_sim_act
global trig_sim_num
133,6 → 135,12
append trig_sim_act (0,2,$trig,[format "%X" 56]),
set trig_sim_num [expr $trig_sim_num+1]
set trig_sim_len [expr $trig_sim_len+56]
append trig_sim_act (0,1,2,[format "%X" 2]),
set trig_sim_num [expr $trig_sim_num+1]
set trig_sim_len [expr $trig_sim_len+2]
append trig_sim_act (0,2,[format "%X" $pnum],[format "%X" 10]),
set trig_sim_num [expr $trig_sim_num+1]
set trig_sim_len [expr $trig_sim_len+10]
return 0
}
}
269,6 → 277,7
proc initTrigConfig {} {
global triggerAddr
global triggerData
global triggerPnum
if {[set triggerAddr]==""} {
set triggerAddr ffff
}
275,11 → 284,15
if {[set triggerData]==""} {
set triggerData a5a5a5a5
}
if {[set triggerPnum]==""} {
set triggerPnum 0
}
}
 
proc updateTrigger {{trigCmd 0}} {
global triggerAddr
global triggerData
global triggerPnum
global trig_wren
global trig_rden
global trig_aden
288,7 → 301,7
append triggerValue [format "%1X" [expr $trig_wren*8+$trig_rden*4+$trigCmd]]
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue
config_trig 2 $triggerValue $triggerPnum
}
 
proc startTrigger {} {
299,8 → 312,8
set trigEnable [expr $trig_wren+$trig_rden+$trig_aden+$trig_daen]
if {$trigEnable>0} {
updateTrigger 2
#reset_fifo 0
#query_usedw 0
reset_fifo 0
query_usedw 0
updateTrigger 3
} else {
updateTrigger 0
319,7 → 332,7
proc read_fifo_content {} {
global log
global fifoUsedw
#$log insert end "\n****************************************\n"
$log insert end "\n****************************************\n"
for {set i 0} {$i<$fifoUsedw} {incr i} {
set fifoContent [read_fifo 0]
set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
515,7 → 528,10
checkbutton .console.trig.trigdata -text {@Data:} -variable trig_daen
checkbutton .console.trig.wren -text {@WR} -variable trig_wren
checkbutton .console.trig.rden -text {@RD} -variable trig_rden
pack .console.trig.wren .console.trig.rden \
label .console.trig.pnum -text {Pre-Capture:}
entry .console.trig.trigvalue_pnum -textvar triggerPnum -width 4
pack .console.trig.pnum .console.trig.trigvalue_pnum \
.console.trig.wren .console.trig.rden \
.console.trig.trigaddr .console.trig.trigvalue_addr \
.console.trig.trigdata .console.trig.trigvalue_data \
.console.trig.starttrig \
/trunk/sim/altera/wave.do
41,6 → 41,12
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_out
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_num
add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_cnt
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_full
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_wr
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_rd
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_trig/sld_virtual_jtag_component/user_input/vj_sim_done
add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_addr_mask/sld_virtual_jtag_component/user_input/vj_sim_done
47,7 → 53,7
add wave -noupdate -divider {New Divider}
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {388925000 ps} 0}
WaveRestoreCursors {{Cursor 1} {11169937 ps} 0}
configure wave -namecolwidth 147
configure wave -valuecolwidth 100
configure wave -justifyvalue left
62,4 → 68,4
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {14421760 ps}
WaveRestoreZoom {0 ps} {10500 ns}

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