URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
Subversion Repositories bustap-jtag
Compare Revisions
- This comparison shows the changes necessary to convert path
/bustap-jtag
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/rtl/altera/virtual_jtag_addr_mask.v
13,7 → 13,7
// Virtual JTAG. |
//************************************************************** |
|
`include "../../sim/altera/jtag_sim_define.h" |
`include "jtag_sim_define.h" |
`timescale 1ns/1ns |
|
module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 , |
165,8 → 165,14
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 1, |
sld_virtual_jtag_component.sld_ir_width = 2, |
`ifdef USE_SIM_STIMULUS |
sld_virtual_jtag_component.sld_sim_action = `ADDR_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `ADDR_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `ADDR_SLD_SIM_T_LENG; |
`else |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
`endif |
|
endmodule |
/trunk/rtl/altera/virtual_jtag_adda_fifo.v
13,7 → 13,7
// via Virtual JTAG. |
//************************************************************** |
|
`include "../../sim/altera/jtag_sim_define.h" |
`include "jtag_sim_define.h" |
`timescale 1ns/1ns |
|
module virtual_jtag_adda_fifo(clk,wr_en,data_in); |
166,8 → 166,14
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 0, |
sld_virtual_jtag_component.sld_ir_width = 2, |
`ifdef USE_SIM_STIMULUS |
sld_virtual_jtag_component.sld_sim_action = `FIFO_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `FIFO_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `FIFO_SLD_SIM_T_LENG; |
`else |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
`endif |
|
endmodule |
/trunk/rtl/altera/virtual_jtag_adda_trig.v
13,7 → 13,7
// via Virtual JTAG. |
//************************************************************** |
|
`include "../../sim/altera/jtag_sim_define.h" |
`include "jtag_sim_define.h" |
`timescale 1ns/1ns |
|
module virtual_jtag_adda_trig(trig_out); |
93,8 → 93,14
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 2, |
sld_virtual_jtag_component.sld_ir_width = 2, |
`ifdef USE_SIM_STIMULUS |
sld_virtual_jtag_component.sld_sim_action = `TRIG_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `TRIG_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `TRIG_SLD_SIM_T_LENG; |
`else |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
`endif |
|
endmodule |
/trunk/rtl/altera/jtag_sim_define.h
0,0 → 1,16
`define USE_SIM_STIMULUS |
|
`define FIFO_SLD_SIM_ACTION "((1,1,1,2))" |
`define FIFO_SLD_SIM_N_SCAN 1 |
`define FIFO_SLD_SIM_T_LENG 2 |
|
`define ADDR_SLD_SIM_ACTION "((1,1,1,2))" |
`define ADDR_SLD_SIM_N_SCAN 1 |
`define ADDR_SLD_SIM_T_LENG 2 |
|
`define TRIG_SLD_SIM_ACTION "((1,1,1,2))" |
`define TRIG_SLD_SIM_N_SCAN 1 |
`define TRIG_SLD_SIM_T_LENG 2 |
|
|
|
/trunk/sim/altera/jtag_sim_define.h
File deleted
/trunk/sim/altera/virtual_jtag_stimulus.tcl
380,6 → 380,7
set trig_sim_num [expr $trig_sim_num+1] |
set trig_sim_len [expr $trig_sim_len+2] |
$log delete 1.0 end |
$log insert end "`define USE_SIM_STIMULUS\n\n" |
$log insert end "`define FIFO_SLD_SIM_ACTION $fifo_sim_act\n" |
$log insert end "`define FIFO_SLD_SIM_N_SCAN $fifo_sim_num\n" |
$log insert end "`define FIFO_SLD_SIM_T_LENG $fifo_sim_len\n\n" |
390,7 → 391,7
$log insert end "`define TRIG_SLD_SIM_N_SCAN $trig_sim_num\n" |
$log insert end "`define TRIG_SLD_SIM_T_LENG $trig_sim_len\n\n" |
|
set fileId [open jtag_sim_define.h w] |
set fileId [open ../../rtl/altera/jtag_sim_define.h w] |
puts $fileId [$log get 1.0 end] |
close $fileId |
} |
/trunk/sim/altera/sim.do
11,9 → 11,9
|
# compile altera virtual jtag files |
source virtual_jtag_stimulus.tcl |
vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v |
vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v |
vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v |
vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v +incdir+../../rtl/altera |
vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v +incdir+../../rtl/altera |
vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v +incdir+../../rtl/altera |
vlog -work work altera_mf.v |
|
# compile testbench files |
35,7 → 35,7
up_bfm_sv.obj -L $::env(MODEL_TECH) -lmtipli |
|
# compile jtag bfms files |
vlog -work work -sv jtag_bfm_sv.v |
vlog -work work -sv jtag_bfm_sv.v +incdir+../../rtl/altera |
|
vsim -novopt \ |
-sv_lib up_bfm_c \ |