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URL https://opencores.org/ocsvn/c16/c16/trunk

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    /c16/tags/V10/vhdl
    from Rev 3 to Rev 26
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Rev 3 → Rev 26

/select_yy.vhd
0,0 → 1,100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity select_yy is
Port( SY : in std_logic_vector( 3 downto 0);
IMM : in std_logic_vector(15 downto 0);
QUICK : in std_logic_vector( 3 downto 0);
M_RDAT : in std_logic_vector( 7 downto 0);
IO_RDAT : in std_logic_vector( 7 downto 0);
RR : in std_logic_vector(15 downto 0);
YY : out std_logic_vector(15 downto 0)
);
end select_yy;
 
architecture Behavioral of select_yy is
 
function b4(A : std_logic) return std_logic_vector is
begin
return A & A & A & A;
end;
 
function b8(A : std_logic) return std_logic_vector is
begin
return b4(A) & b4(A);
end;
 
begin
 
-- bits 1..0
--
s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), M_RDAT(1 downto 0),
IO_RDAT(1 downto 0), RR(1 downto 0))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0);
when SY_RR => YY(1 downto 0) <= RR (1 downto 0);
when SY_SQ | SY_UQ => YY(1 downto 0) <= QUICK (1 downto 0);
when SY_SM | SY_UM => YY(1 downto 0) <= M_RDAT (1 downto 0);
when SY_IO => YY(1 downto 0) <= IO_RDAT(1 downto 0);
when others => YY(1 downto 0) <= SY (1 downto 0);
end case;
end process;
 
-- bits 3..2
--
s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), M_RDAT(3 downto 2),
IO_RDAT(3 downto 2), RR(3 downto 2))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2);
when SY_RR => YY(3 downto 2) <= RR (3 downto 2);
when SY_SQ | SY_UQ => YY(3 downto 2) <= QUICK (3 downto 2);
when SY_SM | SY_UM => YY(3 downto 2) <= M_RDAT (3 downto 2);
when SY_IO => YY(3 downto 2) <= IO_RDAT(3 downto 2);
when others => YY(3 downto 2) <= "00";
end case;
end process;
 
-- bits 7..4
--
s_7_4: process(SY, IMM(7 downto 4), QUICK(3), M_RDAT(7 downto 4),
IO_RDAT(7 downto 4), RR(7 downto 4))
begin
case SY is
when SY_I16 | SY_SI8
| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4);
when SY_RR => YY(7 downto 4) <= RR (7 downto 4);
when SY_SQ => YY(7 downto 4) <= b4(QUICK(3));
when SY_SM | SY_UM => YY(7 downto 4) <= M_RDAT (7 downto 4);
when SY_IO => YY(7 downto 4) <= IO_RDAT(7 downto 4);
when others => YY(7 downto 4) <= "0000";
end case;
end process;
 
-- bits 15..8
--
s_15_8: process(SY, IMM(15 downto 7), QUICK(3), M_RDAT(7), RR(15 downto 8))
begin
case SY is
when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8);
when SY_SI8 => YY(15 downto 8) <= b8(IMM(7));
when SY_RR => YY(15 downto 8) <= RR(15 downto 8);
when SY_SQ => YY(15 downto 8) <= b8(QUICK(3));
when SY_SM => YY(15 downto 8) <= b8(M_RDAT(7));
when others => YY(15 downto 8) <= "00000000";
end case;
end process;
 
end Behavioral;
/BaudGen.vhd
0,0 → 1,57
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
use STD.TEXTIO.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity BaudGen is
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
Port( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : out std_logic
);
end BaudGen;
 
architecture Behavioral of BaudGen is
 
-- divide bg_clock_freq and bg_baud_rate
-- by their common divisor...
--
function gcd(M, N: integer) return integer is
begin
if ((M mod N) = 0) then return N;
else return gcd(N, M mod N);
end if;
end;
constant common_div : integer := gcd(bg_clock_freq, 16 * bg_baud_rate);
constant clock_freq : integer := bg_clock_freq / common_div;
constant baud_freq : integer := 16 * bg_baud_rate / common_div;
constant limit : integer := clock_freq - baud_freq;
 
signal COUNTER : integer range 0 to clock_freq - 1;
 
begin
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_16 <= '0'; -- make CE_16 stay on for (at most) one cycle
 
if (CLR = '1') then
COUNTER <= 0;
elsif (COUNTER >= limit) then
CE_16 <= '1';
COUNTER <= COUNTER - limit;
else
COUNTER <= COUNTER + baud_freq;
end if;
end if;
end process;
 
end Behavioral;
/cpu16.npl
0,0 → 1,63
JDF F
// Created by Project Navigator ver 1.0
PROJECT cpu16
DESIGN cpu16 Normal
DEVFAM virtexe
DEVFAMTIME 1064066933
DEVICE xcv100e
DEVICETIME 1064066933
DEVPKG pq240
DEVPKGTIME 1064066933
DEVSPEED -6
DEVSPEEDTIME 1064065691
FLOW XST VHDL
FLOWTIME 0
STIMULUS test.vhd Normal
STIMULUS cpu_test.vhd Normal
MODULE memory.vhd
MODSTYLE memory Normal
MODULE uart_rx.vhd
MODSTYLE uart_rx Normal
MODULE uart_tx.vhd
MODSTYLE uart_tx Normal
MODULE alu8.vhd
MODSTYLE alu8 Normal
MODULE cpu.vhd
MODSTYLE cpu16 Normal
MODULE temperature.vhd
MODSTYLE temperature Normal
MODULE cpu_engine.vhd
MODSTYLE cpu_engine Normal
MODULE data_core.vhd
MODSTYLE data_core Normal
MODULE uart.vhd
MODSTYLE uart Normal
MODULE uart._baudgen.vhd
MODSTYLE uart_baudgen Normal
MODULE opcode_decoder.vhd
MODSTYLE opcode_decoder Normal
MODULE opcode_fetch.vhd
MODSTYLE opcode_fetch Normal
MODULE select_yy.vhd
MODSTYLE select_yy Normal
MODULE Board_cpu.vhd
MODSTYLE board_cpu Normal
MODULE BaudGen.vhd
MODSTYLE baudgen Normal
MODULE input_output.vhd
MODSTYLE input_output Normal
MODULE ds1722.vhd
MODSTYLE ds1722 Normal
MODULE bin_to_7segment.vhd
MODSTYLE bin_to_7segment Normal
LIBFILE mem_content.vhd work ***
LIBFILE cpu_pack.vhd work ***
DEPASSOC board_cpu board_cpu.ucf SYSTEM
[Normal]
p_ModelSimSignalWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
p_ModelSimStructWin=xstvhd, virtexe, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1056198882, False
_SynthExtractROM=xstvhd, virtexe, Schematic.t_synthesize, 1064066560, False
[STATUS-ALL]
board_cpu.ngcFile=WARNINGS,1064942956
[STRATEGY-LIST]
Normal=True
/mem_content.vhd
0,0 → 1,300
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package mem_content is
 
-- content of m_0_0
constant m_0_0_0 : BIT_VECTOR := X"E2BF124C93051303CFCCAC2652AEC692651B64AB6F4B926C081C0804080004D8";
constant m_0_0_1 : BIT_VECTOR := X"3FECF52100000231E7622B29268922F7931543E3664B3853387CEE7E65615B26";
constant m_0_0_2 : BIT_VECTOR := X"A3DF7793B9EFA732AAA25225224A0504A18029D278325DA4C200000709A03C38";
constant m_0_0_3 : BIT_VECTOR := X"16FB6E31C79C5674A32FF38CBCDDCC3AC9249D44A8BC952CC48B890935196A2A";
constant m_0_0_4 : BIT_VECTOR := X"9747FF77CA23FDFFD5BFFD5AA5FFEAD447FFAB5019BBED52FFDD5F2099A8D485";
constant m_0_0_5 : BIT_VECTOR := X"BEBDD5F1A999ABDED9BDB7E3C3C87F7FECF6FFECF7BDB97FF67BDED8BFFB3DEF";
constant m_0_0_6 : BIT_VECTOR := X"F5795E5795A769DE72DEF5AFDAA92E593BEBF001E1A9DD5E15659B6EFA4B6B57";
constant m_0_0_7 : BIT_VECTOR := X"C979FFA375642725E137AB37725E7FE8DD5909287E2725E7FECDD49094D55FD7";
constant m_0_0_8 : BIT_VECTOR := X"CC29BD98577B30A6F6615DECC5056F6418B3E6AF158EE4EE2725E7FE8DD49096";
constant m_0_0_9 : BIT_VECTOR := X"A9468AB07F9A8DD52A43627DAB64EFEB6142615DECC29BD98577B30A6F6615DE";
constant m_0_0_A : BIT_VECTOR := X"C37F407497FFC07C6F39FD9ABA7747C65D0AB43A1468556A56BA4AF04870D26E";
constant m_0_0_B : BIT_VECTOR := X"D5A1521A956A49666EFB555B43EA964B4EA54B4A2940E47252C115963FB6E0D3";
constant m_0_0_C : BIT_VECTOR := X"D914D4D3FF4DEE6A66D4D4B6A6A514D4AA6A5352B4F696CACD252979E92D4A92";
constant m_0_0_D : BIT_VECTOR := X"FB783C1E0F07825B7DA5A8B56DFEB66D412888104BF52A4192884BC2D115A6FD";
constant m_0_0_E : BIT_VECTOR := X"D949482400AE5242865241948065201242A2A48250A884F290DF6942A59554A6";
constant m_0_0_F : BIT_VECTOR := X"E37FFEB6A42ADBBBB776EDDCABFC921BF5B5247F1241E46A40934A52921525BE";
 
-- content of m_0_1
constant m_0_1_0 : BIT_VECTOR := X"80710228CA648A1C4AC88A359072F4E3512A2443C653894400000400080005F8";
constant m_0_1_1 : BIT_VECTOR := X"2CDA76114000020319D9E2815261D81190833D5B640CA648A1C4A25E44519435";
constant m_0_1_2 : BIT_VECTOR := X"584711D108232251871523DA353AE97B250035ADC4767BADF1000005A216E21B";
constant m_0_1_3 : BIT_VECTOR := X"227805D04096659DA10D7682C82A834F48844968961CC087A661488CA5A921C7";
constant m_0_1_4 : BIT_VECTOR := X"9050A52548A93452D3052D320429699010A5A64449CAD232525737A0D57AFD47";
constant m_0_1_5 : BIT_VECTOR := X"AF3C7AC2F0A8C7203045C2290F304D14A6AA14A6AB2A8B0A535594448529AACA";
constant m_0_1_6 : BIT_VECTOR := X"EF694EF694EF295EF2F7FDAFA41022C42AF0C8000EF6C7AD2F13A802BD1890E0";
constant m_0_1_7 : BIT_VECTOR := X"6156F7D6D11BD9855C9BA46D1855BDF1B446F6279219855BDF1B4C4E486CF694";
constant m_0_1_8 : BIT_VECTOR := X"633522C66E458CDC8B19A9163426C8B0464D9A22FF7BB0ABD9855BDF1B4C4E4A";
constant m_0_1_9 : BIT_VECTOR := X"A4EE4A88CA560B349EA159FA54B0ABB499BD99A91633522C66E458CDC8B19A91";
constant m_0_1_A : BIT_VECTOR := X"88093E5F9081BE5F9F2CA1A53F15F2360FDF1F9FBF3F1F3E7EEF2788D45AB659";
constant m_0_1_B : BIT_VECTOR := X"0F9B3A81D327503B7334ADACDE1FC8E55E10E44B0CAE7331395EC7A39F805D7E";
constant m_0_1_C : BIT_VECTOR := X"6BAC675508C62DA3AACC670263384C676633B79DCE03B9D45321990CBD7C99D6";
constant m_0_1_D : BIT_VECTOR := X"26F47A3D1E8F472B1372BDCC034A00E323915631F0E65688A40DF5FF3BCE6466";
constant m_0_1_E : BIT_VECTOR := X"A944E733BE62199C6A39D88E746399D9984833392E4E6BE9CEC4DCAAB2230E56";
constant m_0_1_F : BIT_VECTOR := X"F49B5E4973A800AD5564D56C292E39D350019D254333583B3249792C4E1F9989";
 
-- content of m_0_2
constant m_0_2_0 : BIT_VECTOR := X"094339A22811E831226222911943600815C01222E322D910000000040FFFFAD8";
constant m_0_2_1 : BIT_VECTOR := X"8021119540000264311108A4D1D45A49D84AB11170E2851E8712291311144691";
constant m_0_2_2 : BIT_VECTOR := X"3D374DDCCE9BB99CF4C89A01A01246517C0028D20D0300221940000404400681";
constant m_0_2_3 : BIT_VECTOR := X"810CD0934E45111006D2F323B23B637CA7D346F226C3D1A0516CA6A28BC21314";
constant m_0_2_4 : BIT_VECTOR := X"0B8A117245658508C3508C357284618A8A1186AA2C85C8D8882CD34A228540D4";
constant m_0_2_5 : BIT_VECTOR := X"5943E85C8A2008F70B2E687C38E7E1422E41422E41905CA11720C92F508B9064";
constant m_0_2_6 : BIT_VECTOR := X"4212908421480090004B1283B5B966C925DE97FFF9D83E8540F220416447DC3C";
constant m_0_2_7 : BIT_VECTOR := X"49BDDA54D2B72126FB52A54D126F769534ADC8973A9126F769134BFDA8488400";
constant m_0_2_8 : BIT_VECTOR := X"309790612B20C2564184AC830C52E418E1E3061C321924972126F769134BFDAA";
constant m_0_2_9 : BIT_VECTOR := X"2216631A98006004406B91BB5124972684B204AC8309590612F20C25E4184BC8";
constant m_0_2_A : BIT_VECTOR := X"4A211611561106100323C842E00B1C5E1C78C138718250A30EB8101A0D440300";
constant m_0_2_B : BIT_VECTOR := X"19B762E317AC5477A1F22570D9185A2D04342D13D5AE2699AB1EEC0149842C44";
constant m_0_2_C : BIT_VECTOR := X"E95497EE4949856BF25497E524BF1497EA4BD61A5CFE0BD8A6A5B53D914DFB17";
constant m_0_2_D : BIT_VECTOR := X"F60D068341A0D168FB16349044226A2428B156294B113F4AD29C4BB17B62F753";
constant m_0_2_E : BIT_VECTOR := X"A54C2D563E732B5A730B5EC2C770B12B1A5A56396D4562385A3EC58AD6ABA2C1";
constant m_0_2_F : BIT_VECTOR := X"C36DEC041630105D0BAD42EE59AC8B5B4022B535156365F16B6D129184F0B07D";
 
-- content of m_0_3
constant m_0_3_0 : BIT_VECTOR := X"0006843D0F080F409E1D1E5F1004CFC4F5074E20000011F80C0C0C0C000000C9";
constant m_0_3_1 : BIT_VECTOR := X"0CD2700740000109524077C210821021C00020405E10F080F40BE4F0E8F23C5F";
constant m_0_3_2 : BIT_VECTOR := X"28A7A1C00043800020044044044B6099BF800892559008B04060000106602AD8";
constant m_0_3_3 : BIT_VECTOR := X"10204088A13C8F26D0807802802A03721D084001040001020840909080000200";
constant m_0_3_4 : BIT_VECTOR := X"6121110490004488BB088BB000445DA10111768402088800884442241140C459";
constant m_0_3_5 : BIT_VECTOR := X"88054C008C465A2200603120BA379122209C22209C270A11104E128008882709";
constant m_0_3_6 : BIT_VECTOR := X"31CC731CE67B8EF399A5215935B92A5BC88137FFF96054C00111404232488000";
constant m_0_3_7 : BIT_VECTOR := X"9ED7DB6CD5166A7B5112AECD67B5F6DB35459A569D0A7B5F6DB35559AD99B9CF";
constant m_0_3_8 : BIT_VECTOR := X"9654272CA84E59509CB2A13965CA89CB2DF9F2E990C84F226A7B5F6DF35559AD";
constant m_0_3_9 : BIT_VECTOR := X"B4E7828B938683369A2EF4934B4F2246B2A6B2B139656272CA84E59509CB2A13";
constant m_0_3_A : BIT_VECTOR := X"DA1165E7451175E613AC8806CE11212710C91321932642644FC4A6AB45983619";
constant m_0_3_B : BIT_VECTOR := X"4C1833C98346713183A231309912AD57EC2057C00AD8443015F089D098044A1D";
constant m_0_3_C : BIT_VECTOR := X"7D86076808605923B246072030398607230396D8EFFC9DB80231919C39E0819C";
constant m_0_3_D : BIT_VECTOR := X"BF75BA5D6EB74AB55FABCC984223222E0D5F7475424B76C8F74D4663BF076C07";
constant m_0_3_E : BIT_VECTOR := X"E0A856ABE24015F06015B0056C015B15F0606B65887252C8AF57EAFD2BEF357A";
constant m_0_3_F : BIT_VECTOR := X"64891C042B60108F9124647C0C8C95E840215B9192B645CEBE498A5292E55EAF";
 
-- content of m_0_4
constant m_0_4_0 : BIT_VECTOR := X"00848018060306401898780C00840DC0C0461C20800010CC180C080C07FFF811";
constant m_0_4_1 : BIT_VECTOR := X"4C814146000001000211460000800600E08000014C006430600180C4C3C0F00C";
constant m_0_4_2 : BIT_VECTOR := X"200380E09001C120298C92C92C9B24480300000001B2990284600000064000D8";
constant m_0_4_3 : BIT_VECTOR := X"10014208A0303C2200A07A48A08A5800B9000500618231604018800014010200";
constant m_0_4_4 : BIT_VECTOR := X"210050F1B09000282082820A2814105100504145000028448C00406132050118";
constant m_0_4_5 : BIT_VECTOR := X"04202449CC440810612531088000000A1E340A1E358D00050F1AC68002878D63";
constant m_0_4_6 : BIT_VECTOR := X"6B58C6B5AD210A42918D695B74CB6ECBC0419000000802449809414010404994";
constant m_0_4_7 : BIT_VECTOR := X"5E00493A0C40E97805060BA05780124E83103A12B409780124E83103A50A158C";
constant m_0_4_8 : BIT_VECTOR := X"82018D04031A080634100C682F406341048B568CB65B2F00E9780124A83103A7";
constant m_0_4_9 : BIT_VECTOR := X"2297422300865324508C8437492F0127900E900C682018D04031A080634100C6";
constant m_0_4_A : BIT_VECTOR := X"530050C04050D0C003A20C20020010971C48913811227160C722142311843099";
constant m_0_4_B : BIT_VECTOR := X"0D983381B3467A19018A30320D402513802C13A80270241004A0001003142001";
constant m_0_4_C : BIT_VECTOR := X"1D86076828601003B246073030394607230396DC470008B21231918419ECC19C";
constant m_0_4_D : BIT_VECTOR := X"19008040603018940489C60060A0A00A8C4A224CB18000080111B03117022E43";
constant m_0_4_E : BIT_VECTOR := X"44A81289C00404A60404A90128404E84A60609C0002000002501225509492128";
constant m_0_4_F : BIT_VECTOR := X"2008011409545002000400100A8084EE08A04E50909C040094009294A6004A06";
 
-- content of m_0_5
constant m_0_5_0 : BIT_VECTOR := X"528E81485241520A28282814528C94914452148AA94A42540400000407FFF855";
constant m_0_5_1 : BIT_VECTOR := X"220104224000010146514A28A2A8A28ACA944A531405201520A2814141405114";
constant m_0_5_2 : BIT_VECTOR := X"8A2B8ACA8515950A28AA90A90A9344953900089251A055269260000141092840";
constant m_0_5_3 : BIT_VECTOR := X"04A32A28A050146680A93A4225200232A822955428A29428428A8505155148A8";
constant m_0_5_4 : BIT_VECTOR := X"64344AF1D2AA082504225040A5128204144A08145028250425414244AA0D1419";
constant m_0_5_5 : BIT_VECTOR := X"82151128A1112288108484AA728F82095E34895E358D2944AF1AC791A2578D63";
constant m_0_5_6 : BIT_VECTOR := X"635AC6B1AD6B58C6B18C63084A201800282247FFF52151120504532A0A082042";
constant m_0_5_7 : BIT_VECTOR := X"014124892D04940506E11892C05049224B41250A4D2405049224B4125108B18D";
constant m_0_5_8 : BIT_VECTOR := X"880B8D10171A202E34405C68830163441020C1AA010080A09405049264B41251";
constant m_0_5_9 : BIT_VECTOR := X"020748A13210088042065284A000A0894049405C6880B8D10171A202E34405C6";
constant m_0_5_A : BIT_VECTOR := X"3142D144544A41442B0A250AC85042864552A51A840A3448970210A140908044";
constant m_0_5_B : BIT_VECTOR := X"D5A1530AB56A6B480A89415095128141808541AAA832A15250651944A0328295";
constant m_0_5_C : BIT_VECTOR := X"3410910A6509024890109114848810910848828481FC902A8524493229A55A9A";
constant m_0_5_D : BIT_VECTOR := X"9951A8D46A151A054CA04A212894952A4D0223450400101C01FF00520D141A15";
constant m_0_5_E : BIT_VECTOR := X"456140A0CAA15062815068541A1502102282A0CA52829482835328332040040A";
constant m_0_5_F : BIT_VECTOR := X"204110B2A042CA8610468435A2501062A595064A820CA1CA0492108424E502A6";
 
-- content of m_0_6
constant m_0_6_0 : BIT_VECTOR := X"516CAA4E935593534C4EADA6516C66DA641B46AA4E4A9A600000000407FFF859";
constant m_0_6_1 : BIT_VECTOR := X"0CEB6412000001484604134D284D2AD2D21B521366A935593534DA62756D59A6";
constant m_0_6_2 : BIT_VECTOR := X"B34BD2D289A5A51296ACC0CC0CDB709981800A52109A0892512000001660085C";
constant m_0_6_3 : BIT_VECTOR := X"16AA4A2AAA9B5662240D7A10800A00800DB49466AAA8D5AA54AA296941946B36";
constant m_0_6_4 : BIT_VECTOR := X"742692719A82AB496434964281A4B2140692C85412A049402901093011A49008";
constant m_0_6_5 : BIT_VECTOR := X"021015A82DDDA88A14B0B68340882AD24E36D24E378DA869271BC7D534938DE3";
constant m_0_6_6 : BIT_VECTOR := X"214A5210A5294A5231AC6B1D92ADAB61A02040000109015A84441A4808622042";
constant m_0_6_7 : BIT_VECTOR := X"0D012499244524340921499243404926491149A95514340492649114930A94A4";
constant m_0_6_8 : BIT_VECTOR := X"E8A98DD1531BA2A637454C6E8515637450A142A2110886812434049264911493";
constant m_0_6_9 : BIT_VECTOR := X"B6C74A2120974336D8040299200680824552454C6E8A98DD1531BA2A637454C6";
constant m_0_6_A : BIT_VECTOR := X"126A52611692D261232029A8004042065D52A52AA54A550A1700B6010080B819";
constant m_0_6_B : BIT_VECTOR := X"90A2431215086840A81250400000211184B511A32234A6514469501722A48484";
constant m_0_6_C : BIT_VECTOR := X"1016D423496DB24A1356D426B6A156D42B6A1A1023000468D5254922018D1218";
constant m_0_6_D : BIT_VECTOR := X"0B0080402010088C058842A14D25241A24426644FBFC0F03C1DCF8108D111810";
constant m_0_6_E : BIT_VECTOR := X"D16D1088D4A2446AA2446091182446046A8A885294ACA4022101623308CC3118";
constant m_0_6_F : BIT_VECTOR := X"2248842488C092028054A0102C94C42AA12442929884A60084921AD6B7004202";
 
-- content of m_0_7
constant m_0_7_0 : BIT_VECTOR := X"0080010842414248282829141080148141020400210040400000000400000241";
constant m_0_7_1 : BIT_VECTOR := X"0A8340020000000800150A208A208208C8840800140420142082914141485014";
constant m_0_7_2 : BIT_VECTOR := X"082388C804119008888210210203148401000240008804020020000015400054";
constant m_0_7_3 : BIT_VECTOR := X"0021220000521400008038400402400088020010208010200208044440400088";
constant m_0_7_4 : BIT_VECTOR := X"6020484010800224000240002012000100480000000024000400091008040108";
constant m_0_7_5 : BIT_VECTOR := X"0000000800000082041400200080008908040908040100048402008002420100";
constant m_0_7_6 : BIT_VECTOR := X"214A52948421084210A521084804892800081000040000000000012000200000";
constant m_0_7_7 : BIT_VECTOR := X"4010000804409100448048805004000201102400040100400020100241421084";
constant m_0_7_8 : BIT_VECTOR := X"8202010404020808041010082140004104085080804020009100400020100241";
constant m_0_7_9 : BIT_VECTOR := X"06874021008542A0D08410048920002910091010082020104040208080410100";
constant m_0_7_A : BIT_VECTOR := X"11005141004851410B0000020200109604000008000010000700342110802815";
constant m_0_7_B : BIT_VECTOR := X"04881340900260000009000000000300A0040080801201000024000080120204";
constant m_0_7_C : BIT_VECTOR := X"1480010024000000810001000008000100008A00030000680120090009A4409A";
constant m_0_7_D : BIT_VECTOR := X"090080402010080C0480C208209091100406664C00000000000000100D001A00";
constant m_0_7_E : BIT_VECTOR := X"406001804A210022210028400A10028022220048420210000101203300C82018";
constant m_0_7_F : BIT_VECTOR := X"2248801200D04802801020140244406200900648080C22000C00000001000602";
 
-- content of m_1_0
constant m_1_0_0 : BIT_VECTOR := X"E5E0924F05AD3BEC52829CFDAFFF7EFFAF2B5FD201E0900D20B7B41DE0924832";
constant m_1_0_1 : BIT_VECTOR := X"04A24A04964929EFCFD28E74A2E9673A5934F4A39D2CABA4B16D65E03F249241";
constant m_1_0_2 : BIT_VECTOR := X"8A412056D752A9E02F7BD752A9E02F73D09E0F04824124920C0E9E0944555535";
constant m_1_0_3 : BIT_VECTOR := X"000001E3C3777EAB7773F56EEC7BADDDCA9078241EA78249549176D5B5AA48A4";
constant m_1_0_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_8 : BIT_VECTOR := X"880140807C6807C6803A2C000000000000000000000000000000000000000000";
constant m_1_0_9 : BIT_VECTOR := X"801CE4B9C536A49F2B8E0029E91F562502C2982B550056AA53E19B235C46394F";
constant m_1_0_A : BIT_VECTOR := X"4895717C7129B6C4810133C1085B924C90C9A388000A2E3310AE4EA0AE239675";
constant m_1_0_B : BIT_VECTOR := X"5F47CD474F6ABF32B73D539E882248FB762D558A32E44D0BC944CC72B4B9571C";
constant m_1_0_C : BIT_VECTOR := X"E31C831C849DC891DC85115F2D5048D56322B9195BD5AB46ADECC8F355D5C2EE";
constant m_1_0_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000724AC77C";
constant m_1_0_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_0_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_1
constant m_1_1_0 : BIT_VECTOR := X"931179D88A1ECA9082DEDFAD29DAD2BDE73BDB351F10CCEB5038631311CCD440";
constant m_1_1_1 : BIT_VECTOR := X"8E75677ACCF79C1D7439D3AE751CEDD732FB0E74EB98965E76CA305BF95E76A3";
constant m_1_1_2 : BIT_VECTOR := X"B6A351492202815BFC9F2AA6D35BFC972F31188E46A04135100EF11CCB2AAA84";
constant m_1_1_3 : BIT_VECTOR := X"0000017E215953EA557A7D4AAD4AA955A9A8C46A22DC432A0654255320A32A32";
constant m_1_1_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000100000";
constant m_1_1_8 : BIT_VECTOR := X"A8012080330804A680330E000000000000000000000000000000000000000000";
constant m_1_1_9 : BIT_VECTOR := X"4002C943DB0B492E3096001832E8624B8480A04C660098CC30608537586EB0C1";
constant m_1_1_A : BIT_VECTOR := X"1C296235629D20280E24574421100489948022940017300000309420C2110A65";
constant m_1_1_B : BIT_VECTOR := X"281B8D0AC168C81056346B1A310501494C08881022608086110808A034380628";
constant m_1_1_C : BIT_VECTOR := X"C12009200829420294112FA852B801220084980466090502130081034601826C";
constant m_1_1_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000601988A0";
constant m_1_1_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_1_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_2
constant m_1_2_0 : BIT_VECTOR := X"78348B01A5C785C90F250000520425210042148348355AE034FD8E38345A0D3F";
constant m_1_2_1 : BIT_VECTOR := X"A2C2AD5558A8B4611C4B48E2D2258471691E12C238B1CBAAD4E48139EF22C068";
constant m_1_2_2 : BIT_VECTOR := X"B06834A086360939E3B0E6360939E3B0E08341A2E06B64834FFC8345A5575508";
constant m_1_2_3 : BIT_VECTOR := X"0000011068B0B9220B0204416040882C481A0D069F20D57ACAF4720392157357";
constant m_1_2_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_2_8 : BIT_VECTOR := X"88016000664807C6001F28000000000000000000000000000000000000000000";
constant m_1_2_9 : BIT_VECTOR := X"001A14B8F744A490B4BC0028C9FA6B2F864E18707800E0F051ABA26E02DC0546";
constant m_1_2_A : BIT_VECTOR := X"0DCC09C009E81544850F2E8F7BC35245A859C118001F167733964B40D2B69009";
constant m_1_2_B : BIT_VECTOR := X"53442C5546623A5A208110408863F0A6376165CA01424E83C8E42256899DF194";
constant m_1_2_C : BIT_VECTOR := X"159D859D871619E1618B9F9329D988D9752A50A913CBAAECA9E22AEB117C6141";
constant m_1_2_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000000B8DDF4C";
constant m_1_2_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_2_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_3
constant m_1_3_0 : BIT_VECTOR := X"155615EA90AC88E810208563085694842148C6112952AF9D12B0BB5152AD44CF";
constant m_1_3_1 : BIT_VECTOR := X"357856D0ADA15F117515ABA5788AF5D2B432456AE95EA2056C89515CA9057A2D";
constant m_1_3_2 : BIT_VECTOR := X"E22516808E995E5CA8922E995E5CA89220956A956A252D9133F2152AD1061028";
constant m_1_3_3 : BIT_VECTOR := X"00000052A51D1C621102AC42225188444A8955A2E5A54AB7456C44EA2542B62B";
constant m_1_3_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_8 : BIT_VECTOR := X"D00141002E3800D3806552000000000000000000000000000000000000000000";
constant m_1_3_9 : BIT_VECTOR := X"800A8DE26151EDB41A14000C9BE3336B86001201800403001930A86610CC2064";
constant m_1_3_A : BIT_VECTOR := X"0848432C4388860C94346614A50986C198404010001704004004D80068500C41";
constant m_1_3_B : BIT_VECTOR := X"014D064C6432631AE42D3216995715940004011D1484C20B582CA4C098388834";
constant m_1_3_C : BIT_VECTOR := X"81B009B00AB2822B28193EC17C14AB80402721013B55AE209DAA49B193A21488";
constant m_1_3_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000414BCA04";
constant m_1_3_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_3_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_4
constant m_1_4_0 : BIT_VECTOR := X"044304E218A00029326DEE399EF398C73BDE72047046251847B8885046251180";
constant m_1_4_1 : BIT_VECTOR := X"312C128827104A801084A8813C4270409E00213A204AB1412863C18208412884";
constant m_1_4_2 : BIT_VECTOR := X"408C438287188C82000007188C82000008842231288D2484200104627820823A";
constant m_1_4_3 : BIT_VECTOR := X"000000308C0407620022EC40045988008E23108840611895413871918D209409";
constant m_1_4_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_5 : BIT_VECTOR := X"0000000000000000000000000000000040000000000000000000000000000000";
constant m_1_4_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000180000";
constant m_1_4_8 : BIT_VECTOR := X"F0016180757807C5005F56000000000000000000000000000000000000000000";
constant m_1_4_9 : BIT_VECTOR := X"600050138A0A000A84A80012200000002484E301FF8603FF247B05184A309491";
constant m_1_4_A : BIT_VECTOR := X"D0012801281122201A3A105AD69070080082278C000038226138076012C18A0C";
constant m_1_4_B : BIT_VECTOR := X"3802A9129148800012804940218020684808EA45A168048C01009830A0044209";
constant m_1_4_C : BIT_VECTOR := X"50000800080882408812803802A1003A90885A044C10010A0609800A40108165";
constant m_1_4_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000281410E0";
constant m_1_4_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_4_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_5
constant m_1_5_0 : BIT_VECTOR := X"0D46902A346828214480842958C6B18C6B1A525069468129063221C54681418F";
constant m_1_5_1 : BIT_VECTOR := X"340A419481290282409022041A4835020D20A4188106682409635490A1241A0D";
constant m_1_5_2 : BIT_VECTOR := X"CA0D06B652422190A81202422190A81204146A341A0C001063F2146814924929";
constant m_1_5_3 : BIT_VECTOR := X"000000428D0505495041812A0A112541068351A0C4A51A0CD40931858F0A04A0";
constant m_1_5_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000080000";
constant m_1_5_8 : BIT_VECTOR := X"6804000029280090802228000000000000000000000000000000000000000000";
constant m_1_5_9 : BIT_VECTOR := X"DFFFE01FFEFC000FFF7DFFFFC0FFFE0FAFDFFB7FFF8203FF7FDBFF7FFEFFFDFF";
constant m_1_5_A : BIT_VECTOR := X"FFFFF0FFF0FFF001CFAF1FEF7BFFE01FC1FC0821FFFF7EFFBFFE07DFFFEF7DFB";
constant m_1_5_B : BIT_VECTOR := X"FFF3FFE3FFFF1FFF1FFFCFFFE7E1F87EFFFFFF83FFF01F5F8301FC3FE3FFFF8F";
constant m_1_5_C : BIT_VECTOR := X"EF0FFF8FFF8FFFF8FFFF8FFE07FE1C7FFFF9FC7FCFFFF91FE7FFFE7FFCFFFFFF";
constant m_1_5_D : BIT_VECTOR := X"00000000000000000000000000000000000000000000000000000000779F9FF9";
constant m_1_5_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_5_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_6
constant m_1_6_0 : BIT_VECTOR := X"4C02046010E2202954818C6B5AC6B5AC694843402002234C02B289D4022300A0";
constant m_1_6_1 : BIT_VECTOR := X"910811802300462A02046811080210088408810A0442E0010963650208811804";
constant m_1_6_2 : BIT_VECTOR := X"480402A4965AAD020248965AAD02024894C020110805B6C02800002210000828";
constant m_1_6_3 : BIT_VECTOR := X"000000100404044A40538948087029010A0100805000088DD11971958FA88C88";
constant m_1_6_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_8 : BIT_VECTOR := X"E80000802820008000020A000000000000000000000000000000000000000000";
constant m_1_6_9 : BIT_VECTOR := X"E01EF011FF7E000FBFBE003FE01F7F078088827E0004FC007FFBBF7F1EFE3DFF";
constant m_1_6_A : BIT_VECTOR := X"1DFC78FC787DA3E010101FD0841BF009BCD3E79C000F2044422007E0FEF79E7D";
constant m_1_6_B : BIT_VECTOR := X"7F13EF13FF789F7887BC03DE00F0FC7F7F4DFFC537EE0F8FC1E0FE343D3DFF8C";
constant m_1_6_C : BIT_VECTOR := X"F7810781078FD1F8FD0F81FF03F9E27FF789FBBC4FDF89EE27EFE27BC47FE7EF";
constant m_1_6_D : BIT_VECTOR := X"000000000000000000000000000000000000000000000000000000007BDFDFFC";
constant m_1_6_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_6_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
-- content of m_1_7
constant m_1_7_0 : BIT_VECTOR := X"4442006210200021100084294A521084294A52042042032842300940420310A0";
constant m_1_7_1 : BIT_VECTOR := X"1018008001000280128020900840104804002008240220000800500008801884";
constant m_1_7_2 : BIT_VECTOR := X"C084420242000000024892000000024894442210188492442800042030020008";
constant m_1_7_3 : BIT_VECTOR := X"00000000840405010010A02002140400422110885001080C4018000001000C00";
constant m_1_7_4 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_5 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_6 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_7 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_8 : BIT_VECTOR := X"0805808008080000802228000000000000000000000000000000000000000000";
constant m_1_7_9 : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_A : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_B : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_C : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_D : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_E : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
constant m_1_7_F : BIT_VECTOR := X"0000000000000000000000000000000000000000000000000000000000000000";
 
 
end mem_content;
 
package body mem_content is
 
end mem_content;
 
/memory.vhd
0,0 → 1,370
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
use work.mem_content.All;
 
entity memory is
Port ( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
PC : in std_logic_vector(15 downto 0);
ADR : in std_logic_vector(15 downto 0);
WR : in std_logic;
WDAT : in std_logic_vector( 7 downto 0);
 
OPC : out std_logic_vector( 7 downto 0);
RDAT : out std_logic_vector( 7 downto 0)
);
end memory;
 
architecture Behavioral of memory is
 
signal ENA : std_logic;
signal ENB : std_logic;
 
signal WR_0 : std_logic;
signal WR_1 : std_logic;
 
signal LADR : std_logic_vector( 3 downto 0);
signal OUT_0 : std_logic_vector( 7 downto 0);
signal OUT_1 : std_logic_vector( 7 downto 0);
 
signal LPC : std_logic_vector( 3 downto 0);
signal OPC_0 : std_logic_vector( 7 downto 0);
signal OPC_1 : std_logic_vector( 7 downto 0);
 
begin
 
ENA <= CE and not T2;
ENB <= CE and T2;
 
WR_0 <= '1' when (WR = '1' and ADR(15 downto 12) = "0000" ) else '0';
WR_1 <= '1' when (WR = '1' and ADR(15 downto 12) = "0001" ) else '0';
 
-- Bank 0 ------------------------------------------------------------------------
--
m_0_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_0_0, INIT_01 => m_0_0_1, INIT_02 => m_0_0_2, INIT_03 => m_0_0_3,
INIT_04 => m_0_0_4, INIT_05 => m_0_0_5, INIT_06 => m_0_0_6, INIT_07 => m_0_0_7,
INIT_08 => m_0_0_8, INIT_09 => m_0_0_9, INIT_0A => m_0_0_A, INIT_0B => m_0_0_B,
INIT_0C => m_0_0_C, INIT_0D => m_0_0_D, INIT_0E => m_0_0_E, INIT_0F => m_0_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(0 downto 0), DOB => OUT_0(0 downto 0)
);
 
m_0_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_1_0, INIT_01 => m_0_1_1, INIT_02 => m_0_1_2, INIT_03 => m_0_1_3,
INIT_04 => m_0_1_4, INIT_05 => m_0_1_5, INIT_06 => m_0_1_6, INIT_07 => m_0_1_7,
INIT_08 => m_0_1_8, INIT_09 => m_0_1_9, INIT_0A => m_0_1_A, INIT_0B => m_0_1_B,
INIT_0C => m_0_1_C, INIT_0D => m_0_1_D, INIT_0E => m_0_1_E, INIT_0F => m_0_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(1 downto 1), DOB => OUT_0(1 downto 1)
);
 
m_0_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_2_0, INIT_01 => m_0_2_1, INIT_02 => m_0_2_2, INIT_03 => m_0_2_3,
INIT_04 => m_0_2_4, INIT_05 => m_0_2_5, INIT_06 => m_0_2_6, INIT_07 => m_0_2_7,
INIT_08 => m_0_2_8, INIT_09 => m_0_2_9, INIT_0A => m_0_2_A, INIT_0B => m_0_2_B,
INIT_0C => m_0_2_C, INIT_0D => m_0_2_D, INIT_0E => m_0_2_E, INIT_0F => m_0_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(2 downto 2), DOB => OUT_0(2 downto 2)
);
 
m_0_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_3_0, INIT_01 => m_0_3_1, INIT_02 => m_0_3_2, INIT_03 => m_0_3_3,
INIT_04 => m_0_3_4, INIT_05 => m_0_3_5, INIT_06 => m_0_3_6, INIT_07 => m_0_3_7,
INIT_08 => m_0_3_8, INIT_09 => m_0_3_9, INIT_0A => m_0_3_A, INIT_0B => m_0_3_B,
INIT_0C => m_0_3_C, INIT_0D => m_0_3_D, INIT_0E => m_0_3_E, INIT_0F => m_0_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(3 downto 3), DOB => OUT_0(3 downto 3)
);
 
m_0_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_4_0, INIT_01 => m_0_4_1, INIT_02 => m_0_4_2, INIT_03 => m_0_4_3,
INIT_04 => m_0_4_4, INIT_05 => m_0_4_5, INIT_06 => m_0_4_6, INIT_07 => m_0_4_7,
INIT_08 => m_0_4_8, INIT_09 => m_0_4_9, INIT_0A => m_0_4_A, INIT_0B => m_0_4_B,
INIT_0C => m_0_4_C, INIT_0D => m_0_4_D, INIT_0E => m_0_4_E, INIT_0F => m_0_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(4 downto 4), DOB => OUT_0(4 downto 4)
);
 
m_0_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_5_0, INIT_01 => m_0_5_1, INIT_02 => m_0_5_2, INIT_03 => m_0_5_3,
INIT_04 => m_0_5_4, INIT_05 => m_0_5_5, INIT_06 => m_0_5_6, INIT_07 => m_0_5_7,
INIT_08 => m_0_5_8, INIT_09 => m_0_5_9, INIT_0A => m_0_5_A, INIT_0B => m_0_5_B,
INIT_0C => m_0_5_C, INIT_0D => m_0_5_D, INIT_0E => m_0_5_E, INIT_0F => m_0_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(5 downto 5), DOB => OUT_0(5 downto 5)
);
 
m_0_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_6_0, INIT_01 => m_0_6_1, INIT_02 => m_0_6_2, INIT_03 => m_0_6_3,
INIT_04 => m_0_6_4, INIT_05 => m_0_6_5, INIT_06 => m_0_6_6, INIT_07 => m_0_6_7,
INIT_08 => m_0_6_8, INIT_09 => m_0_6_9, INIT_0A => m_0_6_A, INIT_0B => m_0_6_B,
INIT_0C => m_0_6_C, INIT_0D => m_0_6_D, INIT_0E => m_0_6_E, INIT_0F => m_0_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(6 downto 6), DOB => OUT_0(6 downto 6)
);
 
m_0_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_0_7_0, INIT_01 => m_0_7_1, INIT_02 => m_0_7_2, INIT_03 => m_0_7_3,
INIT_04 => m_0_7_4, INIT_05 => m_0_7_5, INIT_06 => m_0_7_6, INIT_07 => m_0_7_7,
INIT_08 => m_0_7_8, INIT_09 => m_0_7_9, INIT_0A => m_0_7_A, INIT_0B => m_0_7_B,
INIT_0C => m_0_7_C, INIT_0D => m_0_7_D, INIT_0E => m_0_7_E, INIT_0F => m_0_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_0,
DOA => OPC_0(7 downto 7), DOB => OUT_0(7 downto 7)
);
 
-- Bank 1 ------------------------------------------------------------------------
--
m_1_0 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_0_0, INIT_01 => m_1_0_1, INIT_02 => m_1_0_2, INIT_03 => m_1_0_3,
INIT_04 => m_1_0_4, INIT_05 => m_1_0_5, INIT_06 => m_1_0_6, INIT_07 => m_1_0_7,
INIT_08 => m_1_0_8, INIT_09 => m_1_0_9, INIT_0A => m_1_0_A, INIT_0B => m_1_0_B,
INIT_0C => m_1_0_C, INIT_0D => m_1_0_D, INIT_0E => m_1_0_E, INIT_0F => m_1_0_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(0 downto 0),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(0 downto 0), DOB => OUT_1(0 downto 0)
);
 
m_1_1 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_1_0, INIT_01 => m_1_1_1, INIT_02 => m_1_1_2, INIT_03 => m_1_1_3,
INIT_04 => m_1_1_4, INIT_05 => m_1_1_5, INIT_06 => m_1_1_6, INIT_07 => m_1_1_7,
INIT_08 => m_1_1_8, INIT_09 => m_1_1_9, INIT_0A => m_1_1_A, INIT_0B => m_1_1_B,
INIT_0C => m_1_1_C, INIT_0D => m_1_1_D, INIT_0E => m_1_1_E, INIT_0F => m_1_1_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(1 downto 1),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(1 downto 1), DOB => OUT_1(1 downto 1)
);
 
m_1_2 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_2_0, INIT_01 => m_1_2_1, INIT_02 => m_1_2_2, INIT_03 => m_1_2_3,
INIT_04 => m_1_2_4, INIT_05 => m_1_2_5, INIT_06 => m_1_2_6, INIT_07 => m_1_2_7,
INIT_08 => m_1_2_8, INIT_09 => m_1_2_9, INIT_0A => m_1_2_A, INIT_0B => m_1_2_B,
INIT_0C => m_1_2_C, INIT_0D => m_1_2_D, INIT_0E => m_1_2_E, INIT_0F => m_1_2_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(2 downto 2),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(2 downto 2), DOB => OUT_1(2 downto 2)
);
 
m_1_3 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_3_0, INIT_01 => m_1_3_1, INIT_02 => m_1_3_2, INIT_03 => m_1_3_3,
INIT_04 => m_1_3_4, INIT_05 => m_1_3_5, INIT_06 => m_1_3_6, INIT_07 => m_1_3_7,
INIT_08 => m_1_3_8, INIT_09 => m_1_3_9, INIT_0A => m_1_3_A, INIT_0B => m_1_3_B,
INIT_0C => m_1_3_C, INIT_0D => m_1_3_D, INIT_0E => m_1_3_E, INIT_0F => m_1_3_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(3 downto 3),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(3 downto 3), DOB => OUT_1(3 downto 3)
);
 
m_1_4 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_4_0, INIT_01 => m_1_4_1, INIT_02 => m_1_4_2, INIT_03 => m_1_4_3,
INIT_04 => m_1_4_4, INIT_05 => m_1_4_5, INIT_06 => m_1_4_6, INIT_07 => m_1_4_7,
INIT_08 => m_1_4_8, INIT_09 => m_1_4_9, INIT_0A => m_1_4_A, INIT_0B => m_1_4_B,
INIT_0C => m_1_4_C, INIT_0D => m_1_4_D, INIT_0E => m_1_4_E, INIT_0F => m_1_4_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(4 downto 4),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(4 downto 4), DOB => OUT_1(4 downto 4)
);
 
m_1_5 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_5_0, INIT_01 => m_1_5_1, INIT_02 => m_1_5_2, INIT_03 => m_1_5_3,
INIT_04 => m_1_5_4, INIT_05 => m_1_5_5, INIT_06 => m_1_5_6, INIT_07 => m_1_5_7,
INIT_08 => m_1_5_8, INIT_09 => m_1_5_9, INIT_0A => m_1_5_A, INIT_0B => m_1_5_B,
INIT_0C => m_1_5_C, INIT_0D => m_1_5_D, INIT_0E => m_1_5_E, INIT_0F => m_1_5_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(5 downto 5),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(5 downto 5), DOB => OUT_1(5 downto 5)
);
-- synopsys translate_on
 
m_1_6 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_6_0, INIT_01 => m_1_6_1, INIT_02 => m_1_6_2, INIT_03 => m_1_6_3,
INIT_04 => m_1_6_4, INIT_05 => m_1_6_5, INIT_06 => m_1_6_6, INIT_07 => m_1_6_7,
INIT_08 => m_1_6_8, INIT_09 => m_1_6_9, INIT_0A => m_1_6_A, INIT_0B => m_1_6_B,
INIT_0C => m_1_6_C, INIT_0D => m_1_6_D, INIT_0E => m_1_6_E, INIT_0F => m_1_6_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(6 downto 6),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(6 downto 6), DOB => OUT_1(6 downto 6)
);
 
 
m_1_7 : RAMB4_S1_S1
-- synopsys translate_off
GENERIC MAP(
INIT_00 => m_1_7_0, INIT_01 => m_1_7_1, INIT_02 => m_1_7_2, INIT_03 => m_1_7_3,
INIT_04 => m_1_7_4, INIT_05 => m_1_7_5, INIT_06 => m_1_7_6, INIT_07 => m_1_7_7,
INIT_08 => m_1_7_8, INIT_09 => m_1_7_9, INIT_0A => m_1_7_A, INIT_0B => m_1_7_B,
INIT_0C => m_1_7_C, INIT_0D => m_1_7_D, INIT_0E => m_1_7_E, INIT_0F => m_1_7_F)
-- synopsys translate_on
PORT MAP( ADDRA => PC(11 downto 0), ADDRB => ADR(11 downto 0),
CLKA => CLK_I, CLKB => CLK_I,
DIA => "0", DIB => WDAT(7 downto 7),
ENA => ENA, ENB => ENB,
RSTA => '0', RSTB => '0',
WEA => '0', WEB => WR_1,
DOA => OPC_1(7 downto 7), DOB => OUT_1(7 downto 7)
);
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CE = '1') then
LADR <= ADR(15 downto 12);
end if;
end if;
end if;
end process;
 
process(LADR, OUT_0, OUT_1)
begin
 
case LADR is
when "0001" => RDAT <= OUT_1;
when others => RDAT <= OUT_0;
end case;
 
end process;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '0') then
if (CE = '1') then
LPC <= PC(15 downto 12);
end if;
end if;
end if;
end process;
 
process(LPC, OPC_0, OPC_1)
begin
case LPC is
when "0001" => OPC <= OPC_1;
when others => OPC <= OPC_0;
end case;
end process;
 
end Behavioral;
/alu8.vhd
0,0 → 1,271
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity alu8 is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
 
ALU_OP : in std_logic_vector( 4 downto 0);
XX : in std_logic_vector(15 downto 0);
YY : in std_logic_vector(15 downto 0);
 
ZZ : out std_logic_vector(15 downto 0)
);
end alu8;
 
architecture Behavioral of alu8 is
 
 
function sh_mask(Y : unsigned(3 downto 0);
YMAX : unsigned(3 downto 0);
LR : std_logic;
FILL : std_logic;
X : std_logic) return std_logic is
 
begin
if (YMAX >= Y) then -- Y small
if (LR = '1') then return X; -- LSL
else return FILL; -- LSR
end if;
else -- Y big
if (LR = '1') then return FILL; -- LSL
else return X; -- ASR/LSR
end if;
end if;
end;
 
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
 
function b16(A : std_logic) return std_logic_vector is
begin
return b8(A) & b8(A);
end;
 
function aoxn(A : std_logic_vector(3 downto 0)) return std_logic is
begin
case A is
-- and
when "0000" => return '0';
when "0001" => return '0';
when "0010" => return '0';
when "0011" => return '1';
-- or
when "0100" => return '0';
when "0101" => return '1';
when "0110" => return '1';
when "0111" => return '1';
-- xor
when "1000" => return '1';
when "1001" => return '0';
when "1010" => return '0';
when "1011" => return '1';
-- not Y
when "1100" => return '1';
when "1101" => return '0';
when "1110" => return '1';
when others => return '0';
end case;
end;
 
signal MD_OR : std_logic_vector(15 downto 0); -- Multiplicator/Divisor
signal PROD_REM : std_logic_vector(31 downto 0);
signal MD_OP : std_logic; -- operation D/M, S/U
signal QP_NEG : std_logic; -- product / quotient negative
signal RM_NEG : std_logic; -- remainder negative
 
begin
 
alumux: process(ALU_OP, MD_OP, XX, YY, QP_NEG, RM_NEG, PROD_REM)
 
variable MASKED_X : std_logic_vector(15 downto 0);
variable SCNT : unsigned(3 downto 0);
variable SFILL : std_logic;
variable ROL1 : std_logic_vector(15 downto 0);
variable ROL2 : std_logic_vector(15 downto 0);
variable ROL4 : std_logic_vector(15 downto 0);
variable ROL8 : std_logic_vector(15 downto 0);
variable X_GE_Y : std_logic; -- signed X >= Y
variable X_HS_Y : std_logic; -- unsigned X >= Y
variable X_HSGE_Y : std_logic; -- any X >= Y
variable X_EQ_Y : std_logic; -- signed X == Y
variable X_CMP_Y : std_logic;
 
begin
MASKED_X := XX and b16(ALU_OP(0));
SFILL := ALU_OP(0) and XX(15);
 
if (ALU_OP(1) = '1') then -- LSL
SCNT := UNSIGNED(YY(3 downto 0));
else -- LSR / ASR
SCNT := "0000" - UNSIGNED(YY(3 downto 0));
end if;
 
if (SCNT(0) = '0') then ROL1 := XX;
else ROL1 := XX(14 downto 0) & XX(15);
end if;
 
if (SCNT(1) = '0') then ROL2 := ROL1;
else ROL2 := ROL1(13 downto 0) & ROL1(15 downto 14);
end if;
 
if (SCNT(2) = '0') then ROL4 := ROL2;
else ROL4 := ROL2(11 downto 0) & ROL2(15 downto 12);
end if;
 
if (SCNT(3) = '0') then ROL8 := ROL4;
else ROL8 := ROL4(7 downto 0) & ROL4(15 downto 8);
end if;
 
if (XX = YY) then X_EQ_Y := '1';
else X_EQ_Y := '0';
end if;
 
if (UNSIGNED(XX) >= UNSIGNED(YY)) then X_HSGE_Y := '1';
else X_HSGE_Y := '0';
end if;
 
if (XX(15) /= YY(15)) then -- different sign/high bit
X_HS_Y := XX(15); -- X ia bigger iff high bit set
X_GE_Y := YY(15); -- X is bigger iff Y negative
else -- same sign/high bit: GE == HS
X_HS_Y := X_HSGE_Y;
X_GE_Y := X_HSGE_Y;
end if;
 
case ALU_OP is
when ALU_X_HS_Y => X_CMP_Y := X_HS_Y;
when ALU_X_LO_Y => X_CMP_Y := not X_HS_Y;
when ALU_X_HI_Y => X_CMP_Y := X_HS_Y and not X_EQ_Y;
when ALU_X_LS_Y => X_CMP_Y := not (X_HS_Y and not X_EQ_Y);
when ALU_X_GE_Y => X_CMP_Y := X_GE_Y;
when ALU_X_LT_Y => X_CMP_Y := not X_GE_Y;
when ALU_X_GT_Y => X_CMP_Y := X_GE_Y and not X_EQ_Y;
when ALU_X_LE_Y => X_CMP_Y := not (X_GE_Y and not X_EQ_Y);
when ALU_X_EQ_Y => X_CMP_Y := X_EQ_Y;
when others => X_CMP_Y := not X_EQ_Y;
end case;
 
ZZ <= X"0000";
 
case ALU_OP is
when ALU_X_HS_Y | ALU_X_LO_Y | ALU_X_HI_Y | ALU_X_LS_Y |
ALU_X_GE_Y | ALU_X_LT_Y | ALU_X_GT_Y | ALU_X_LE_Y |
ALU_X_EQ_Y | ALU_X_NE_Y =>
ZZ <= b16(X_CMP_Y);
 
when ALU_NEG_Y | ALU_X_SUB_Y =>
ZZ <= MASKED_X - YY;
 
when ALU_MOVE_Y | ALU_X_ADD_Y =>
ZZ <= MASKED_X + YY;
 
when ALU_X_AND_Y | ALU_X_OR_Y | ALU_X_XOR_Y | ALU_NOT_Y =>
for i in 0 to 15 loop
ZZ(i) <= aoxn(ALU_OP(1 downto 0) & XX(i) & YY(i));
end loop;
 
when ALU_X_LSR_Y | ALU_X_ASR_Y | ALU_X_LSL_Y =>
for i in 0 to 15 loop
ZZ(i) <= sh_mask(SCNT, CONV_UNSIGNED(i, 4),
ALU_OP(1), SFILL, ROL8(i));
end loop;
 
when ALU_X_MIX_Y =>
ZZ(15 downto 8) <= YY(7 downto 0);
ZZ( 7 downto 0) <= XX(7 downto 0);
 
when ALU_MUL_IU | ALU_MUL_IS |
ALU_DIV_IU | ALU_DIV_IS | ALU_MD_STP => -- mult/div ini/step
ZZ <= PROD_REM(15 downto 0);
 
when ALU_MD_FIN => -- mult/div
if (QP_NEG = '0') then ZZ <= PROD_REM(15 downto 0);
else ZZ <= X"0000" - PROD_REM(15 downto 0);
end if;
 
when others => -- modulo
if (RM_NEG = '0') then ZZ <= PROD_REM(31 downto 16);
else ZZ <= X"0000" - PROD_REM(31 downto 16);
end if;
end case;
end process;
 
muldiv: process(CLK_I)
 
variable POS_YY : std_logic_vector(15 downto 0);
variable POS_XX : std_logic_vector(15 downto 0);
variable DIFF : std_logic_vector(16 downto 0);
variable SUM : std_logic_vector(16 downto 0);
 
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
PROD_REM <= X"00000000"; -- product/remainder
MD_OR <= X"0000"; -- multiplicator/divisor
MD_OP <= '0'; -- mult(0)/div(1)
QP_NEG <= '0'; -- quotient/product negative
RM_NEG <= '0'; -- remainder negative
elsif (CE = '1') then
SUM := ('0' & PROD_REM(31 downto 16)) + ('0' & MD_OR);
DIFF := ('0' & PROD_REM(30 downto 15)) - ('0' & MD_OR);
 
if (XX(15) = '0') then POS_XX := XX;
else POS_XX := X"0000" - XX;
end if;
 
if (YY(15) = '0') then POS_YY := YY;
else POS_YY := X"0000" - YY;
end if;
 
case ALU_OP is
when ALU_MUL_IU | ALU_MUL_IS | ALU_DIV_IU | ALU_DIV_IS =>
MD_OP <= ALU_OP(1); -- div / mult
MD_OR <= POS_YY; -- multiplicator/divisor
QP_NEG <= ALU_OP(0) and (XX(15) xor YY(15));
RM_NEG <= ALU_OP(0) and XX(15);
PROD_REM <= X"0000" & POS_XX;
 
when ALU_MD_STP =>
if (MD_OP = '0') then -- multiplication step
 
PROD_REM(15 downto 0) <= PROD_REM(16 downto 1);
if (PROD_REM(0) = '0') then
PROD_REM(31 downto 15) <=
'0' & PROD_REM(31 downto 16);
else
PROD_REM(31 downto 15) <= SUM;
end if;
else -- division step
if (DIFF(16) = '1') then -- carry: small remainder
PROD_REM(31 downto 16) <= PROD_REM(30 downto 15);
else
PROD_REM(31 downto 16) <= DIFF(15 downto 0);
end if;
 
PROD_REM(15 downto 1) <= PROD_REM(14 downto 0);
PROD_REM(0) <= not DIFF(16);
end if;
 
when others =>
end case;
end if;
end if;
end if;
end process;
 
end Behavioral;
/uart.vhd
0,0 → 1,73
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uart is
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic;
 
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
 
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
end uart;
 
architecture Behavioral of uart is
 
COMPONENT uart_tx
PORT( CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : IN std_logic;
DATA : IN std_logic_vector(7 downto 0);
DATA_FLAG : IN std_logic;
SER_OUT : OUT std_logic;
DATA_FLAGQ : OUT std_logic
);
END COMPONENT;
 
COMPONENT uart_rx
PORT( CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : IN std_logic;
SER_IN : IN std_logic;
DATA : OUT std_logic_vector(7 downto 0);
DATA_FLAG : OUT std_logic
);
END COMPONENT;
 
begin
 
tx: uart_tx
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
DATA => TX_DATA,
DATA_FLAG => TX_FLAG,
 
SER_OUT => TX_SEROUT,
DATA_FLAGQ => TX_FLAGQ
);
 
rx: uart_rx
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
DATA => RX_DATA,
SER_IN => RX_SERIN,
DATA_FLAG => RX_FLAG
);
 
end Behavioral;
/cpu_engine.vhd
0,0 → 1,459
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity cpu_engine is
PORT( CLK_I : in std_logic;
T2 : out std_logic;
CLR : in std_logic;
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
 
-- input/output
INT : in std_logic;
IO_ADR : out std_logic_vector(7 downto 0);
IO_RD : out std_logic;
IO_WR : out std_logic;
IO_RDAT : in std_logic_vector( 7 downto 0);
 
-- external memory
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic;
 
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
 
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
 
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0);
HALT : out std_logic
);
end cpu_engine;
 
architecture Behavioral of cpu_engine is
 
COMPONENT memory
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CE : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
ADR : IN std_logic_vector(15 downto 0);
WR : IN std_logic;
WDAT : IN std_logic_vector(7 downto 0);
 
OPC : OUT std_logic_vector(7 downto 0);
RDAT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
COMPONENT opcode_fetch
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
PC_OP : IN std_logic_vector(2 downto 0);
JDATA : IN std_logic_vector(15 downto 0);
RR : IN std_logic_vector(15 downto 0);
RDATA : IN std_logic_vector(7 downto 0);
PC : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
COMPONENT opcode_decoder
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : in std_logic_vector(7 downto 0);
OP_CYC : in cycle;
INT : in std_logic;
RRZ : in std_logic;
 
OP_CAT : out op_category;
 
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
 
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_M : out std_logic;
D_WE_SP : out SP_OP;
 
-- input/output
IO_RD : out std_logic;
IO_WR : out std_logic;
 
PC_OP : out std_logic_vector(2 downto 0);
 
LAST_M : out std_logic;
HLT : out std_logic
);
END COMPONENT;
 
COMPONENT data_core
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
 
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
 
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
 
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
 
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
 
-- input/output
IO_RDAT : in std_logic_vector( 7 downto 0);
 
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
END COMPONENT;
 
-- global signals
signal CE : std_logic;
signal LT2 : std_logic;
 
-- memory signals
signal MEM_WDAT : std_logic_vector(7 downto 0);
signal MEM_RDAT : std_logic_vector(7 downto 0);
signal M_PC : std_logic_vector(15 downto 0);
signal M_OPC : std_logic_vector(7 downto 0);
 
-- decoder signals
--
signal D_CAT : op_category;
signal D_OPC : std_logic_vector(7 downto 0);
signal D_CYC : cycle;
signal D_PC : std_logic_vector(15 downto 0); -- debug signal
signal D_PC_OP : std_logic_vector( 2 downto 0);
signal D_LAST_M : std_logic;
signal D_IO_RD : std_logic;
signal D_IO_WR : std_logic;
-- select signals
signal D_SX : std_logic_vector(1 downto 0);
signal D_SY : std_logic_vector(3 downto 0);
signal D_OP : std_logic_vector(4 downto 0);
signal D_SA : std_logic_vector(4 downto 0);
signal D_SMQ : std_logic;
-- write enable/select signals
signal D_WE_RR : std_logic;
signal D_WE_LL : std_logic;
signal D_WE_SP : SP_OP;
signal D_MEM_WE : std_logic;
signal MEM_WE : std_logic;
 
-- core signals
--
signal C_IMM : std_logic_vector(15 downto 0);
signal ADR : std_logic_vector(15 downto 0);
 
signal C_CYC : cycle; -- debug signal
signal C_PC : std_logic_vector(15 downto 0); -- debug signal
signal C_OPC : std_logic_vector( 7 downto 0); -- debug signal
signal C_RR : std_logic_vector(15 downto 0);
signal RRZ : std_logic;
signal OC_JD : std_logic_vector(15 downto 0);
signal C_MQ : std_logic_vector(7 downto 0);
 
-- select signals
signal C_SX : std_logic_vector(1 downto 0);
signal C_SY : std_logic_vector(3 downto 0);
signal C_OP : std_logic_vector(4 downto 0);
signal C_SA : std_logic_vector(4 downto 0);
signal C_SMQ : std_logic;
signal C_WE_RR : std_logic;
signal C_WE_LL : std_logic;
signal C_WE_SP : SP_OP;
 
signal XM_OPC : std_logic_vector(7 downto 0);
signal LM_OPC : std_logic_vector(7 downto 0);
signal LM_RDAT : std_logic_vector(7 downto 0);
signal LXM_RDAT : std_logic_vector(7 downto 0);
signal OPCS : std_logic;
signal RDATS : std_logic;
 
begin
 
memo: memory
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CE => CE,
 
-- read in T1
PC => M_PC,
OPC => LM_OPC,
 
-- read or written in T2
ADR => ADR,
WR => MEM_WE,
WDAT => MEM_WDAT,
RDAT => LM_RDAT
);
 
ocf: opcode_fetch
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
PC_OP => D_PC_OP,
JDATA => OC_JD,
RR => C_RR,
RDATA => MEM_RDAT,
PC => M_PC
);
 
opdec: opcode_decoder
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
OPCODE => D_OPC,
OP_CYC => D_CYC,
INT => INT,
RRZ => RRZ,
 
OP_CAT => D_CAT,
-- select signals
D_SX => D_SX,
D_SY => D_SY,
D_OP => D_OP,
D_SA => D_SA,
D_SMQ => D_SMQ,
 
-- write enable/select signal
D_WE_RR => D_WE_RR,
D_WE_LL => D_WE_LL,
D_WE_M => D_MEM_WE,
D_WE_SP => D_WE_SP,
 
IO_RD => D_IO_RD,
IO_WR => D_IO_WR,
 
PC_OP => D_PC_OP,
LAST_M => D_LAST_M,
HLT => HALT
);
 
dcore: data_core
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
CE => CE,
 
-- select signals
SX => C_SX,
SY => C_SY,
OP => C_OP,
PC => C_PC,
QU => C_OPC(3 downto 0),
SA => C_SA,
SMQ => C_SMQ,
 
-- write enable/select signal
WE_RR => C_WE_RR,
WE_LL => C_WE_LL,
WE_SP => C_WE_SP,
 
IMM => C_IMM,
M_RDAT => MEM_RDAT,
ADR => ADR,
MQ => MEM_WDAT,
 
IO_RDAT => IO_RDAT,
 
Q_RR => C_RR,
Q_LL => Q_LL,
Q_SP => Q_SP
);
 
CE <= '1';
T2 <= LT2;
 
IO_ADR <= ADR(7 downto 0);
Q_RR <= C_RR;
RRZ <= '1' when (C_RR = X"0000") else '0';
OC_JD <= M_OPC & C_IMM(7 downto 0);
 
Q_PC <= C_PC;
Q_OPC <= C_OPC;
Q_CYC <= C_CYC;
Q_IMM <= C_IMM;
 
-- select signals
Q_SX <= C_SX;
Q_SY <= C_SY;
Q_OP <= C_OP;
Q_SA <= C_SA;
Q_SMQ <= C_SMQ;
 
-- write enable/select signal
Q_WE_RR <= C_WE_RR;
Q_WE_LL <= C_WE_LL;
Q_WE_SP <= C_WE_SP;
 
XM_WDAT <= MEM_WDAT;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
LT2 <= not LT2;
end if;
end process;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '1') then
RDATS <= ADR(15) or ADR(14) or ADR(13);
LXM_RDAT <= XM_RDAT;
end if;
end if;
end process;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '0') then
OPCS <= M_PC(15) or M_PC(14) or M_PC(13);
XM_OPC <= XM_RDAT;
end if;
end if;
end process;
 
process(OPCS, LM_OPC, XM_OPC)
begin
if (OPCS = '0') then M_OPC <= LM_OPC;
else M_OPC <= XM_OPC;
end if;
end process;
 
process(RDATS, LXM_RDAT, LM_RDAT)
begin
if (RDATS = '0') then MEM_RDAT <= LM_RDAT;
else MEM_RDAT <= LXM_RDAT;
end if;
end process;
 
process(LT2, M_PC, ADR, MEM_WE)
begin
if (LT2 = '0') then -- opcode fetch
XM_ADR <= M_PC;
XM_WE <= '0';
XM_CE <= M_PC(15) or M_PC(14) or M_PC(13);
else -- data
XM_ADR <= ADR;
XM_WE <= MEM_WE;
XM_CE <= ADR(15) or ADR(14) or ADR(13);
end if;
end process;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (LT2 = '1') then
if (CLR = '1') then
D_PC <= X"0000";
D_OPC <= X"01";
D_CYC <= M1;
 
C_PC <= X"0000";
C_OPC <= X"01";
C_CYC <= M1;
C_IMM <= X"FFFF";
 
C_SX <= "00";
C_SY <= "0000";
C_OP <= "00000";
C_SA <= "00000";
C_SMQ <= '0';
C_WE_RR <= '0';
C_WE_LL <= '0';
C_WE_SP <= SP_NOP;
MEM_WE <= '0';
 
elsif (CE = '1') then
C_CYC <= D_CYC;
Q_CAT <= D_CAT;
C_PC <= D_PC;
C_OPC <= D_OPC;
C_SX <= D_SX;
C_SY <= D_SY;
C_OP <= D_OP;
C_SA <= D_SA;
C_SMQ <= D_SMQ;
C_WE_RR <= D_WE_RR;
C_WE_LL <= D_WE_LL;
C_WE_SP <= D_WE_SP;
IO_RD <= D_IO_RD;
IO_WR <= D_IO_WR;
MEM_WE <= D_MEM_WE;
 
if (D_LAST_M = '1') then -- D goes to M1
-- signals valid for entire opcode...
D_OPC <= M_OPC;
D_PC <= M_PC;
D_CYC <= M1;
else
case D_CYC is
when M1 => D_CYC <= M2; -- C goes to M1
C_IMM <= X"00" & M_OPC;
when M2 => D_CYC <= M3;
C_IMM(15 downto 8) <= M_OPC;
when M3 => D_CYC <= M4;
when M4 => D_CYC <= M5;
when M5 => D_CYC <= M1;
end case;
end if;
end if;
end if;
end if;
end process;
 
end Behavioral;
/uart._baudgen.vhd
0,0 → 1,116
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity uart_baudgen is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
 
RD : in std_logic;
WR : in std_logic;
 
TX_DATA : in std_logic_vector(7 downto 0);
TX_SEROUT : out std_logic;
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_READY : out std_logic;
TX_BUSY : out std_logic
);
end uart_baudgen;
 
architecture Behavioral of uart_baudgen is
 
COMPONENT baudgen
Generic(bg_clock_freq : integer; bg_baud_rate : integer);
PORT(
CLK_I : IN std_logic;
CLR : IN std_logic;
CE_16 : OUT std_logic
);
END COMPONENT;
 
COMPONENT uart
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic;
 
TX_DATA : in std_logic_vector(7 downto 0);
TX_FLAG : in std_logic;
TX_SEROUT : out std_logic;
TX_FLAGQ : out std_logic;
 
RX_SERIN : in std_logic;
RX_DATA : out std_logic_vector(7 downto 0);
RX_FLAG : out std_logic
);
END COMPONENT;
 
signal CE_16 : std_logic;
signal RX_FLAG : std_logic;
signal RX_OLD_FLAG : std_logic;
signal TX_FLAG : std_logic;
signal TX_FLAGQ : std_logic;
signal LTX_DATA : std_logic_vector(7 downto 0);
signal LRX_READY : std_logic;
 
begin
 
RX_READY <= LRX_READY;
TX_BUSY <= TX_FLAG xor TX_FLAGQ;
 
baud: baudgen
GENERIC MAP(bg_clock_freq => 40000000, bg_baud_rate => 115200)
PORT MAP(
CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16
);
 
urt: uart
PORT MAP( CLK_I => CLK_I,
CLR => CLR,
CE_16 => CE_16,
TX_DATA => LTX_DATA,
TX_FLAG => TX_FLAG,
TX_SEROUT => TX_SEROUT,
TX_FLAGQ => TX_FLAGQ,
RX_SERIN => RX_SERIN,
RX_DATA => RX_DATA,
RX_FLAG => RX_FLAG
);
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
TX_FLAG <= '0';
LTX_DATA <= X"33";
else
if (RD = '1') then -- read Rx data
LRX_READY <= '0';
end if;
 
if (WR = '1') then -- write Tx data
TX_FLAG <= not TX_FLAG;
LTX_DATA <= TX_DATA;
end if;
 
if (RX_FLAG /= RX_OLD_FLAG) then
LRX_READY <= '1';
end if;
 
RX_OLD_FLAG <= RX_FLAG;
end if;
end if;
end if;
end process;
 
end Behavioral;
/test.vhd
0,0 → 1,186
 
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
use work.cpu_pack.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS
 
COMPONENT cpu_engine
PORT( CLK : in std_logic;
CCK : in std_logic;
CLR : in std_logic;
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
 
-- input/output
INT : in std_logic;
IO_ADR : out std_logic_vector(7 downto 0);
IO_RD : out std_logic;
IO_WR : out std_logic;
IO_RDAT : in std_logic_vector( 7 downto 0);
 
-- memory
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic;
 
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
 
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
 
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0);
HALT : out std_logic
);
END COMPONENT;
 
signal CLK : std_logic;
signal CLR : std_logic;
signal Q_PC : std_logic_vector(15 downto 0);
signal Q_OPC : std_logic_vector( 7 downto 0);
signal Q_CAT : op_category;
signal Q_CYC : cycle;
signal Q_IMM : std_logic_vector(15 downto 0);
 
signal Q_SP : std_logic_vector(15 downto 0);
signal Q_LL : std_logic_vector(15 downto 0);
signal Q_RR : std_logic_vector(15 downto 0);
 
-- input/output
signal INT : std_logic;
signal IO_RD : std_logic;
signal IO_ADR : std_logic_vector( 7 downto 0);
signal IO_WR : std_logic;
signal IO_RDAT : std_logic_vector( 7 downto 0);
signal HALT : std_logic;
 
-- memory
signal XM_ADR : std_logic_vector(15 downto 0);
signal XM_RDAT : std_logic_vector( 7 downto 0);
signal XM_WDAT : std_logic_vector( 7 downto 0);
signal XM_WE : std_logic;
signal XM_CE : std_logic;
 
-- select signals
signal Q_SX : std_logic_vector(1 downto 0);
signal Q_SY : std_logic_vector(3 downto 0);
signal Q_OP : std_logic_vector(4 downto 0);
signal Q_SA : std_logic_vector(4 downto 0);
signal Q_SMQ : std_logic;
 
-- write enable/select signal
signal Q_WE_RR : std_logic;
signal Q_WE_LL : std_logic;
signal Q_WE_SP : SP_OP;
 
signal clk_counter : INTEGER := 0;
 
BEGIN
 
uut: cpu_engine PORT MAP(
CLK => CLK,
CCK => CLK,
CLR => CLR,
Q_PC => Q_PC,
Q_OPC => Q_OPC,
Q_CAT => Q_CAT,
Q_IMM => Q_IMM,
Q_CYC => Q_CYC,
 
INT => INT,
IO_ADR => IO_ADR,
IO_RD => IO_RD,
IO_WR => IO_WR,
IO_RDAT => IO_RDAT,
 
XM_ADR => XM_ADR,
XM_RDAT => XM_RDAT,
XM_WDAT => XM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
 
Q_SX => Q_SX,
Q_SY => Q_SY,
Q_OP => Q_OP,
Q_SA => Q_SA,
Q_SMQ => Q_SMQ,
 
Q_WE_RR => Q_WE_RR,
Q_WE_LL => Q_WE_LL,
Q_WE_SP => Q_WE_SP,
 
Q_RR => Q_RR,
Q_LL => Q_LL,
Q_SP => Q_SP,
HALT => HALT
);
 
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 1 ns;
CLK <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
 
PROCESS(CLK)
BEGIN
if (rising_edge(CLK)) then
if (Q_CYC = M1) then
CLK_COUNTER <= CLK_COUNTER + 1;
end if;
 
if (XM_ADR(0) = '0') then IO_RDAT <= X"44"; -- data
else IO_RDAT <= X"01"; -- control
end if;
 
case CLK_COUNTER is
when 0 => CLR <= '1'; INT <= '0';
when 1 => CLR <= '0';
-- when 20 => INT <= '1';
 
 
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
 
END;
/input_output.vhd
0,0 → 1,222
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity input_output is
PORT ( CLK_I : in std_logic;
T2 : in std_logic;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
 
HALT : in STD_LOGIC;
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
 
-- temperature
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
 
LED : out STD_LOGIC_VECTOR (7 downto 0);
 
CLR : out STD_LOGIC;
 
-- input/output
IO_RD : in std_logic;
IO_WR : in std_logic;
IO_ADR : in std_logic_vector( 7 downto 0);
IO_RDAT : out std_logic_vector( 7 downto 0);
IO_WDAT : in std_logic_vector( 7 downto 0);
INT : out STD_LOGIC
);
end input_output;
 
architecture Behavioral of input_output is
 
COMPONENT temperature
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
TEMP_SPO : IN std_logic;
DATA_OUT : OUT std_logic_vector(7 downto 0);
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic
);
END COMPONENT;
 
COMPONENT uart_baudgen
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
RD : IN std_logic;
WR : IN std_logic;
TX_DATA : IN std_logic_vector(7 downto 0);
RX_SERIN : IN std_logic;
TX_SEROUT : OUT std_logic;
RX_DATA : OUT std_logic_vector(7 downto 0);
RX_READY : OUT std_logic;
TX_BUSY : OUT std_logic
);
END COMPONENT;
 
signal L_IO_ADR : std_logic_vector(7 downto 0);
signal IO_RD_SERIAL : std_logic;
signal IO_WR_SERIAL : std_logic;
signal RX_READY : std_logic;
signal TX_BUSY : std_logic;
signal RX_DATA : std_logic_vector(7 downto 0);
signal TEMP_DO : std_logic_vector(7 downto 0);
 
signal FLAG : std_logic;
 
signal LCLR : std_logic;
signal C1_N, C2_N : std_logic; -- switch debounce, active low
 
signal RX_INT_ENABLED : std_logic;
signal TX_INT_ENABLED : std_logic;
signal TIM_INT_ENABLED : std_logic;
signal TIMER_INT : std_logic;
signal TIMER : std_logic_vector(14 downto 0);
signal CLK_COUNT : std_logic_vector(15 downto 0);
 
signal CLK_COUNT_EN : std_logic;
signal CLK_HALT_MSK : std_logic;
signal CLK_HALT_VAL : std_logic;
 
begin
 
tempr: temperature
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => LCLR,
DATA_OUT => TEMP_DO,
TEMP_SPI => TEMP_SPI,
TEMP_SPO => TEMP_SPO,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK
);
 
uart: uart_baudgen
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CLR => LCLR,
RD => IO_RD_SERIAL,
WR => IO_WR_SERIAL,
TX_DATA => IO_WDAT,
TX_SEROUT => SER_OUT,
RX_SERIN => SER_IN,
RX_DATA => RX_DATA,
RX_READY => RX_READY,
TX_BUSY => TX_BUSY
);
 
CLR <= LCLR;
INT <= (RX_INT_ENABLED and RX_READY)
or (TX_INT_ENABLED and not TX_BUSY)
or (TIM_INT_ENABLED and TIMER_INT);
 
-- IO read process
--
process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH,
TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY,
RX_INT_ENABLED, RX_READY)
begin
IO_RD_SERIAL <= '0';
IO_WR_SERIAL <= '0';
case L_IO_ADR is
when X"00" => IO_RDAT <= RX_DATA;
IO_RD_SERIAL <= IO_RD;
IO_WR_SERIAL <= IO_WR;
when X"01" => IO_RDAT <= '0'
& (TIM_INT_ENABLED and TIMER_INT)
& (TX_INT_ENABLED and not TX_BUSY)
& (RX_INT_ENABLED and RX_READY)
& '0'
& TIMER_INT
& TX_BUSY
& RX_READY;
when X"02" => IO_RDAT <= TEMP_DO;
when X"03" => IO_RDAT <= SWITCH(7 downto 0);
when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0);
when others => IO_RDAT <= CLK_COUNT(15 downto 8);
end case;
end process;
 
-- IO write and timer process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
L_IO_ADR <= IO_ADR;
if (LCLR = '1') then
LED <= X"00";
RX_INT_ENABLED <= '0';
TX_INT_ENABLED <= '0';
TIM_INT_ENABLED <= '0';
TIMER_INT <= '0';
TIMER <= "000" & X"000";
else
if (IO_WR = '1') then
case L_IO_ADR is
when X"00" => -- handled by uart
when X"01" => -- handled by uart
when X"02" => LED <= IO_WDAT;
when X"03" => RX_INT_ENABLED <= IO_WDAT(0);
TX_INT_ENABLED <= IO_WDAT(1);
TIM_INT_ENABLED <= IO_WDAT(2);
when X"04" => TIMER_INT <= '0';
when X"05" => CLK_COUNT_EN <= '1';
CLK_COUNT <= X"0000";
CLK_HALT_VAL <= IO_WDAT(0);
CLK_HALT_MSK <= IO_WDAT(1);
when X"06" => CLK_COUNT_EN <= '0';
when others =>
end case;
end if;
 
TIMER <= TIMER + 1;
if (TIMER = 19999) then -- 1 ms
TIMER_INT <= '1';
TIMER <= "000" & X"000";
end if;
 
if (CLK_COUNT_EN = '1' and
(HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then
CLK_COUNT <= CLK_COUNT + 1;
end if;
end if;
end if;
end if;
end process;
 
-- reset debounce process
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
-- switch debounce
if (SWITCH(8) = '1' or SWITCH(9) = '1') then
LCLR <= '1';
C2_N <= '0';
C1_N <= '0';
else
LCLR <= not C2_N;
C2_N <= C1_N;
C1_N <= '1';
end if;
end if;
end if;
end process;
 
end Behavioral;
/data_core.vhd
0,0 → 1,201
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity data_core is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
 
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
 
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
 
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
M_RDAT : in std_logic_vector( 7 downto 0); -- memory data
 
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
 
-- input/output
IO_RDAT: in std_logic_vector( 7 downto 0);
 
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end data_core;
 
architecture Behavioral of data_core is
 
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
 
COMPONENT alu8
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
 
ALU_OP : IN std_logic_vector( 4 downto 0);
XX : IN std_logic_vector(15 downto 0);
YY : IN std_logic_vector(15 downto 0);
ZZ : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
COMPONENT select_yy
PORT( SY : IN std_logic_vector( 3 downto 0);
IMM : IN std_logic_vector(15 downto 0);
QUICK : IN std_logic_vector( 3 downto 0);
M_RDAT : IN std_logic_vector( 7 downto 0);
IO_RDAT : IN std_logic_vector( 7 downto 0);
RR : IN std_logic_vector(15 downto 0);
YY : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
-- cpu registers
--
signal RR : std_logic_vector(15 downto 0);
signal LL : std_logic_vector(15 downto 0);
signal SP : std_logic_vector(15 downto 0);
 
-- internal buses
--
signal XX : std_logic_vector(15 downto 0);
signal YY : std_logic_vector(15 downto 0);
signal ZZ : std_logic_vector(15 downto 0);
signal ADR_X : std_logic_vector(15 downto 0);
signal ADR_Z : std_logic_vector(15 downto 0);
signal ADR_YZ : std_logic_vector(15 downto 0);
signal ADR_XYZ : std_logic_vector(15 downto 0);
 
begin
 
alu_8: alu8
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
CLR => CLR,
ALU_OP => OP,
XX => XX,
YY => YY,
ZZ => ZZ
);
 
selyy: select_yy
PORT MAP( SY => SY,
IMM => IMM,
QUICK => QU,
M_RDAT => M_RDAT,
IO_RDAT => IO_RDAT,
RR => RR,
YY => YY
);
 
ADR <= ADR_XYZ;
MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
 
Q_RR <= RR;
Q_LL <= LL;
Q_SP <= SP;
 
-- memory address
--
sel_ax: process(SA(4 downto 3), IMM)
 
variable SAX : std_logic_vector(4 downto 3);
 
begin
SAX := SA(4 downto 3);
 
case SAX is
 
when SA_43_I16 => ADR_X <= IMM;
when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
when others => ADR_X <= b8(SA(3)) & b8(SA(3));
end case;
end process;
 
sel_az: process(SA(2 downto 1), LL, RR, SP)
 
variable SAZ : std_logic_vector(2 downto 1);
 
begin
SAZ := SA(2 downto 1);
 
case SAZ is
when SA_21_0 => ADR_Z <= X"0000";
when SA_21_LL => ADR_Z <= LL;
when SA_21_RR => ADR_Z <= RR;
when others => ADR_Z <= SP;
end case;
end process;
 
sel_ayz: process(SA(0), ADR_Z)
begin
ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
end process;
 
sel_axyz: process(ADR_X, ADR_YZ)
begin
ADR_XYZ <= ADR_X + ADR_YZ;
end process;
 
sel_xx: process(SX, LL, RR, SP, PC)
begin
case SX is
when SX_LL => XX <= LL;
when SX_RR => XX <= RR;
when SX_SP => XX <= SP;
when others => XX <= PC;
end case;
end process;
 
regs: process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
RR <= X"0000";
LL <= X"0000";
SP <= X"0000";
elsif (CE = '1') then
if (WE_RR = '1') then RR <= ZZ; end if;
if (WE_LL = '1') then LL <= ZZ; end if;
 
case WE_SP is
when SP_INC => SP <= ADR_YZ;
when SP_LOAD => SP <= ADR_XYZ;
when SP_NOP => null;
end case;
end if;
end if;
end if;
end process;
 
end Behavioral;
/opcode_fetch.vhd
0,0 → 1,57
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use work.cpu_pack.ALL;
 
entity opcode_fetch is
Port( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
PC_OP : in std_logic_vector( 2 downto 0);
JDATA : in std_logic_vector(15 downto 0);
RR : in std_logic_vector(15 downto 0);
RDATA : in std_logic_vector( 7 downto 0);
 
PC : out std_logic_vector(15 downto 0)
);
end opcode_fetch;
 
architecture Behavioral of opcode_fetch is
 
signal LPC : std_logic_vector(15 downto 0);
signal LRET : std_logic_vector( 7 downto 0);
 
begin
 
PC <= LPC;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then LPC <= X"0000";
elsif (CE = '1') then
case PC_OP is
when PC_NEXT => LPC <= LPC + 1; -- next address
when PC_JMP => LPC <= JDATA; -- jump address
when PC_RETL => LRET <= RDATA; -- return address L
LPC <= LPC + 1;
when PC_RETH => LPC <= RDATA & LRET; -- return address H
when PC_JPRR => LPC <= RR;
when PC_WAIT =>
when others => LPC <= X"0008"; -- interrupt
end case;
end if;
end if;
end if;
end process;
 
end Behavioral;
/ds1722.vhd
0,0 → 1,160
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
entity DS1722 is
Port( CLK_I: in std_logic;
T2: in std_logic;
RESET: in std_logic;
DATA_IN: in std_logic_vector(7 downto 0);
DATA_OUT: out std_logic_vector(7 downto 0);
ADDRESS: in std_logic_vector(7 downto 0);
 
START: in std_logic;
DONE: out std_logic;
TEMP_SPI: out STD_LOGIC; -- Physical interfaes
TEMP_SPO: in STD_LOGIC;
TEMP_CE: out STD_LOGIC;
TEMP_SCLK: out STD_LOGIC
);
end DS1722;
 
architecture DS1722_arch of DS1722 is
 
signal counter : std_logic_vector(7 downto 0);
signal data_latch : std_logic_vector(7 downto 0);
 
type BIG_STATE is ( SET_CE, LATCH_ADD, ADD_OUT_1, ADD_OUT_2,
DATA, WRITE_DATA_1, WRITE_DATA_2, READ_DATA_1, READ_DATA_2,
NEXT_TO_LAST_ONE, LAST_ONE);
 
signal state : BIG_STATE;
 
signal bit_count: INTEGER range 0 to 7;
 
signal Write: std_logic;
 
begin
 
-- Set up counter to sample digital themometer.
process (CLK_I, RESET)
begin
if (RESET = '1') then --asynchronous RESET active High
counter <= "00000000";
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
counter <= counter + "00000001";
end if;
end if;
end process;
 
DONE <= START when (state = LAST_ONE) else '0';
DATA_OUT <= data_latch;
 
Write <= ADDRESS(7);
 
-- process to convert byte commands to SPI and SPI to byte.
process (CLK_I, RESET)
begin
if (RESET='1') then --asynchronous RESET active High
state <= SET_CE;
TEMP_CE <= '0';
TEMP_SCLK <= '0';
bit_count <= 0;
elsif (rising_edge(CLK_I)) then
if (T2 = '1') then
if (counter = "11111111" and START = '1') then
case state is
when SET_CE =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= LATCH_ADD;
bit_count <= 0;
 
when LATCH_ADD =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
state <= ADD_OUT_1;
data_latch <= ADDRESS;
 
when ADD_OUT_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= ADD_OUT_2;
TEMP_SPI <= data_latch(7);
 
when ADD_OUT_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= ADD_OUT_1;
bit_count <= bit_count + 1;
else
state <= DATA;
bit_count <= 0;
end if;
 
when DATA =>
data_latch <= DATA_IN;
TEMP_SCLK <= '0';
TEMP_CE <= '1';
if Write = '0' then
state <= READ_DATA_1;
else
state <= WRITE_DATA_1;
end if;
 
when WRITE_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= WRITE_DATA_2;
TEMP_SPI <= data_latch(7);
 
when WRITE_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & data_latch(7);
if bit_count < 7 then
state <= WRITE_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
 
when READ_DATA_1 =>
TEMP_SCLK <= '1';
TEMP_CE <= '1';
state <= READ_DATA_2;
 
when READ_DATA_2 =>
TEMP_SCLK <= '0';
TEMP_CE <= '1';
data_latch <= data_latch(6 downto 0) & TEMP_SPO;
if bit_count < 7 then
state <= READ_DATA_1;
bit_count <= bit_count + 1;
else
state <= NEXT_TO_LAST_ONE;
bit_count <= 0;
end if;
 
when NEXT_TO_LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= LAST_ONE;
 
when LAST_ONE =>
TEMP_CE <= '0';
TEMP_SCLK <= '0';
state <= SET_CE;
end case;
end if;
end if;
end if;
end process;
 
end DS1722_arch;
/bin_to_7segment.vhd
0,0 → 1,112
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity bin_to_7segment is
Port( CLK_I : in std_logic;
T2 : in std_logic;
PC : in std_logic_vector(15 downto 0);
SEG1 : out std_logic_vector(7 downto 1);
SEG2 : out std_logic_vector(7 downto 0));
end bin_to_7segment;
 
architecture Behavioral of bin_to_7segment is
 
-- +------- middle upper
-- |+------- right upper
-- ||+------ right lower
-- |||+----- middle lower
-- ||||+---- left lower
-- |||||+--- left upper
-- ||||||+-- middle middle
-- |||||||
constant LEDV_0 : std_logic_vector(6 downto 0):= "1111110";-- 0
constant LEDV_1 : std_logic_vector(6 downto 0):= "0110000";-- 1
constant LEDV_2 : std_logic_vector(6 downto 0):= "1101101";-- 2
constant LEDV_3 : std_logic_vector(6 downto 0):= "1111001";-- 3
constant LEDV_4 : std_logic_vector(6 downto 0):= "0110011";-- 4
constant LEDV_5 : std_logic_vector(6 downto 0):= "1011011";-- 5
constant LEDV_6 : std_logic_vector(6 downto 0):= "1011111";-- 6
constant LEDV_7 : std_logic_vector(6 downto 0):= "1110000";-- 7
constant LEDV_8 : std_logic_vector(6 downto 0):= "1111111";-- 8
constant LEDV_9 : std_logic_vector(6 downto 0):= "1111011";-- 9
constant LEDV_A : std_logic_vector(6 downto 0):= "1110111";-- A
constant LEDV_b : std_logic_vector(6 downto 0):= "0011111";-- b
constant LEDV_C : std_logic_vector(6 downto 0):= "1001110";-- C
constant LEDV_d : std_logic_vector(6 downto 0):= "0111101";-- d
constant LEDV_E : std_logic_vector(6 downto 0):= "1001111";-- E
constant LEDV_F : std_logic_vector(6 downto 0):= "1000111";-- F
 
signal LED_CNT : std_logic_vector(24 downto 0);
signal LED_VAL : std_logic_vector(15 downto 0);
 
begin
 
process(CLK_I)
 
variable LED4H, LED4L : std_logic_vector(3 downto 0);
 
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (LED_CNT(24) = '0') then
LED4H := LED_VAL( 7 downto 4);
LED4L := LED_VAL( 3 downto 0);
else
LED4H := LED_VAL(15 downto 12);
LED4L := LED_VAL(11 downto 8);
end if;
 
if (LED_CNT = 0) then LED_VAL <= PC; end if;
LED_CNT <= LED_CNT + 1;
 
case LED4H is
when X"0" => SEG1 <= LEDV_0;
when X"1" => SEG1 <= LEDV_1;
when X"2" => SEG1 <= LEDV_2;
when X"3" => SEG1 <= LEDV_3;
when X"4" => SEG1 <= LEDV_4;
when X"5" => SEG1 <= LEDV_5;
when X"6" => SEG1 <= LEDV_6;
when X"7" => SEG1 <= LEDV_7;
when X"8" => SEG1 <= LEDV_8;
when X"9" => SEG1 <= LEDV_9;
when X"A" => SEG1 <= LEDV_A;
when X"B" => SEG1 <= LEDV_b;
when X"C" => SEG1 <= LEDV_c;
when X"D" => SEG1 <= LEDV_d;
when X"E" => SEG1 <= LEDV_E;
when others => SEG1 <= LEDV_F;
end case;
 
case LED4L is
when X"0" => SEG2(7 downto 1) <= LEDV_0;
when X"1" => SEG2(7 downto 1) <= LEDV_1;
when X"2" => SEG2(7 downto 1) <= LEDV_2;
when X"3" => SEG2(7 downto 1) <= LEDV_3;
when X"4" => SEG2(7 downto 1) <= LEDV_4;
when X"5" => SEG2(7 downto 1) <= LEDV_5;
when X"6" => SEG2(7 downto 1) <= LEDV_6;
when X"7" => SEG2(7 downto 1) <= LEDV_7;
when X"8" => SEG2(7 downto 1) <= LEDV_8;
when X"9" => SEG2(7 downto 1) <= LEDV_9;
when X"A" => SEG2(7 downto 1) <= LEDV_A;
when X"B" => SEG2(7 downto 1) <= LEDV_b;
when X"C" => SEG2(7 downto 1) <= LEDV_c;
when X"D" => SEG2(7 downto 1) <= LEDV_d;
when X"E" => SEG2(7 downto 1) <= LEDV_E;
when others => SEG2(7 downto 1) <= LEDV_F;
end case;
 
SEG2(0) <= LED_CNT(24);
end if;
end if;
end process;
 
end Behavioral;
/uart_rx.vhd
0,0 → 1,88
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity UART_RX is
PORT( CLK_I : in std_logic;
CLR : in std_logic;
CE_16 : in std_logic; -- 16 times baud rate
SER_IN : in std_logic; -- Serial input line
 
DATA : out std_logic_vector(7 downto 0);
DATA_FLAG : out std_logic -- toggle on every byte received
);
end UART_RX;
 
architecture RX_UART_arch of UART_RX is
 
signal POSITION : std_logic_vector(7 downto 0); -- sample position
signal BUF : std_logic_vector(9 downto 0);
signal LDATA_FLAG : std_logic;
signal SER_IN1 : std_logic; -- double clock the input
signal SER_HOT : std_logic; -- double clock the input
 
begin
 
-- double clock the input data...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
SER_IN1 <= '1';
SER_HOT <= '1';
else
SER_IN1 <= SER_IN;
SER_HOT <= SER_IN1;
end if;
end if;
end process;
 
DATA_FLAG <= LDATA_FLAG;
 
process(CLK_I, POSITION)
 
variable START_BIT : boolean;
variable STOP_BIT : boolean;
variable STOP_POS : boolean;
 
begin
START_BIT := POSITION(7 downto 4) = X"0";
STOP_BIT := POSITION(7 downto 4) = X"9";
STOP_POS := STOP_BIT and POSITION(3 downto 2) = "11"; -- 3/4 of stop bit
 
if (rising_edge(CLK_I)) then
if (CLR = '1') then
LDATA_FLAG <= '0';
POSITION <= X"00"; -- idle
BUF <= "1111111111";
DATA <= "00000000";
elsif (CE_16 = '1') then
if (POSITION = X"00") then -- uart idle
BUF <= "1111111111";
if (SER_HOT = '0') then -- start bit received
POSITION <= X"01";
end if;
else
POSITION <= POSITION + X"01";
if (POSITION(3 downto 0) = "0111") then -- 1/2 of the bit
BUF <= SER_HOT & BUF(9 downto 1); -- sample data
-- validate start bit
--
if (START_BIT and SER_HOT = '1') then -- inside start bit
POSITION <= X"00";
end if;
 
if (STOP_BIT) then -- inside stop bit
DATA <= BUF(9 downto 2);
end if;
elsif (STOP_POS) then -- 3/4 of stop bit
LDATA_FLAG <= LDATA_FLAG xor (BUF(9) and not BUF(0));
POSITION <= X"00";
end if;
end if;
end if;
end if;
end process;
 
end RX_UART_arch;
/cpu_pack.vhd
0,0 → 1,247
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package cpu_pack is
type cycle is ( M1, M2, M3, M4, M5 );
 
type op_category is (
INTR,
HALT_WAIT,
 
-- 0X
HALT,
NOP,
JMP_i,
JMP_RRNZ_i,
JMP_RRZ_i,
CALL_i,
CALL_RR,
RET,
MOVE_SPi_RR,
MOVE_SPi_RS,
MOVE_SPi_RU,
MOVE_SPi_LL,
MOVE_SPi_LS,
MOVE_SPi_LU,
MOVE_RR_dSP,
MOVE_R_dSP,
 
-- 1X
AND_RR_i,
OR_RR_i,
XOR_RR_i,
SEQ_RR_i,
SNE_RR_i,
SGE_RR_i,
SGT_RR_i,
SLE_RR_i,
 
-- 2X
SLT_RR_i,
SHS_RR_i,
SHI_RR_i,
SLS_RR_i,
SLO_RR_i,
CLRW_dSP,
CLRB_dSP,
IN_ci_RU,
OUT_R_ci,
 
-- 3X
AND_LL_RR,
OR_LL_RR,
XOR_LL_RR,
SEQ_LL_RR,
SNE_LL_RR,
SGE_LL_RR,
SGT_LL_RR,
SLE_LL_RR,
SLT_LL_RR,
SHS_LL_RR,
SHI_LL_RR,
SLS_LL_RR,
SLO_LL_RR,
LNOT_RR,
NEG_RR,
NOT_RR,
 
-- 4X
MOVE_LL_RR,
MOVE_LL_cRR,
MOVE_L_cRR,
MOVE_RR_LL,
MOVE_RR_cLL,
MOVE_R_cLL,
MOVE_cRR_RR,
MOVE_cRR_RS,
MOVE_cRR_RU,
MOVE_ci_RR,
MOVE_ci_RS,
MOVE_ci_RU,
MOVE_ci_LL,
MOVE_ci_LS,
MOVE_ci_LU,
MOVE_RR_SP,
 
-- 5X
LSL_RR_i,
ASR_RR_i,
LSR_RR_i,
LSL_LL_RR,
ASR_LL_RR,
LSR_LL_RR,
ADD_LL_RR,
SUB_LL_RR,
MOVE_RR_ci,
MOVE_R_ci,
MOVE_RR_uSP,
MOVE_R_uSP,
 
-- 6X
MOVE_uSP_RR,
MOVE_uSP_RS,
MOVE_uSP_RU,
MOVE_uSP_LL,
MOVE_uSP_LS,
MOVE_uSP_LU,
LEA_uSP_RR,
MOVE_dRR_dLL,
MOVE_RRi_LLi,
 
-- 7X
MUL_IS,
MUL_IU,
DIV_IS,
DIV_IU,
MD_STEP,
MD_FIN,
MOD_FIN,
EI,
RETI,
DI,
 
-- 9X ... FX
ADD_RR_I,
SUB_RR_I,
MOVE_I_RR,
ADD_SP_I,
SEQ_LL_I,
MOVE_I_LL,
undef );
 
type SP_OP is ( SP_NOP, SP_INC, SP_LOAD );
 
-- ALU codes
--
constant ALU_X_HS_Y : std_logic_vector(4 downto 0) := "00000";
constant ALU_X_LO_Y : std_logic_vector(4 downto 0) := "00001";
constant ALU_X_HI_Y : std_logic_vector(4 downto 0) := "00010";
constant ALU_X_LS_Y : std_logic_vector(4 downto 0) := "00011";
constant ALU_X_GE_Y : std_logic_vector(4 downto 0) := "00100";
constant ALU_X_LT_Y : std_logic_vector(4 downto 0) := "00101";
constant ALU_X_GT_Y : std_logic_vector(4 downto 0) := "00110";
constant ALU_X_LE_Y : std_logic_vector(4 downto 0) := "00111";
constant ALU_X_EQ_Y : std_logic_vector(4 downto 0) := "01000";
constant ALU_X_NE_Y : std_logic_vector(4 downto 0) := "01001";
 
constant ALU_NEG_Y : std_logic_vector(4 downto 0) := "01100";
constant ALU_X_SUB_Y : std_logic_vector(4 downto 0) := "01101";
constant ALU_MOVE_Y : std_logic_vector(4 downto 0) := "01110";
constant ALU_X_ADD_Y : std_logic_vector(4 downto 0) := "01111";
 
constant ALU_X_AND_Y : std_logic_vector(4 downto 0) := "10000";
constant ALU_X_OR_Y : std_logic_vector(4 downto 0) := "10001";
constant ALU_X_XOR_Y : std_logic_vector(4 downto 0) := "10010";
constant ALU_NOT_Y : std_logic_vector(4 downto 0) := "10011";
 
constant ALU_X_LSR_Y : std_logic_vector(4 downto 0) := "10100";
constant ALU_X_ASR_Y : std_logic_vector(4 downto 0) := "10101";
constant ALU_X_LSL_Y : std_logic_vector(4 downto 0) := "10110";
constant ALU_X_MIX_Y : std_logic_vector(4 downto 0) := "10111";
 
constant ALU_MUL_IU : std_logic_vector(4 downto 0) := "11000";
constant ALU_MUL_IS : std_logic_vector(4 downto 0) := "11001";
constant ALU_DIV_IU : std_logic_vector(4 downto 0) := "11010";
constant ALU_DIV_IS : std_logic_vector(4 downto 0) := "11011";
 
constant ALU_MD_STP : std_logic_vector(4 downto 0) := "11100";
constant ALU_MD_FIN : std_logic_vector(4 downto 0) := "11101";
constant ALU_MOD_FIN : std_logic_vector(4 downto 0) := "11110";
 
constant ALU_ANY : std_logic_vector(4 downto 0) := ALU_X_AND_Y;
--------------------------------------------------------------
constant SA_43_0 : std_logic_vector(1 downto 0) := "00";
constant SA_43_FFFF : std_logic_vector(1 downto 0) := "01"; -- last bit 1 !!!
constant SA_43_I16 : std_logic_vector(1 downto 0) := "10";
constant SA_43_I8S : std_logic_vector(1 downto 0) := "11";
 
constant SA_21_0 : std_logic_vector(1 downto 0) := "00";
constant SA_21_LL : std_logic_vector(1 downto 0) := "01";
constant SA_21_RR : std_logic_vector(1 downto 0) := "10";
constant SA_21_SP : std_logic_vector(1 downto 0) := "11";
 
constant ADR_cSP_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '0';
constant ADR_cRR_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '0';
constant ADR_cLL_L : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '0';
constant ADR_cI16_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '0';
constant ADR_16SP_L : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '0';
constant ADR_8SP_L : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '0';
constant ADR_IO : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_0 & '0';
 
constant ADR_cSP_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_SP & '1';
constant ADR_cRR_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_RR & '1';
constant ADR_cLL_H : std_logic_vector(4 downto 0) := SA_43_0 & SA_21_LL & '1';
constant ADR_cI16_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_0 & '1';
constant ADR_16SP_H : std_logic_vector(4 downto 0) := SA_43_I16 & SA_21_SP & '1';
constant ADR_8SP_H : std_logic_vector(4 downto 0) := SA_43_I8S & SA_21_SP & '1';
 
constant ADR_dSP : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '0';
constant ADR_dRR : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_RR & '0';
constant ADR_dLL : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_LL & '0';
constant ADR_SPi : std_logic_vector(4 downto 0) := SA_43_FFFF & SA_21_SP & '1';
constant ADR_RRi : std_logic_vector(4 downto 0) := ADR_cRR_L;
constant ADR_LLi : std_logic_vector(4 downto 0) := ADR_cLL_L;
--------------------------------------------------------------
constant SX_LL : std_logic_vector(1 downto 0) := "00";
constant SX_RR : std_logic_vector(1 downto 0) := "01";
constant SX_SP : std_logic_vector(1 downto 0) := "10";
constant SX_PC : std_logic_vector(1 downto 0) := "11";
constant SX_ANY : std_logic_vector(1 downto 0) := SX_RR;
--------------------------------------------------------------
constant SY_SY0 : std_logic_vector(3 downto 0) := "0000";
constant SY_SY1 : std_logic_vector(3 downto 0) := "0001";
constant SY_SY2 : std_logic_vector(3 downto 0) := "0010";
constant SY_SY3 : std_logic_vector(3 downto 0) := "0011";
constant SY_I16 : std_logic_vector(3 downto 0) := "0100";
constant SY_RR : std_logic_vector(3 downto 0) := "0101";
 
constant SY_SI8 : std_logic_vector(3 downto 0) := "1000";
constant SY_UI8 : std_logic_vector(3 downto 0) := "1001";
constant SY_SQ : std_logic_vector(3 downto 0) := "1010";
constant SY_UQ : std_logic_vector(3 downto 0) := "1011";
constant SY_SM : std_logic_vector(3 downto 0) := "1100";
constant SY_UM : std_logic_vector(3 downto 0) := "1101";
constant SY_IO : std_logic_vector(3 downto 0) := "1110";
constant SY_ANY : std_logic_vector(3 downto 0) := SY_RR;
--------------------------------------------------------------
constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- count up
constant PC_JMP : std_logic_vector(2 downto 0) := "001"; -- JMP/CALL
constant PC_RETH : std_logic_vector(2 downto 0) := "010"; -- RET (H)
constant PC_RETL : std_logic_vector(2 downto 0) := "011"; -- RET (L)
constant PC_WAIT : std_logic_vector(2 downto 0) := "100"; -- WAIT
constant PC_JPRR : std_logic_vector(2 downto 0) := "101"; -- JMP (RR)
constant PC_INT : std_logic_vector(2 downto 0) := "110"; -- INT
--------------------------------------------------------------
 
end cpu_pack;
 
package body cpu_pack is
end cpu_pack;
/cpu_test.vhd
0,0 → 1,119
 
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
use work.cpu_pack.ALL;
 
ENTITY testbench IS
END testbench;
 
ARCHITECTURE behavior OF testbench IS
 
COMPONENT cpu16
PORT(
clk : IN std_logic;
cck : IN std_logic;
switch : IN std_logic_vector(9 downto 0);
ser_in : IN std_logic;
temp_spo : IN std_logic;
xm_rdat : IN std_logic_vector(7 downto 0);
ser_out : OUT std_logic;
temp_spi : OUT std_logic;
temp_ce : OUT std_logic;
temp_sclk : OUT std_logic;
seg1 : OUT std_logic_vector(7 downto 0);
seg2 : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
xm_adr : OUT std_logic_vector(15 downto 0);
xm_wdat : OUT std_logic_vector(7 downto 0);
xm_we : OUT std_logic;
xm_ce : OUT std_logic
);
END COMPONENT;
 
signal clk : std_logic;
signal cck : std_logic;
signal switch : std_logic_vector(9 downto 0) := "0000000000";
signal ser_in : std_logic := '0';
signal temp_spo : std_logic := '0';
signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
signal ser_out : std_logic;
signal temp_spi : std_logic := '0';
signal temp_ce : std_logic;
signal temp_sclk : std_logic;
signal seg1 : std_logic_vector(7 downto 0) := X"00";
signal seg2 : std_logic_vector(7 downto 0) := X"00";
signal led : std_logic_vector(7 downto 0);
signal xm_adr : std_logic_vector(15 downto 0);
signal xm_wdat : std_logic_vector(7 downto 0);
signal xm_we : std_logic;
signal xm_ce : std_logic;
 
signal clk_counter : INTEGER := 0;
 
BEGIN
 
uut: cpu16 PORT MAP(
clk => clk,
cck => cck,
switch => switch,
ser_in => ser_in,
ser_out => ser_out,
temp_spo => temp_spo,
temp_spi => temp_spi,
temp_ce => temp_ce,
temp_sclk => temp_sclk,
seg1 => seg1,
seg2 => seg2,
led => led,
xm_adr => xm_adr,
xm_rdat => xm_rdat,
xm_wdat => xm_wdat,
xm_we => xm_we,
xm_ce => xm_ce
);
 
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK <= transport '0';
WAIT FOR 1 ns;
CLK <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
 
PROCESS(CLK)
BEGIN
if (rising_edge(CLK)) then
CLK_COUNTER <= CLK_COUNTER + 1;
 
case CLK_COUNTER is
when 0 => switch(9 downto 8) <= "11";
when 1 => switch(9 downto 8) <= "00";
 
 
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
 
END;
/uart_tx.vhd
0,0 → 1,71
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity UART_TX is
PORT( CLK_I : in std_logic;
CLR : in std_logic; -- RESET
CE_16 : in std_logic; -- BUAD rate clock
DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
DATA_FLAG : in std_logic; -- toggle to send data
SER_OUT : out std_logic; -- Serial output line
DATA_FLAGQ : out std_logic -- Transmitting Flag
);
end UART_TX;
 
 
architecture TX_UART_arch of UART_TX is
 
signal BUF : std_logic_vector(7 downto 0);
signal TODO : integer range 0 to 9; -- bits to send
signal FLAGQ : std_logic;
signal CE_1 : std_logic;
signal C16 : std_logic_vector(3 downto 0);
 
begin
 
DATA_FLAGQ <= FLAGQ;
 
-- generate a CE_1 every 16 CE_16...
--
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
CE_1 <= '0';
if (CLR = '1') then
C16 <= "0000";
elsif (CE_16 = '1') then
if (C16 = "1111") then
CE_1 <= '1';
end if;
C16 <= C16 + "0001";
end if;
end if;
end process;
 
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
SER_OUT <= '1';
BUF <= "11111111";
TODO <= 0;
FLAGQ <= DATA_FLAG; -- idle
elsif (CE_1 = '1') then
if (TODO > 0) then -- transmitting
SER_OUT <= BUF(0); -- next bit
BUF <= '1' & BUF(7 downto 1);
if (TODO = 1) then
FLAGQ <= DATA_FLAG;
end if;
TODO <= TODO - 1;
elsif (FLAGQ /= DATA_FLAG) then -- new byte
SER_OUT <= '0'; -- start bit
TODO <= 9;
BUF <= DATA;
end if;
end if;
end if;
end process;
 
end TX_UART_arch;
/cpu.vhd
0,0 → 1,226
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 
use work.cpu_pack.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity cpu16 is
PORT( CLK_I : in STD_LOGIC;
T2 : out STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
 
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
 
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
 
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
 
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
end cpu16;
 
architecture behavioral of cpu16 is
 
COMPONENT bin_to_7segment
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
PC : IN std_logic_vector(15 downto 0);
SEG1 : OUT std_logic_vector(7 downto 1);
SEG2 : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
 
COMPONENT cpu_engine
PORT( CLK_I : in std_logic;
T2 : out std_logic;
CLR : in std_logic;
Q_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector( 7 downto 0);
Q_CAT : out op_category;
Q_IMM : out std_logic_vector(15 downto 0);
Q_CYC : out cycle;
 
-- input/output
INT : in std_logic;
IO_ADR : out std_logic_vector(7 downto 0);
IO_RD : out std_logic;
IO_WR : out std_logic;
IO_RDAT : in std_logic_vector( 7 downto 0);
 
-- memory
XM_ADR : out std_logic_vector(15 downto 0);
XM_RDAT : in std_logic_vector( 7 downto 0);
XM_WDAT : out std_logic_vector( 7 downto 0);
XM_WE : out std_logic;
XM_CE : out std_logic;
 
-- select signals
Q_SX : out std_logic_vector(1 downto 0);
Q_SY : out std_logic_vector(3 downto 0);
Q_OP : out std_logic_vector(4 downto 0);
Q_SA : out std_logic_vector(4 downto 0);
Q_SMQ : out std_logic;
 
-- write enable/select signal
Q_WE_RR : out std_logic;
Q_WE_LL : out std_logic;
Q_WE_SP : out SP_OP;
 
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0);
HALT : out std_logic
);
END COMPONENT;
 
COMPONENT input_output
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : OUT std_logic;
 
TEMP_SPO : IN std_logic;
TEMP_SPI : OUT std_logic;
TEMP_CE : OUT std_logic;
TEMP_SCLK : OUT std_logic;
 
SER_IN : IN std_logic;
SER_OUT : OUT std_logic;
 
SWITCH : IN std_logic_vector(9 downto 0);
LED : OUT std_logic_vector(7 downto 0);
 
IO_RD : IN std_logic;
IO_WR : IN std_logic;
IO_ADR : IN std_logic_vector(7 downto 0);
IO_WDAT : IN std_logic_vector(7 downto 0);
IO_RDAT : OUT std_logic_vector(7 downto 0);
INT : OUT std_logic;
HALT : in std_logic
);
END COMPONENT;
 
signal CLR : std_logic;
signal LT2 : std_logic;
 
signal ADR : std_logic_vector(15 downto 0);
 
signal HALT : std_logic;
signal INT : std_logic;
signal IO_RD : std_logic;
signal IO_WR : std_logic;
signal IO_ADR : std_logic_vector( 7 downto 0);
signal IO_RDAT : std_logic_vector( 7 downto 0);
signal IOM_WDAT : std_logic_vector( 7 downto 0);
signal PC : std_logic_vector(15 downto 0);
 
signal Q_C_SX : std_logic_vector(1 downto 0);
signal Q_C_SY : std_logic_vector(3 downto 0);
signal Q_C_OP : std_logic_vector(4 downto 0);
signal Q_C_SA : std_logic_vector(4 downto 0);
signal Q_C_SMQ : std_logic;
 
signal Q_C_WE_RR : std_logic;
signal Q_C_WE_LL : std_logic;
signal Q_C_WE_SP : SP_OP;
 
signal Q_C_RR : std_logic_vector(15 downto 0);
signal Q_C_LL : std_logic_vector(15 downto 0);
signal Q_C_SP : std_logic_vector(15 downto 0);
 
signal Q_C_OPC : std_logic_vector( 7 downto 0);
signal Q_C_CAT : op_category;
signal Q_C_IMM : std_logic_vector(15 downto 0);
signal Q_C_CYC : cycle;
 
begin
 
T2 <= LT2;
SEG1(0) <= HALT;
XM_ADR <= ADR;
XM_WDAT <= IOM_WDAT;
 
seg7: bin_to_7segment
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
PC => PC,
SEG1 => SEG1(7 downto 1),
SEG2 => SEG2
);
 
eng: cpu_engine
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR, -- SW-1 (RESET)
Q_PC => PC,
Q_OPC => Q_C_OPC,
Q_CAT => Q_C_CAT,
Q_IMM => Q_C_IMM,
Q_CYC => Q_C_CYC,
 
INT => INT,
IO_ADR => IO_ADR,
IO_RD => IO_RD,
IO_WR => IO_WR,
IO_RDAT => IO_RDAT,
 
XM_ADR => ADR,
XM_RDAT => XM_RDAT,
XM_WDAT => IOM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
 
Q_SX => Q_C_SX,
Q_SY => Q_C_SY,
Q_OP => Q_C_OP,
Q_SA => Q_C_SA,
Q_SMQ => Q_C_SMQ,
 
Q_WE_RR => Q_C_WE_RR,
Q_WE_LL => Q_C_WE_LL,
Q_WE_SP => Q_C_WE_SP,
 
Q_RR => Q_C_RR,
Q_LL => Q_C_LL,
Q_SP => Q_C_SP,
HALT => HALT
);
 
io: input_output
PORT MAP( CLK_I => CLK_I,
T2 => LT2,
CLR => CLR,
 
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
 
SER_IN => SER_IN,
SER_OUT => SER_OUT,
 
SWITCH => SWITCH,
LED => LED,
 
IO_RD => IO_RD,
IO_WR => IO_WR,
IO_ADR => IO_ADR,
IO_RDAT => IO_RDAT,
IO_WDAT => IOM_WDAT,
INT => INT,
HALT => HALT
);
 
end behavioral;
/test.tbw Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/test.tbw
test.tbw Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: board_cpu.bit =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: board_cpu.bit =================================================================== --- board_cpu.bit (nonexistent) +++ board_cpu.bit (revision 26)
board_cpu.bit Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: temperature.vhd =================================================================== --- temperature.vhd (nonexistent) +++ temperature.vhd (revision 26) @@ -0,0 +1,127 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +entity temperature is + PORT( CLK_I : in STD_LOGIC; + T2 : in STD_LOGIC; + CLR : in STD_LOGIC; + DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0); + TEMP_SPI : out STD_LOGIC; + TEMP_SPO : in STD_LOGIC; + TEMP_CE : out STD_LOGIC; + TEMP_SCLK : out STD_LOGIC + ); +end temperature; + +architecture behavioral of temperature is + + component DS1722 + PORT( RESET : in std_logic; + CLK_I : in std_logic; + T2 : in std_logic; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + ADDRESS : in std_logic_vector(7 downto 0); + + START : in std_logic; + DONE : out std_logic; + + TEMP_SPI : out STD_LOGIC; + TEMP_SPO : in STD_LOGIC; + TEMP_CE : out STD_LOGIC; + TEMP_SCLK : out STD_LOGIC + ); +end component; + + signal TEMP_DATA_IN : STD_LOGIC_VECTOR (7 downto 0); + signal TEMP_DATA_OUT : STD_LOGIC_VECTOR (7 downto 0); + signal TEMP_ADDRESS : STD_LOGIC_VECTOR (7 downto 0); + signal TEMP_START : std_logic; + signal TEMP_DONE : std_logic; + + type TEMPERATURE_STATES is (TEMP_IDLE, TEMP_SETUP, TEMP_SETUP_COMPLETE, + TEMP_GET_DATA, TEMP_GET_DATA_COMPLETE); + signal TEMP_state : TEMPERATURE_STATES; + +begin + + tsensor: DS1722 + PORT MAP( CLK_I => CLK_I, + T2 => T2, + RESET => CLR, + + DATA_IN => TEMP_DATA_IN, + DATA_OUT => TEMP_DATA_OUT, + ADDRESS => TEMP_ADDRESS, + + START => TEMP_START, + DONE => TEMP_DONE, + + TEMP_SPI => TEMP_SPI, + TEMP_SPO => TEMP_SPO, + TEMP_CE => TEMP_CE, + TEMP_SCLK => TEMP_SCLK + ); + +-- State machine to step though the process of getting data from the Digital Thermometer. + process (CLR, CLK_I) + begin + if (CLR = '1') then + TEMP_state <= TEMP_IDLE; + TEMP_START <= '0'; + TEMP_ADDRESS <= "00000000"; + TEMP_DATA_IN <= "00000000"; + elsif (rising_edge(CLK_I)) then + if (T2 = '1') then + case TEMP_state is + when TEMP_IDLE => + TEMP_START <= '0'; + TEMP_ADDRESS <= "00000000"; + TEMP_DATA_IN <= "00000000"; + TEMP_state <= TEMP_SETUP; + + when TEMP_SETUP => + TEMP_ADDRESS <= "10000000"; + TEMP_DATA_IN <= "11101000"; + if (TEMP_DONE = '1') then + TEMP_state <= TEMP_SETUP_COMPLETE; + TEMP_START <= '0'; + else + TEMP_state <= TEMP_SETUP; + TEMP_START <= '1'; + end if; + + when TEMP_SETUP_COMPLETE => + TEMP_START <= '0'; + if (TEMP_DONE = '1') then + TEMP_state <= TEMP_SETUP_COMPLETE; + else + TEMP_state <= TEMP_GET_DATA; + end if; + + when TEMP_GET_DATA => + TEMP_ADDRESS <= "00000010"; + if (TEMP_DONE = '1') then + TEMP_state <= TEMP_GET_DATA_COMPLETE; + DATA_OUT <= TEMP_DATA_OUT; + TEMP_START <= '0'; + else + TEMP_state <= TEMP_GET_DATA; + TEMP_START <= '1'; + end if; + + when TEMP_GET_DATA_COMPLETE => + TEMP_START <= '0'; + if (TEMP_DONE = '1') then + TEMP_state <= TEMP_GET_DATA_COMPLETE; + else + TEMP_state <= TEMP_GET_DATA; + end if; + end case; + end if; + end if; + end process; + +end behavioral; Index: opcode_decoder.vhd =================================================================== --- opcode_decoder.vhd (nonexistent) +++ opcode_decoder.vhd (revision 26) @@ -0,0 +1,1359 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following lines to use the declarations that are +-- provided for instantiating Xilinx primitive components. +--library UNISIM; +--use UNISIM.VComponents.all; + +use work.cpu_pack.ALL; + +entity opcode_decoder is + PORT( CLK_I : IN std_logic; + T2 : IN std_logic; + CLR : IN std_logic; + CE : IN std_logic; + OPCODE : IN std_logic_vector(7 downto 0); + OP_CYC : IN cycle; + INT : IN std_logic; + RRZ : IN std_logic; + + OP_CAT : OUT op_category; + + -- select signals + D_SX : out std_logic_vector(1 downto 0); -- ALU select X + D_SY : out std_logic_vector(3 downto 0); -- ALU select Y + D_OP : out std_logic_vector(4 downto 0); -- ALU operation + D_SA : out std_logic_vector(4 downto 0); -- select address + D_SMQ : out std_logic; + + -- write enable/select signal + D_WE_RR : out std_logic; + D_WE_LL : out std_logic; + D_WE_M : out std_logic; + D_WE_SP : out SP_OP; + + -- input/output + IO_RD : out std_logic; + IO_WR : out std_logic; + + PC_OP : out std_logic_vector(2 downto 0); + + LAST_M : out std_logic; -- last M cycle of an opcode + HLT : out std_logic + ); +end opcode_decoder; + +architecture Behavioral of opcode_decoder is + + function pc(A : std_logic; + OP : std_logic_vector(2 downto 0)) return std_logic_vector is + begin + if (A = '1') then return OP; + else return PC_NEXT; + end if; + end; + + function hadr( A : std_logic; + ADR : std_logic_vector(4 downto 0)) return std_logic_vector is + begin + return ADR(4 downto 1) & A; + end; + + function mix(A : std_logic) return std_logic_vector is + begin + if (A = '1') then return ALU_X_MIX_Y; + else return ALU_MOVE_Y; + end if; + end; + + function sp(A : std_logic; + OP : SP_OP) return SP_OP is + begin + if (A = '1') then return OP; + else return SP_NOP; + end if; + end; + + signal LAST : cycle; + + signal ENABLE_INT : std_logic; + signal DISABLE_INT : std_logic; + signal DISABLE_CNT : std_logic_vector(3 downto 0); + + signal HALT_REQ : std_logic; + signal UNHALT_REQ : std_logic; + signal HALTED : std_logic; + signal SERVE_INT : std_logic; + signal INT_ACK : std_logic; + +begin + + LAST_M <= '1' when (OP_CYC = LAST) else '0'; + + HLT <= HALTED; + + process(CLK_I) + begin + if (rising_edge(CLK_I)) then + if (T2 = '1') then + if (CLR = '1') then + DISABLE_CNT <= "0001"; -- 1 x disabled + INT_ACK <= '0'; + HALTED <= '0'; + elsif (CE = '1') then + if (DISABLE_INT = '1') then + DISABLE_CNT <= DISABLE_CNT + 1; + elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then + DISABLE_CNT <= DISABLE_CNT - 1; + end if; + + if (UNHALT_REQ = '1') then + HALTED <= '0'; + elsif (HALT_REQ = '1') then + HALTED <= '1'; + end if; + + INT_ACK <= SERVE_INT; + end if; + end if; + end if; + end process; + + process(OPCODE, OP_CYC, INT, RRZ, INT_ACK, DISABLE_CNT, HALTED) + + variable IS_M1 : std_logic; + variable IS_M2, IS_M1_M2 : std_logic; + variable IS_M3, IS_M2_M3 : std_logic; + variable IS_M4, IS_M3_M4 : std_logic; + variable IS_M5 : std_logic; + + begin + if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if; + if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if; + if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if; + if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if; + if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if; + + IS_M1_M2 := IS_M1 or IS_M2; + IS_M2_M3 := IS_M2 or IS_M3; + IS_M3_M4 := IS_M3 or IS_M4; + + -- default: NOP + -- + OP_CAT <= undef; + D_SX <= SX_ANY; + D_SY <= SY_ANY; + D_OP <= "00000"; + D_SA <= "00000"; + D_SMQ <= '0'; + D_WE_RR <= '0'; + D_WE_LL <= '0'; + D_WE_M <= '0'; + D_WE_SP <= SP_NOP; + IO_RD <= '0'; + IO_WR <= '0'; + PC_OP <= PC_NEXT; + LAST <= M1; -- default: single cycle opcode (M1 only) + ENABLE_INT <= '0'; + DISABLE_INT <= '0'; + HALT_REQ <= '0'; + UNHALT_REQ <= '0'; + SERVE_INT <= '0'; + + if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or + or INT_ACK = '1' ) then -- continue INT + OP_CAT <= INTR; + LAST <= M2; + SERVE_INT <= IS_M1; -- assert INT_ACK in M2 + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_PC; + D_SY <= SY_SY0; -- PC + 0 (current PC) + D_SA <= ADR_dSP; + PC_OP <= pc(IS_M1, PC_INT); + D_WE_M <= IS_M1_M2; + D_SMQ <= IS_M1; + D_WE_SP <= sp(IS_M1_M2, SP_LOAD); + DISABLE_INT <= '1'; + UNHALT_REQ <= '1'; + + elsif (HALTED = '1') then + OP_CAT <= HALT_WAIT; + LAST <= M2; + PC_OP <= PC_WAIT; + + elsif (OPCODE(7) = '1') then + case OPCODE(6 downto 4) is + when "010" => + OP_CAT <= ADD_RR_I; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_RR; + D_SY <= SY_UQ; + D_WE_RR <= IS_M1; + + when "011" => + OP_CAT <= SUB_RR_I; + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_RR; + D_SY <= SY_UQ; + D_WE_RR <= IS_M1; + + when "100" => + OP_CAT <= MOVE_I_RR; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SQ; + D_WE_RR <= IS_M1; + + when "101" => + OP_CAT <= SEQ_LL_I; + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_LL; + D_SY <= SY_SQ; + D_WE_RR <= IS_M1; -- !! RR + + when "110" => + OP_CAT <= MOVE_I_LL; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UQ; + D_WE_LL <= IS_M1; + + when "111" => + case OPCODE(3 downto 0) is + when "0100" => + OP_CAT <= ADD_RR_I; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + LAST <= M3; + D_WE_RR <= IS_M3; + + when "0101" => + OP_CAT <= ADD_RR_I; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + LAST <= M2; + D_WE_RR <= IS_M2; + + when "0110" => + OP_CAT <= SUB_RR_I; + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + LAST <= M3; + D_WE_RR <= IS_M3; + + when "0111" => + OP_CAT <= SUB_RR_I; + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + LAST <= M2; + D_WE_RR <= IS_M2; + + when "1000" => + OP_CAT <= MOVE_I_RR; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_I16; + LAST <= M3; + D_WE_RR <= IS_M3; + + when "1001" => + OP_CAT <= MOVE_I_RR; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SI8; + LAST <= M2; + D_WE_RR <= IS_M2; + + when "1010" => + OP_CAT <= SEQ_LL_I; + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_LL; + D_SY <= SY_I16; + LAST <= M3; + D_WE_RR <= IS_M3; -- SEQ sets RR ! + + when "1011" => + OP_CAT <= SEQ_LL_I; + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_LL; + D_SY <= SY_SI8; + LAST <= M2; + D_WE_RR <= IS_M2; -- SEQ sets RR ! + + when "1100" => + OP_CAT <= MOVE_I_LL; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_I16; + LAST <= M3; + D_WE_LL <= IS_M3; + + when "1101" => + OP_CAT <= MOVE_I_LL; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SI8; + LAST <= M2; + D_WE_LL <= IS_M2; + + when others => -- undefined + end case; + + when others => -- undefined + end case; + else + case OPCODE(6 downto 0) is + -- 00000000000000000000000000000000000000000000000000000000000000000000 + when "0000000" => + OP_CAT <= HALT; + HALT_REQ <= '1'; + PC_OP <= PC_WAIT; + + when "0000001" => + OP_CAT <= NOP; + + when "0000010" => + OP_CAT <= JMP_i; + LAST <= M3; + PC_OP <= pc(IS_M2, PC_JMP); + + when "0000011" => + OP_CAT <= JMP_RRNZ_i; + LAST <= M3; + PC_OP <= pc(IS_M2 and not RRZ, PC_JMP); + + when "0000100" => + OP_CAT <= JMP_RRZ_i; + LAST <= M3; + PC_OP <= pc(IS_M2 and RRZ, PC_JMP); + + when "0000101" => + OP_CAT <= CALL_i; + LAST <= M3; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_PC; + D_SY <= SY_SY3; -- PC + 3 + D_SA <= ADR_dSP; + PC_OP <= pc(IS_M2, PC_JMP); + D_WE_M <= IS_M1_M2; + D_SMQ <= IS_M1; + D_WE_SP <= sp(IS_M1_M2, SP_LOAD); + + when "0000110" => + OP_CAT <= CALL_RR; + LAST <= M2; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_PC; + D_SY <= SY_SY1; -- PC + 1 + D_SA <= ADR_dSP; + PC_OP <= pc(IS_M1, PC_JPRR); + D_WE_M <= IS_M1_M2; + D_SMQ <= IS_M1; + D_WE_SP <= sp(IS_M1_M2, SP_LOAD); + + when "0000111" | "1111000" => + if (OPCODE(0) = '1') then + OP_CAT <= RET; + else + OP_CAT <= RETI; + ENABLE_INT <= '1'; + end if; + + LAST <= M5; + D_SA <= ADR_SPi; -- read address: (SP)+ + D_WE_SP <= sp(IS_M1_M2, SP_INC); + case OP_CYC is + when M1 => PC_OP <= PC_WAIT; + when M2 => PC_OP <= PC_WAIT; + when M3 => PC_OP <= PC_RETL; + when M4 => PC_OP <= PC_RETH; + when others => + end case; + + when "0001000" => + OP_CAT <= MOVE_SPi_RR; + D_SX <= SX_RR; + D_SY <= SY_UM; + D_SA <= ADR_SPi; + LAST <= M3; + PC_OP <= pc(IS_M1_M2, PC_WAIT); + D_WE_RR <= IS_M2_M3; + D_WE_SP <= sp(IS_M1_M2, SP_INC); + D_OP <= mix(IS_M3); + + when "0001001" => + OP_CAT <= MOVE_SPi_RS; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SM; + D_SA <= ADR_SPi; + D_WE_RR <= IS_M2; + PC_OP <= pc(IS_M1, PC_WAIT); + D_WE_SP <= sp(IS_M1, SP_INC); + + when "0001010" => + OP_CAT <= MOVE_SPi_RU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_SPi; + PC_OP <= pc(IS_M1, PC_WAIT); + D_WE_SP <= sp(IS_M1, SP_INC); + D_WE_RR <= IS_M2; + + when "0001011" => + OP_CAT <= MOVE_SPi_LL; + LAST <= M3; + D_SX <= SX_LL; + D_SY <= SY_UM; + D_SA <= ADR_SPi; + PC_OP <= pc(IS_M1_M2, PC_WAIT); + D_WE_SP <= sp(IS_M1_M2, SP_INC); + D_WE_LL <= IS_M2_M3; + D_OP <= mix(IS_M3); + + when "0001100" => + OP_CAT <= MOVE_SPi_LS; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SM; + D_SA <= ADR_SPi; + PC_OP <= pc(IS_M1, PC_WAIT); + D_WE_SP <= sp(IS_M1, SP_INC); + D_WE_LL <= IS_M2; + + when "0001101" => + OP_CAT <= MOVE_SPi_LU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_SPi; + PC_OP <= pc(IS_M1, PC_WAIT); + D_WE_SP <= sp(IS_M1, SP_INC); + D_WE_LL <= IS_M2; + + when "0001110" => + OP_CAT <= MOVE_RR_dSP; + LAST <= M2; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_SA <= ADR_dSP; + PC_OP <= pc(IS_M1, PC_WAIT); + D_WE_SP <= sp(IS_M1_M2, SP_LOAD); + D_SMQ <= IS_M1; + D_WE_M <= IS_M1_M2; + + when "0001111" => + OP_CAT <= MOVE_R_dSP; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_SA <= ADR_dSP; + D_WE_SP <= SP_LOAD; + D_WE_M <= '1'; + + -- 11111111111111111111111111111111111111111111111111111111111111111111 + when "0010000" => + OP_CAT <= AND_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_AND_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0010001" => + OP_CAT <= AND_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_AND_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0010010" => + OP_CAT <= OR_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0010011" => + OP_CAT <= OR_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0010100" => + OP_CAT <= XOR_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_XOR_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0010101" => + OP_CAT <= XOR_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_XOR_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0010110" => + OP_CAT <= SEQ_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0010111" => + OP_CAT <= SEQ_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0011000" => + OP_CAT <= SNE_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_NE_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0011001" => + OP_CAT <= SNE_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_NE_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0011010" => + OP_CAT <= SGE_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_GE_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0011011" => + OP_CAT <= SGE_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_GE_Y; + D_SX <= SX_RR; + D_SY <= SY_SI8; + D_WE_RR <= IS_M1; + + when "0011100" => + OP_CAT <= SGT_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_GT_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0011101" => + OP_CAT <= SGT_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_GT_Y; + D_SX <= SX_RR; + D_SY <= SY_SI8; + D_WE_RR <= IS_M1; + + when "0011110" => + OP_CAT <= SLE_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_LE_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0011111" => + OP_CAT <= SLE_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_LE_Y; + D_SX <= SX_RR; + D_SY <= SY_SI8; + D_WE_RR <= IS_M1; + + -- 22222222222222222222222222222222222222222222222222222222222222222222 + when "0100000" => + OP_CAT <= SLT_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_LT_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0100001" => + OP_CAT <= SLT_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_LT_Y; + D_SX <= SX_RR; + D_SY <= SY_SI8; + D_WE_RR <= IS_M1; + + when "0100010" => + OP_CAT <= SHS_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_HS_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0100011" => + OP_CAT <= SHS_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_HS_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0100100" => + OP_CAT <= SHI_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_HI_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0100101" => + OP_CAT <= SHI_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_HI_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0100110" => + OP_CAT <= SLS_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_LS_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0100111" => + OP_CAT <= SLS_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_LS_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0101000" => + OP_CAT <= SLO_RR_i; + LAST <= M3; -- wait for ## + D_OP <= ALU_X_LO_Y; + D_SX <= SX_RR; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "0101001" => + OP_CAT <= SLO_RR_i; + LAST <= M2; -- wait for # + D_OP <= ALU_X_LO_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "0101010" => + OP_CAT <= ADD_SP_I; + LAST <= M3; -- wait for ## + D_OP <= ALU_ANY; + D_SX <= SX_ANY; + D_SY <= SY_ANY; + D_SA <= ADR_16SP_L; + D_WE_SP <= sp(IS_M2, SP_LOAD); + + when "0101011" => + OP_CAT <= ADD_SP_I; + LAST <= M2; -- wait for # + D_OP <= ALU_ANY; + D_SX <= SX_ANY; + D_SY <= SY_ANY; + D_SA <= ADR_8SP_L; + D_WE_SP <= sp(IS_M1, SP_LOAD); + + when "0101100" => + OP_CAT <= CLRW_dSP; + LAST <= M2; + D_OP <= ALU_X_AND_Y; + D_SX <= SX_ANY; + D_SY <= SY_SY0; + D_SA <= ADR_dSP; + D_WE_SP <= SP_LOAD; + D_WE_M <= '1'; + PC_OP <= pc(IS_M1, PC_WAIT); + + when "0101101" => + OP_CAT <= CLRB_dSP; + D_OP <= ALU_X_AND_Y; + D_SX <= SX_ANY; + D_SY <= SY_SY0; + D_SA <= ADR_dSP; + D_WE_SP <= SP_LOAD; + D_WE_M <= IS_M1; + + when "0101110" => + OP_CAT <= IN_ci_RU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_IO; + D_SA <= ADR_IO; + IO_RD <= IS_M2; + D_WE_RR <= IS_M2; + + when "0101111" => + OP_CAT <= OUT_R_ci; + LAST <= M2; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_SA <= ADR_IO; + IO_WR <= IS_M2; + + -- 33333333333333333333333333333333333333333333333333333333333333333333 + when "0110000" => + OP_CAT <= AND_LL_RR; + D_OP <= ALU_X_AND_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110001" => + OP_CAT <= OR_LL_RR; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110010" => + OP_CAT <= XOR_LL_RR; + D_OP <= ALU_X_XOR_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110011" => + OP_CAT <= SEQ_LL_RR; + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110100" => + OP_CAT <= SNE_LL_RR; + D_OP <= ALU_X_NE_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110101" => + OP_CAT <= SGE_LL_RR; + D_OP <= ALU_X_GE_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110110" => + OP_CAT <= SGT_LL_RR; + D_OP <= ALU_X_GT_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0110111" => + OP_CAT <= SLE_LL_RR; + D_OP <= ALU_X_LE_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111000" => + OP_CAT <= SLT_LL_RR; + D_OP <= ALU_X_LT_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111001" => + OP_CAT <= SHS_LL_RR; + D_OP <= ALU_X_HS_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111010" => + OP_CAT <= SHI_LL_RR; + D_OP <= ALU_X_HI_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111011" => + OP_CAT <= SLS_LL_RR; + D_OP <= ALU_X_LS_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111100" => + OP_CAT <= SLO_LL_RR; + D_OP <= ALU_X_LO_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111101" => + OP_CAT <= LNOT_RR; + D_OP <= ALU_X_EQ_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_WE_RR <= IS_M1; + + when "0111110" => + OP_CAT <= NEG_RR; + D_OP <= ALU_NEG_Y; + D_SX <= SX_ANY; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "0111111" => + OP_CAT <= NOT_RR; + D_OP <= ALU_NOT_Y; + D_SX <= SX_ANY; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + -- 44444444444444444444444444444444444444444444444444444444444444444444 + when "1000000" => + OP_CAT <= MOVE_LL_RR; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_LL; + D_SY <= SY_SY0; + D_WE_RR <= IS_M1; + + when "1000001" => + OP_CAT <= MOVE_LL_cRR; + LAST <= M2; + PC_OP <= pc(IS_M1, PC_WAIT); + D_OP <= ALU_X_OR_Y; + D_SX <= SX_LL; + D_SY <= SY_SY0; + D_SA <= hadr(IS_M2, ADR_cRR_H); + D_SMQ <= IS_M2; + D_WE_M <= IS_M1_M2; + + when "1000010" => + OP_CAT <= MOVE_L_cRR; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_LL; + D_SY <= SY_SY0; + D_SA <= ADR_cRR_L; + D_WE_M <= IS_M1; + + when "1000011" => + OP_CAT <= MOVE_RR_LL; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_WE_LL <= IS_M1; + + when "1000100" => + OP_CAT <= MOVE_RR_cLL; + LAST <= M2; + PC_OP <= pc(IS_M1, PC_WAIT); + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_SA <= hadr(IS_M2, ADR_cLL_H); + D_SMQ <= IS_M2; + D_WE_M <= IS_M1_M2; + + when "1000101" => + OP_CAT <= MOVE_R_cLL; + D_OP <= ALU_X_OR_Y; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_SA <= ADR_cLL_L; + D_WE_M <= IS_M1; + + when "1000110" => + OP_CAT <= MOVE_cRR_RR; + LAST <= M3; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_WE_RR <= not IS_M1; -- M2 or M3 + PC_OP <= pc(IS_M1_M2, PC_WAIT); + D_OP <= mix(IS_M3); + D_SA <= hadr(IS_M2, ADR_cRR_H); + + when "1000111" => + OP_CAT <= MOVE_cRR_RS; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SM; + D_SA <= ADR_cRR_L; + D_WE_RR <= IS_M2; + PC_OP <= pc(IS_M1, PC_WAIT); + + when "1001000" => + OP_CAT <= MOVE_cRR_RU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_cRR_L; + D_WE_RR <= IS_M2; + PC_OP <= pc(IS_M1, PC_WAIT); + + when "1001001" => + OP_CAT <= MOVE_ci_RR; + LAST <= M4; + D_SX <= SX_RR; + D_SY <= SY_UM; + PC_OP <= pc(IS_M3, PC_WAIT); + D_OP <= mix(IS_M4); + D_WE_RR <= IS_M3_M4; + D_SA <= hadr(IS_M3, ADR_cI16_H); + + when "1001010" => + OP_CAT <= MOVE_ci_RS; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SM; + D_SA <= ADR_cI16_L; + D_WE_RR <= IS_M3; + + when "1001011" => + OP_CAT <= MOVE_ci_RU; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_cI16_L; + D_WE_RR <= IS_M3; + + when "1001100" => + OP_CAT <= MOVE_ci_LL; + LAST <= M4; + D_SX <= SX_LL; + D_SY <= SY_UM; + PC_OP <= pc(IS_M3, PC_WAIT); + D_OP <= mix(IS_M4); + D_SA <= hadr(IS_M3, ADR_cI16_H); + D_WE_LL <= IS_M3_M4; + + when "1001101" => + OP_CAT <= MOVE_ci_LS; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_SM; + D_SA <= ADR_cI16_L; + D_WE_LL <= IS_M3; + + when "1001110" => + OP_CAT <= MOVE_ci_LU; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_cI16_L; + D_WE_LL <= IS_M3; + + when "1001111" => + OP_CAT <= MOVE_RR_SP; + D_SA <= ADR_cRR_L; + D_WE_SP <= SP_LOAD; + + -- 55555555555555555555555555555555555555555555555555555555555555555555 + when "1010000" => + -- spare + + when "1010001" => + -- spare + + when "1010010" => + OP_CAT <= LSL_RR_i; + LAST <= M2; + D_OP <= ALU_X_LSL_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "1010011" => + OP_CAT <= ASR_RR_i; + LAST <= M2; + D_OP <= ALU_X_ASR_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "1010100" => + OP_CAT <= LSR_RR_i; + LAST <= M2; + D_OP <= ALU_X_LSR_Y; + D_SX <= SX_RR; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "1010101" => + OP_CAT <= LSL_LL_RR; + D_OP <= ALU_X_LSL_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1010110" => + OP_CAT <= ASR_LL_RR; + D_OP <= ALU_X_ASR_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1010111" => + OP_CAT <= LSR_LL_RR; + D_OP <= ALU_X_LSR_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1011000" => + OP_CAT <= ADD_LL_RR; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1011001" => + OP_CAT <= SUB_LL_RR; + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1011010" => + OP_CAT <= MOVE_RR_ci; + LAST <= M3; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= not IS_M1; -- M2 or M3 + D_SA <= hadr(IS_M3, ADR_cI16_H); + D_SMQ <= IS_M3; + + when "1011011" => + OP_CAT <= MOVE_R_ci; + LAST <= M3; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= IS_M2; + D_SA <= ADR_cI16_L; + + when "1011100" => -- long offset / long move + OP_CAT <= MOVE_RR_uSP; + LAST <= M3; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= not IS_M1; + D_SMQ <= IS_M3; + D_SA <= hadr(IS_M3, ADR_16SP_H); + + when "1011101" => -- short offset / long move + OP_CAT <= MOVE_RR_uSP; + LAST <= M2; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= IS_M1_M2; + D_SMQ <= IS_M2; + D_SA <= hadr(IS_M2, ADR_8SP_H); + + when "1011110" => -- long offset / short move + OP_CAT <= MOVE_R_uSP; + LAST <= M3; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= IS_M2; + D_OP <= ALU_X_OR_Y; + D_SA <= ADR_16SP_L; + + when "1011111" => -- short offset / short move + OP_CAT <= MOVE_R_uSP; + LAST <= M2; + D_SX <= SX_RR; + D_SY <= SY_SY0; + D_OP <= ALU_X_OR_Y; + D_WE_M <= IS_M1; + D_OP <= ALU_X_OR_Y; + D_SA <= ADR_8SP_L; + + -- 66666666666666666666666666666666666666666666666666666666666666666666 + when "1100000" => -- long offset, long move + OP_CAT <= MOVE_uSP_RR; + LAST <= M4; + D_SX <= SX_RR; + D_SY <= SY_UM; + PC_OP <= pc(IS_M3, PC_WAIT); + D_OP <= mix(IS_M3_M4); + D_WE_RR <= IS_M3_M4; + D_SA <= hadr(IS_M3, ADR_16SP_H); + + when "1100001" => -- short offset, long move + OP_CAT <= MOVE_uSP_RR; + LAST <= M3; + D_SX <= SX_RR; + D_SY <= SY_UM; + PC_OP <= pc(IS_M2, PC_WAIT); + D_OP <= mix(IS_M3); + D_WE_RR <= IS_M2_M3; + D_SA <= hadr(IS_M2, ADR_8SP_H); + + when "1100010" => -- long offset, short move + OP_CAT <= MOVE_uSP_RS; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_SM; + D_SA <= ADR_16SP_L; + D_WE_RR <= IS_M3; + + when "1100011" => -- short offset, short move + OP_CAT <= MOVE_uSP_RS; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_SM; + D_SA <= ADR_8SP_L; + D_WE_RR <= IS_M2; + + when "1100100" => -- long offset, short move + OP_CAT <= MOVE_uSP_RU; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_UM; + D_SA <= ADR_16SP_L; + D_WE_RR <= IS_M3; + + when "1100101" => -- short offset, short move + OP_CAT <= MOVE_uSP_RU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_UM; + D_SA <= ADR_8SP_L; + D_WE_RR <= IS_M2; + + when "1100110" => -- long offset, long move + OP_CAT <= MOVE_uSP_LL; + LAST <= M4; + D_SX <= SX_LL; + D_SY <= SY_UM; + PC_OP <= pc(IS_M3, PC_WAIT); + D_OP <= mix(IS_M4); + D_WE_LL <= IS_M3_M4; + D_SA <= hadr(IS_M3, ADR_8SP_H); + + when "1100111" => -- short offset, long move + OP_CAT <= MOVE_uSP_LL; + LAST <= M3; + D_SX <= SX_LL; + D_SY <= SY_UM; + PC_OP <= pc(IS_M2, PC_WAIT); + D_OP <= mix(IS_M3); + D_WE_LL <= IS_M2_M3; + D_SA <= hadr(IS_M2, ADR_8SP_H); + + when "1101000" => -- long offset, short move + OP_CAT <= MOVE_uSP_LS; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_SM; + D_SA <= ADR_16SP_L; + D_WE_LL <= IS_M3; + + when "1101001" => -- short offset, short move + OP_CAT <= MOVE_uSP_LS; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_SM; + D_SA <= ADR_8SP_L; + D_WE_LL <= IS_M2; + + when "1101010" => -- long offset, short move + OP_CAT <= MOVE_uSP_LU; + LAST <= M3; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_UM; + D_SA <= ADR_16SP_L; + D_WE_LL <= IS_M3; + + when "1101011" => -- short offset, short move + OP_CAT <= MOVE_uSP_LU; + LAST <= M2; + D_OP <= ALU_MOVE_Y; + D_SX <= SX_RR; + D_SY <= SY_UM; + D_SA <= ADR_8SP_L; + D_WE_LL <= IS_M2; + + when "1101100" => + OP_CAT <= LEA_uSP_RR; + LAST <= M3; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_SP; + D_SY <= SY_I16; + D_WE_RR <= IS_M2; + + when "1101101" => + OP_CAT <= LEA_uSP_RR; + LAST <= M2; + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_SP; + D_SY <= SY_UI8; + D_WE_RR <= IS_M1; + + when "1101110" => + OP_CAT <= MOVE_dRR_dLL; + LAST <= M3; + D_WE_RR <= IS_M1; + D_WE_M <= IS_M2; + D_WE_LL <= IS_M3; + PC_OP <= pc(IS_M1_M2, PC_WAIT); + + case OP_CYC is + when M1 => -- decrement RR + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_RR; + D_SY <= SY_SY1; + D_SA <= ADR_dRR; + when M2 => -- write read memory + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_dLL; + when others => -- decrement LL + D_OP <= ALU_X_SUB_Y; + D_SX <= SX_LL; + D_SY <= SY_SY1; + end case; + + when "1101111" => + OP_CAT <= MOVE_RRi_LLi; + LAST <= M3; + D_WE_RR <= IS_M1; + D_WE_M <= IS_M2; + D_WE_LL <= IS_M3; + PC_OP <= pc(IS_M1_M2, PC_WAIT); + + case OP_CYC is + when M1 => -- decrement RR + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_RR; + D_SY <= SY_SY1; + D_SA <= ADR_RRi; + when M2 => -- write read memory + D_OP <= ALU_MOVE_Y; + D_SX <= SX_ANY; + D_SY <= SY_UM; + D_SA <= ADR_dLL; + when others => -- decrement LL + D_OP <= ALU_X_ADD_Y; + D_SX <= SX_LL; + D_SY <= SY_SY1; + end case; + + -- 77777777777777777777777777777777777777777777777777777777777777777777 + when "1110000" => + OP_CAT <= MUL_IS; + D_OP <= ALU_MUL_IS; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110001" => + OP_CAT <= MUL_IU; + D_OP <= ALU_MUL_IU; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110010" => + OP_CAT <= DIV_IS; + D_OP <= ALU_DIV_IS; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110011" => + OP_CAT <= DIV_IU; + D_OP <= ALU_DIV_IU; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110100" => + OP_CAT <= MD_STEP; + D_OP <= ALU_MD_STP; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110101" => + OP_CAT <= MD_FIN; + D_OP <= ALU_MD_FIN; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110110" => + OP_CAT <= MOD_FIN; + D_OP <= ALU_MOD_FIN; + D_SX <= SX_LL; + D_SY <= SY_RR; + D_WE_RR <= IS_M1; + + when "1110111" => + OP_CAT <= EI; + ENABLE_INT <= '1'; + + when "1111001" => + OP_CAT <= DI; + DISABLE_INT <= '1'; + + -- undefined -------------------------------------------------------- + when others => + end case; + end if; + end process; + +end Behavioral; Index: Board_cpu.vhd =================================================================== --- Board_cpu.vhd (nonexistent) +++ Board_cpu.vhd (revision 26) @@ -0,0 +1,126 @@ +-- +-- This is the top level VHDL file. +-- +-- It iobufs for bidirational signals (towards an optional +-- external fast SRAM. +-- +-- Pins fit the AVNET Virtex-E Evaluation board +-- +-- For other boards, change pin assignments in this file. +-- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.all; + +use work.cpu_pack.ALL; + +library UNISIM; +use UNISIM.VComponents.all; + +entity board_cpu is + PORT ( CLK40 : in STD_LOGIC; + SWITCH : in STD_LOGIC_VECTOR (9 downto 0); + + SER_IN : in STD_LOGIC; + SER_OUT : out STD_LOGIC; + + TEMP_SPO : in STD_LOGIC; + TEMP_SPI : out STD_LOGIC; + + CLK_OUT : out STD_LOGIC; + LED : out STD_LOGIC_VECTOR (7 downto 0); + ENABLE_N : out STD_LOGIC; + DEACTIVATE_N : out STD_LOGIC; + TEMP_CE : out STD_LOGIC; + TEMP_SCLK : out STD_LOGIC; + SEG1 : out STD_LOGIC_VECTOR (7 downto 0); + SEG2 : out STD_LOGIC_VECTOR (7 downto 0); + + XM_ADR : out STD_LOGIC_VECTOR(14 downto 0); + XM_CE_N : out STD_LOGIC; + XM_OE_N : out STD_LOGIC; + XM_WE_N : inout STD_LOGIC; + XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0) + ); +end board_cpu; + +architecture behavioral of board_cpu is + + COMPONENT cpu16 + PORT( CLK_I : in STD_LOGIC; + T2 : out STD_LOGIC; + SWITCH : in STD_LOGIC_VECTOR (9 downto 0); + + SER_IN : in STD_LOGIC; + SER_OUT : out STD_LOGIC; + + TEMP_SPO : in STD_LOGIC; + TEMP_SPI : out STD_LOGIC; + TEMP_CE : out STD_LOGIC; + TEMP_SCLK : out STD_LOGIC; + + SEG1 : out STD_LOGIC_VECTOR (7 downto 0); + SEG2 : out STD_LOGIC_VECTOR( 7 downto 0); + LED : out STD_LOGIC_VECTOR( 7 downto 0); + + XM_ADR : out STD_LOGIC_VECTOR(15 downto 0); + XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0); + XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0); + XM_WE : out STD_LOGIC; + XM_CE : out STD_LOGIC + ); + END COMPONENT; + + signal XM_WDAT : std_logic_vector( 7 downto 0); + signal XM_RDAT : std_logic_vector( 7 downto 0); + signal MEM_T : std_logic; + signal XM_WE : std_logic; + signal WE_N : std_logic; + signal DEL_WE_N : std_logic; + signal XM_CE : std_logic; + +begin + + cp: cpu16 + PORT MAP( CLK_I => CLK40, + T2 => CLK_OUT, + SWITCH => SWITCH, + + SER_IN => SER_IN, + SER_OUT => SER_OUT, + + TEMP_SPO => TEMP_SPO, + TEMP_SPI => TEMP_SPI, + + XM_ADR(14 downto 0) => XM_ADR, + XM_ADR(15) => open, + XM_RDAT => XM_RDAT, + XM_WDAT => XM_WDAT, + XM_WE => XM_WE, + XM_CE => XM_CE, + TEMP_CE => TEMP_CE, + TEMP_SCLK => TEMP_SCLK, + SEG1 => SEG1, + SEG2 => SEG2, + LED => LED + ); + + ENABLE_N <= '0'; + DEACTIVATE_N <= '1'; + + MEM_T <= DEL_WE_N; -- active low + WE_N <= not XM_WE; + XM_OE_N <= XM_WE; + XM_CE_N <= not XM_CE; + + p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7)); + p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0)); + p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6)); + p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1)); + p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5)); + p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2)); + p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4)); + p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3)); + p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N); + +end behavioral;

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