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URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

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  • This comparison shows the changes necessary to convert path
    /can/tags/rel_22/syn
    from Rev 146 to Rev 161
    Reverse comparison

Rev 146 → Rev 161

/synplicity/can.prj
0,0 → 1,100
#-- Synplicity, Inc.
#-- Version 7.2.2
#-- Project file X:\zoidberg_soc\zoidberg_soc\can\syn\synplicity\can.prj
#-- Written on Tue Sep 23 14:15:42 2003
 
 
#add_file options
add_file -verilog "$LIB/proasic/proasicplus.v"
add_file -verilog "../../../memory/actel/ram_64x8_sync/actel_ram_64x8_sync.v"
add_file -verilog "../../../memory/actel/ram_64x4_sync/actel_ram_64x4_sync.v"
add_file -verilog "../../../memory/actel/ram_64x1_sync/actel_ram_64x1_sync.v"
add_file -verilog "../../rtl/verilog/can_registers.v"
add_file -verilog "../../rtl/verilog/can_bsp.v"
add_file -verilog "../../rtl/verilog/can_btl.v"
add_file -verilog "../../rtl/verilog/can_defines.v"
add_file -verilog "../../rtl/verilog/can_register.v"
add_file -verilog "../../rtl/verilog/can_register_asyn.v"
add_file -verilog "../../rtl/verilog/can_register_asyn_syn.v"
add_file -verilog "../../rtl/verilog/can_register_syn.v"
add_file -verilog "../../rtl/verilog/can_top.v"
add_file -verilog "../../rtl/verilog/can_fifo.v"
add_file -verilog "../../rtl/verilog/can_acf.v"
add_file -verilog "../../rtl/verilog/can_crc.v"
add_file -verilog "../../rtl/verilog/can_ibo.v"
 
 
#implementation: "rev_1"
impl -add rev_1
 
#device options
set_option -technology PA
set_option -part APA150
set_option -speed_grade Std
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "can_top"
 
#map options
set_option -frequency 50.000
set_option -fanout_limit 12
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -report_path 4000
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "rev_1/can_top.edn"
 
#implementation attributes
set_option -compiler_compatible 0
set_option -include_path "../../rtl/verilog/;../../bench/verilog/"
 
 
#implementation: "rev_2"
impl -add rev_2
 
#device options
set_option -technology PA
set_option -part APA600
set_option -speed_grade Std
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -top_module "can_top"
 
#map options
set_option -frequency 50.000
set_option -fanout_limit 12
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -report_path 4000
 
#simulation options
set_option -write_verilog 1
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "rev_2/can_top.edn"
 
#implementation attributes
set_option -vlog_std v95
set_option -compiler_compatible 0
set_option -num_critical_paths ""
set_option -num_startend_points ""
set_option -include_path "../../rtl/verilog/;../../bench/verilog/"
impl -active "rev_2"
synplicity/can.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: synplicity/rev_1/dir_keeper =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: synplicity/rev_1/dir_keeper =================================================================== --- synplicity/rev_1/dir_keeper (nonexistent) +++ synplicity/rev_1/dir_keeper (revision 161)
synplicity/rev_1/dir_keeper Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: libero/pinedit.gcf =================================================================== --- libero/pinedit.gcf (nonexistent) +++ libero/pinedit.gcf (revision 161) @@ -0,0 +1,5 @@ +set_io "H5" "clkout_o"; +set_io "M2" "tx_o"; +set_io "J1" "wb_rst_i"; +set_io "M3" "rx_i"; +set_io "H1" "clk_i";

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