Subversion Repositories cic_core

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/doc/cic_ug.pdf

doc/cic_ug.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sim/cic_i_tb_run.tcl =================================================================== --- sim/cic_i_tb_run.tcl (nonexistent) +++ sim/cic_i_tb_run.tcl (revision 3) @@ -0,0 +1,17 @@ +onerror {resume} +set tb_name cic_i_tb +quit -sim +vlog -sv -work work cic_core/trunk/src/cic_package.sv +vlog -sv -work work cic_core/trunk/src/*.sv +vlog -sv -work work cic_core/trunk/sim/$tb_name.sv +vsim -t 1ns -novopt work.$tb_name +add wave /$tb_name/* +add wave {/cic_i_tb/dut1/int_stage[0]/*} +add wave {/cic_i_tb/dut1/int_stage[1]/*} +add wave {/cic_i_tb/dut1/int_stage[2]/*} +add wave {/cic_i_tb/dut1/int_stage[3]/*} +add wave {/cic_i_tb/dut1/comb_stage[0]/*} +add wave {/cic_i_tb/dut1/comb_stage[1]/*} +add wave {/cic_i_tb/dut1/comb_stage[2]/*} +add wave {/cic_i_tb/dut1/comb_stage[3]/*} +run 1 us Index: sim/cic_i_tb.sv =================================================================== --- sim/cic_i_tb.sv (nonexistent) +++ sim/cic_i_tb.sv (revision 3) @@ -0,0 +1,56 @@ +`timescale 1ns / 1ns +/*********************************************************************************************/ +module cic_i_tb(); +/*********************************************************************************************/ +//TB example: impulse responce +/*********************************************************************************************/ +localparam dw = 10; +localparam m = 4; +localparam r = 4; +localparam g = 1; +/*********************************************************************************************/ +reg clk; +reg reset_n; +reg signed [dw-1:0] data_in; +wire in_dv; +reg [$clog2(r)-1:0] counter; +wire signed [dw+$clog2((r**(m))/r)-1:0] data_out; +/*********************************************************************************************/ +initial begin : clk_gen + clk <= 1'b0; + #5 forever #5 clk <= ~clk; +end +/*********************************************************************************************/ +initial begin : reset_gen + $display($time, " << Starting the Simulation >>"); + reset_n = 1'b0; + data_in = '0; + repeat (2) @(negedge clk); + $display($time, " << Coming out of reset >>"); + reset_n = 1'b1; + repeat(3) @(posedge clk); + data_in = 2**(dw-1)-1; + @(posedge clk); + data_in = '0; +end +/*********************************************************************************************/ +assign in_dv = &counter; +/*********************************************************************************************/ +always @(posedge clk) +begin + if (!reset_n) + counter = '0; + else + counter++; +end +/*********************************************************************************************/ +cic_i #(dw, r, m, g) dut1 +( + .clk(clk), + .reset_n(reset_n), + .data_in(data_in), + .in_dv(in_dv), + .data_out(data_out) +); +/*********************************************************************************************/ +endmodule Index: sim/cic_d_tb_run.tcl =================================================================== --- sim/cic_d_tb_run.tcl (nonexistent) +++ sim/cic_d_tb_run.tcl (revision 3) @@ -0,0 +1,18 @@ +onerror {resume} +set tb_name cic_d_tb +quit -sim +vlog -sv -work work cic_core/trunk/src/cic_package.sv +vlog -sv -work work cic_core/trunk/src/*.sv +vlog -sv -work work cic_core/trunk/sim/$tb_name.sv +vsim -t 1ns -novopt work.$tb_name +add wave /$tb_name/* +add wave {/cic_d_tb/dut1/int_stage[0]/*} +add wave {/cic_d_tb/dut1/int_stage[1]/*} +add wave {/cic_d_tb/dut1/int_stage[2]/*} +add wave {/cic_d_tb/dut1/int_stage[3]/*} +add wave /$tb_name/dut1/u1/* +add wave {/cic_d_tb/dut1/comb_stage[0]/*} +add wave {/cic_d_tb/dut1/comb_stage[1]/*} +add wave {/cic_d_tb/dut1/comb_stage[2]/*} +add wave {/cic_d_tb/dut1/comb_stage[3]/*} +run 100 us Index: sim/cic_d_tb.sv =================================================================== --- sim/cic_d_tb.sv (nonexistent) +++ sim/cic_d_tb.sv (revision 3) @@ -0,0 +1,62 @@ +`timescale 1ns / 1ns +package cmath; + import "DPI-C" function real sin(input real x); +endpackage +module cic_d_tb +( +); +localparam R = 25; +localparam idw = 16; +localparam odw = 16; +localparam M = 4; +localparam G = 1; +/*************************************************************/ +localparam real Fs = 100;//MHz +localparam real T_ns = 10**3/Fs;//ns +localparam time half_T = T_ns/2; +localparam real f = 0.5;//MHz +localparam real f_inc = f/Fs; +localparam bias = 5; +real f_n = 0.0; +/*************************************************************/ +reg clk; +reg reset_n; +reg signed[idw-1:0] filter_in; +wire filter_valid; +wire signed[odw-1:0] filter_out; +/*************************************************************/ +import cmath::*; +/*************************************************************/ +initial begin : clk_gen + clk <= 1'b0; + #half_T forever #half_T clk = ~clk; +end +/*************************************************************/ +initial begin : reset_gen + $display($time, " << Starting the Simulation >>"); + reset_n = 1'b0; + repeat (2) @(negedge clk); + $display($time, " << Coming out of reset >>"); + reset_n = 1'b1; + repeat (20) @(posedge clk); + @(posedge clk); +end +/*************************************************************/ +always @(posedge clk) +begin + f_n = f_n + f_inc; +end +/*************************************************************/ +assign filter_in = $rtoi((2**(idw-1)-1)*($sin(f_n))); +/*************************************************************/ +cic_d #(idw,odw,R,M,G) dut1 +( + .clk(clk), + .reset_n(reset_n), + .data_in(filter_in), + .data_out(filter_out), + .out_dv(filter_valid) +); +/*************************************************************/ +endmodule +