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URL https://opencores.org/ocsvn/cic_core/cic_core/trunk

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Rev 1 → Rev 2

/trunk/cic_package.sv
0,0 → 1,94
package cic_package;
/*********************************************************************************************/
function longint nchoosek;
input longint n;
input longint k;
longint tmp;
longint i;
begin
tmp = 1.0;
for (i=1;i<=(n-k);i++)
tmp = tmp*(k+i)/i;
nchoosek = tmp;
end
endfunction
/*********************************************************************************************/
function longint clog2_l;
input longint depth;
longint i;
begin
i = depth;
for(clog2_l = 0; i > 0; clog2_l = clog2_l + 1)
i = i >> 1;
end
endfunction
/*********************************************************************************************/
function longint h;
input longint j;
input longint k;
input longint R;
input longint M;
input longint N;
longint c_stop;
longint i;
longint tmp;
begin
c_stop = k/(R*M);
if ((j>=1)&&(j<=N)) begin
tmp=0.0;
for (i=0;i<=c_stop;i++) begin
if (i%2)
tmp = tmp - nchoosek(N,i)*nchoosek(N-j+k-R*M*i,k-R*M*i);
else
tmp = tmp + nchoosek(N,i)*nchoosek(N-j+k-R*M*i,k-R*M*i);
end
end
else begin
tmp = nchoosek(2*N+1-j,k);
if (k%2)
tmp = -tmp;
end
h = tmp;
end
endfunction
/*********************************************************************************************/
function longint F;
input longint j;
input longint R;
input longint G;
input longint M;
longint c_stop;
longint tmp;
longint i;
begin
tmp = 0.0;
if (j<=M)
c_stop=(((R*G-1)*M)+j-1);
else
c_stop=2*M+1-j;
for (i=0;i<=c_stop;i++) begin
tmp = tmp + h(j,i,R,G,M)*h(j,i,R,G,M);
end
F = tmp;
end
endfunction
/*********************************************************************************************/
function integer B;
input longint j;
input longint R;
input longint G;
input longint M;
input longint dw_in;
input longint dw_out;
longint B_max;
longint sigma_T;
longint tmp;
begin
B_max = $clog2((R*G)**M)+dw_in-1;
sigma_T = (2**(2*(B_max-dw_out+1)))/12;
tmp = (6*sigma_T)/(M*F(j,R,G,M));
B = (clog2_l(tmp)-1)/2;
end
endfunction
/*********************************************************************************************/
endpackage
/trunk/downsampler.sv
0,0 → 1,29
module downsampler
/*********************************************************************************************/
#(parameter dw = 8, r = 4)
/*********************************************************************************************/
(
input clk,
input reset_n,
input [dw-1:0] data_in,
output reg [dw-1:0] data_out,
output reg dv
);
/*********************************************************************************************/
reg [$clog2(r)-1:0] counter;
/*********************************************************************************************/
always_ff @(posedge clk)
begin
if (!reset_n) begin
counter <= '0;
data_out <= '0;
dv <= 1'b0;
end
else begin
counter <= (counter < r-1) ? counter + 1 : '0;
dv <= (counter == r-1);
data_out <= (counter == r-1) ? data_in : data_out;
end
end
/*********************************************************************************************/
endmodule
/trunk/integrator.sv
0,0 → 1,20
module integrator
/*********************************************************************************************/
#(parameter idw = 8 , odw = 9)
/*********************************************************************************************/
(
input clk,
input reset_n,
input signed [idw-1:0] data_in,
output reg signed [odw-1:0] data_out
);
/*********************************************************************************************/
always_ff @(posedge clk)
begin
if (!reset_n)
data_out <= '0;
else
data_out <= data_out + data_in;
end
/*********************************************************************************************/
endmodule
/trunk/comb.sv
0,0 → 1,31
module comb
/*********************************************************************************************/
#(parameter idw = 8, odw = 9, g = 1)
/*********************************************************************************************/
(
input clk,
input reset_n,
input in_dv,
input signed [idw-1:0] data_in,
output reg signed [odw-1:0] data_out
);
/*********************************************************************************************/
reg signed [idw-1:0] data_reg[g];
integer i;
/*********************************************************************************************/
always_ff @(posedge clk)
begin
if (!reset_n) begin
for (i=0;i<g;i++)
data_reg[i] <= '0;
data_out <= '0;
end
else if (in_dv) begin
data_reg[0] <= data_in;
for (i=1;i<g;i++)
data_reg[i] <= data_reg[i-1];
data_out <= data_in - data_reg[g-1];
end
end
/*********************************************************************************************/
endmodule
/trunk/cic_d.sv
0,0 → 1,70
module cic_d
/*********************************************************************************************/
#(parameter idw = 8, odw = 8, r = 4, m = 4, g = 1)
/*********************************************************************************************/
//m - CIC order (comb chain length, integrator chain length)
//r - interpolation ratio
//idw - input data width
//odw - output data width
//g - differential delay in combs
/*********************************************************************************************/
(
input clk,
input reset_n,
input signed [idw-1:0] data_in,
output signed [odw-1:0] data_out,
output out_dv
);
/*********************************************************************************************/
localparam b_max = $clog2((r*g)**m)+idw;
/*********************************************************************************************/
genvar i;
generate
for (i = 0; i < m; i++) begin:int_stage
localparam idw_cur = b_max-cic_package::B(i+1,r,g,m,idw,odw)+1;
localparam odw_cur = idw_cur;
localparam odw_prev = (i!=0) ? b_max-cic_package::B(i,r,g,m,idw,odw)+1 : 0;
wire signed [idw_cur-1:0] int_in;
if (i!=0)
assign int_in = int_stage[i-1].int_out[odw_prev-1:odw_prev-idw_cur];
else
assign int_in = data_in;
wire signed [odw_cur-1:0] int_out;
integrator #(idw_cur, odw_cur) int_inst(.clk(clk) , .reset_n(reset_n) , .data_in(int_in) , .data_out(int_out));
end
endgenerate
/*********************************************************************************************/
localparam ds_dw = b_max-cic_package::B(m,r,g,m,idw,odw)+1;
wire signed [ds_dw-1:0] ds_out;
wire ds_dv;
/*********************************************************************************************/
downsampler #(ds_dw, r) u1
(
.clk(clk),
.reset_n(reset_n),
.data_in(int_stage[m-1].int_out),
.data_out(ds_out),
.dv(ds_dv)
);
/*********************************************************************************************/
genvar j;
generate
for (j = 0; j < m; j++) begin:comb_stage
localparam idw_cur = b_max-cic_package::B(m+j+1,r,g,m,idw,odw);
localparam odw_cur = idw_cur;
localparam odw_prev = (j!=0) ? b_max-cic_package::B(m+j,r,g,m,idw,odw) : 0;
wire signed [idw_cur-1:0] comb_in;
if (j!=0)
assign comb_in = comb_stage[j-1].comb_out[odw_prev-1:odw_prev-idw_cur];
else
assign comb_in = ds_out[ds_dw-1:ds_dw-idw_cur];
wire signed [odw_cur-1:0] comb_out;
comb #(idw_cur, odw_cur, g) comb_inst(.clk(clk) , .reset_n(reset_n) , .in_dv(ds_dv) , .data_in(comb_in) , .data_out(comb_out));
end
endgenerate
/*********************************************************************************************/
localparam dw_out = b_max-cic_package::B(2*m,r,g,m,idw,odw);
assign data_out = comb_stage[m-1].comb_out[dw_out-1:dw_out-odw];
assign out_dv = ds_dv;
/*********************************************************************************************/
endmodule
/trunk/cic_i.sv
0,0 → 1,53
module cic_i
/*********************************************************************************************/
#(parameter dw = 8, r = 4, m = 4, g = 1)
/*********************************************************************************************/
//m - CIC order (comb chain length, integrator chain length)
//r - interpolation ratio
//dw - input data width
//g - differential delay in combs
/*********************************************************************************************/
(
input clk,
input reset_n,
input in_dv,
input signed [dw-1:0] data_in,
output signed [dw+$clog2((r**(m))/r)-1:0] data_out
);
/*********************************************************************************************/
wire signed [dw+m-2:0] upsample;
/*********************************************************************************************/
genvar i;
generate
for (i = 0; i < m; i++) begin:comb_stage
wire signed [dw+i-1:0] comb_in;
localparam odw = (i == m - 1) ? dw+i : dw+i+1;
if (i!=0)
assign comb_in = comb_stage[i-1].comb_out;
else
assign comb_in = data_in;
wire signed [odw-1:0] comb_out;
comb #(dw+i, odw, g) comb_inst(.clk(clk) , .reset_n(reset_n) , .in_dv(in_dv) , .data_in(comb_in) , .data_out(comb_out));
end
endgenerate
/*********************************************************************************************/
assign upsample = (in_dv) ? comb_stage[m-1].comb_out : 0;
/*********************************************************************************************/
genvar j;
generate
for (j = 0; j < m; j++) begin:int_stage
localparam idw = (j == 0) ? dw+m-1 : dw+$clog2(((2**(m-j))*(r**(j)))/r);
localparam odw = dw+$clog2(((2**(m-j-1))*(r**(j+1)))/r);
wire signed [idw-1:0] int_in;
if (j==0)
assign int_in = upsample;
else
assign int_in = int_stage[j-1].int_out;
wire signed [odw-1:0] int_out;
integrator #(idw, odw) int_inst(.clk(clk) , .reset_n(reset_n) , .data_in(int_in) , .data_out(int_out));
end
endgenerate
/*********************************************************************************************/
assign data_out = int_stage[m-1].int_out;
/*********************************************************************************************/
endmodule

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