URL
https://opencores.org/ocsvn/connect-6/connect-6/trunk
Subversion Repositories connect-6
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- This comparison shows the changes necessary to convert path
/connect-6/trunk/BUILD_SCC/DE2
- from Rev 4 to Rev 7
- ↔ Reverse comparison
Rev 4 → Rev 7
/async_receiver_altera.v
3,8 → 3,8
output RxD_data_ready; // onc clock pulse when RxD_data is valid |
output [7:0] RxD_data; |
|
parameter ClkFrequency = 50000000; // 50MHz |
//parameter ClkFrequency = 27000000; // 27MHz |
//parameter ClkFrequency = 50000000; // 50MHz |
parameter ClkFrequency = 27000000; // 27MHz |
parameter Baud = 115200; |
|
// We also detect if a gap occurs in the received stream of characters |
/async_transmitter_altera.v
3,8 → 3,8
input [7:0] TxD_data; |
output TxD, TxD_busy; |
|
parameter ClkFrequency = 50000000; // 50MHz |
//parameter ClkFrequency = 27000000; // 27MHz |
//parameter ClkFrequency = 50000000; // 50MHz |
parameter ClkFrequency = 27000000; // 27MHz |
parameter Baud = 115200; |
|
// Baud generator |
/DE2.v
72,7 → 72,7
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wire mTXD_Done_not; |
RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not), |
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]), |
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_27),.RST_n(KEY[0]), |
.oTxD(UART_TXD),.iRxD(UART_RXD)); |
assign mTXD_Done = !mTXD_Done_not; |
assign LED_RED[9] = mTXD_Done_not; |
88,7 → 88,7
.iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready), |
.oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done), |
// Control |
.iCLK(OSC_50),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn), |
.iCLK(OSC_27),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn), |
//AI |
.oAI_DATA(DATA_to_AI), |
.iAI_DATA(DATA_from_AI), |
103,7 → 103,7
.oAI_Done(mAI_Done), |
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// Control |
.iCLK(OSC_50),.iRST_n(mAI_RSTn) ); |
.iCLK(OSC_27),.iRST_n(mAI_RSTn) ); |
wire [63:0] CMD_Tmp; |
|
//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16], |