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  • This comparison shows the changes necessary to convert path 
    /connect-6/trunk/BUILD_SCC/DE2
    from Rev 7 to Rev 8
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  •

Rev 7 → Rev 8

/constraints.sdc
1,5 → 1,5
# clocks
 
create_clock -period 20.0 -name clk [get_ports OSC_50]
create_clock -period 30.0 -name clk [get_ports OSC_27]
# input/output delays
 
/quartus.tcl
36,7 → 36,7
}
set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"
}
 
#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
#DE2 files
set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]
foreach mcs ${de2files} {
52,6 → 52,11
}
set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"
}
set_global_assignment -name VHDL_FILE "../../../../DE2/pll/pll.vhd"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_inst.vhd"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.cmp"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.ppf"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_syn.v"
 
# run the flow
#execute_flow -compile
/bram_based_stream_buffer.v
0,0 → 1,244
// Copyright (c) 2011 Synopsys, Inc. All rights reserved.
//
//
// $Revision: 1.8 $
 
 
`timescale 1ns / 1ps
 
`ifdef PICO_CLOCK_EDGE
`else
`define PICO_CLOCK_EDGE posedge
`endif
`ifdef PICO_CLOCK_SENSITIVITY
`else
`define PICO_CLOCK_SENSITIVITY clk
`endif
`ifdef PICO_RESET_SENSITIVITY
`else
`define PICO_RESET_SENSITIVITY
`endif
`ifdef PICO_RESET_SENSITIVITY2
`else
`define PICO_RESET_SENSITIVITY2 reset
`endif
 
`timescale 1 ns / 10 ps
 
module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready, reset, flush, load_req, store_req );
 
parameter width = 48;
parameter depth = 800;
parameter awidth = clogb2(depth);
 
input clk, load_ready, store_ready, reset, flush;
wire clk, load_ready, store_ready, reset, flush;
 
input [width-1:0] indata;
wire [width-1:0] indata;
 
output load_req, store_req;
wire load_req, store_req;
 
output [width-1:0] outdata;
wire [width-1:0] outdata;
 
 
function integer clogb2(input integer depth);
begin
for (clogb2=0; depth>0; clogb2=clogb2+1)
depth= depth>>1;
end
endfunction
 
// 0in assert -var (depth >= 1)
// coverage off
// pragma coverage off
// VCS coverage off
// synopsys translate_off
initial begin
if ( depth < 1 ) begin
$display ("ERROR::::");
$display ("mc_log: ERROR: bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);
$display ("END ERROR");
$finish;
end
end
// synopsys translate_on
// VCS coverage on
// pragma coverage on
// coverage on
 
reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;
reg [awidth-1:0] count_ff ;
reg full_ff, not_empty_ff, onefull_ff, init_ff;
 
reg [width-1:0] bypass_reg_ff;
reg bypass_reg_valid_ff;
 
wire [width-1:0] bram_outdata;
wire addq_only, shiftq_only, shiftq_addq, mem_is_empty;
 
wire addq = load_ready;
wire shiftq = store_ready;
 
wire full_mem = full_ff;
assign mem_is_empty = ~not_empty_ff;
 
assign addq_only = (addq & !full_ff & (!shiftq |(shiftq & mem_is_empty)));
assign shiftq_only = (shiftq & !mem_is_empty & (!addq | (addq & full_mem)) );
assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);
 
wire rreq, wreq;
 
assign rreq = not_empty_ff;
assign wreq = addq & !full_mem;
assign load_req = !full_mem;
assign store_req = !mem_is_empty;
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
not_empty_ff <= 1'b0;
full_ff <= 1'b0;
init_ff <= 1'b0;
end
else if (flush) begin
not_empty_ff <= 1'b0;
full_ff <= 1'b0;
init_ff <= 1'b0;
end
else begin
init_ff <= 1'b1;
if (addq & mem_is_empty) begin
not_empty_ff <= 1'b1;
end
else if (shiftq & !addq & onefull_ff) begin
not_empty_ff <= 1'b0;
end
if (addq_only & (count_ff == depth-1)) full_ff <= 1'b1;
else if (shiftq_only) full_ff <= 1'b0;
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
onefull_ff <= 1'b0;
end
else if (flush) begin
onefull_ff <= 1'b0;
end
else begin
if (addq_only) begin
if (mem_is_empty) begin
onefull_ff <= 1'b1;
end
else begin
onefull_ff <= 1'b0;
end
end
else if (shiftq_only) begin
if (onefull_ff) begin
onefull_ff <= 1'b0;
end
else if (count_ff == 2'b10) begin
onefull_ff <= 1'b1;
end
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
read_addr_ff <= {awidth{1'b0}};
next_read_addr_ff <= {awidth{1'b0}};
end
else if (flush) begin
read_addr_ff <= {awidth{1'b0}};
next_read_addr_ff <= {awidth{1'b0}};
end
else begin
if ( (shiftq & not_empty_ff) | ~init_ff ) begin
read_addr_ff <= next_read_addr_ff;
if (next_read_addr_ff == depth-1) begin
next_read_addr_ff <= {awidth{1'b0}};
end
else begin
next_read_addr_ff <= next_read_addr_ff + 1'b1;
end
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
write_addr_ff <= {awidth{1'b0}};
end
else if (flush) begin
write_addr_ff <= {awidth{1'b0}};
end
else begin
if (wreq) begin
if (write_addr_ff == depth-1)
write_addr_ff <= {awidth{1'b0}};
else
write_addr_ff <= write_addr_ff + 1'b1;
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
count_ff <= {awidth{1'b0}};
end
else if (flush) begin
count_ff <= {awidth{1'b0}};
end
else begin
if (addq_only) begin
count_ff <= count_ff + 1'b1;
end
else if (shiftq_only) begin
count_ff <= count_ff - 1'b1;
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
if (`PICO_RESET_SENSITIVITY2)
begin
bypass_reg_valid_ff <= 1'b0;
bypass_reg_ff <= {(width){1'b0}};
end
else if (flush)
begin
bypass_reg_valid_ff <= 1'b0;
end
else
begin
bypass_reg_valid_ff <= addq & ( mem_is_empty | (shiftq & onefull_ff) );
bypass_reg_ff <= indata;
end
end
assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];
 
wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;
 
RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(
.QA(),
.CLKA(clk),
.CENA(~wreq),
.WENA(1'b0),
.AA(write_addr_ff[awidth-1:0]),
.DA(indata[width-1:0]),
.QB(bram_outdata[width-1:0]),
.CLKB(clk),
.CENB(~rreq),
.WENB(1'b1),
.AB(speculative_read_addr),
.DB({width{1'b0}}));
 
 
endmodule
/async_receiver_altera.v
3,8 → 3,9
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
 
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 62500000; // 50MHz
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// We also detect if a gap occurs in the received stream of characters
/async_transmitter_altera.v
3,8 → 3,9
input [7:0] TxD_data;
output TxD, TxD_busy;
 
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 62500000; // 60MHz
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// Baud generator
/AI.vhd
20,6 → 20,20
 
 
architecture c_to_g of AI is
component bram_based_stream_buffer is
--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
port(
clk:in std_logic;
reset:in std_logic;
store_ready:in std_logic;
flush:in std_logic;
store_req:out std_logic;
load_req:out std_logic;
load_ready:in std_logic;
indata:in std_logic_vector(47 downto 0);
outdata:out std_logic_vector(47 downto 0)
);
end component bram_based_stream_buffer;
 
component connect6ai_synth_tcab is
port(
62,7 → 76,13
rawdataout_pico_connect6ai_synth_moveout_out_4_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_5_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_6_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0)
rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0);
instream_queue_di_0:in std_logic_vector(47 downto 0);
instream_queue_req_0:out std_logic;
instream_queue_ready_0:in std_logic;
outstream_queue_do_1:out std_logic_vector(47 downto 0);
outstream_queue_req_1:out std_logic;
outstream_queue_ready_1:in std_logic
 
);
end component connect6ai_synth_tcab;
69,6 → 89,12
signal out_enables:std_logic_vector(7 downto 0);
signal out_enables_reg:std_logic_vector(7 downto 0);
signal AI_DATA,mAI_DATA: std_logic_vector(63 downto 0);
signal ils_fifo_queue_dismantle_outdata:std_logic_vector(47 downto 0);
signal tcab_instream_queue_req_0:std_logic;
signal ils_fifo_queue_dismantle_store_req: std_logic;
signal tcab_outstream_queue_do_1:std_logic_vector(47 downto 0);
signal tcab_outstream_queue_req_1:std_logic;
signal ils_fifo_queue_dismantle_load_req: std_logic;
begin
oAI_DATA<=AI_DATA;
inst_ai:connect6ai_synth_tcab
113,8 → 139,26
rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0)
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0),
instream_queue_di_0=>ils_fifo_queue_dismantle_outdata(47 downto 0),
instream_queue_req_0=>tcab_instream_queue_req_0,
instream_queue_ready_0=>ils_fifo_queue_dismantle_store_req,
outstream_queue_do_1=>tcab_outstream_queue_do_1(47 downto 0),
outstream_queue_req_1=>tcab_outstream_queue_req_1,
outstream_queue_ready_1=>ils_fifo_queue_dismantle_load_req
);
ils_fifo_queue_dismantle:bram_based_stream_buffer
--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
port map(
clk=>iCLK,
reset=>not(iRST_n),
store_ready=>tcab_instream_queue_req_0,
flush=>'0',
store_req=>ils_fifo_queue_dismantle_store_req,
load_req=>ils_fifo_queue_dismantle_load_req,
load_ready=>tcab_outstream_queue_req_1,
indata=>tcab_outstream_queue_do_1(47 downto 0),
outdata=>ils_fifo_queue_dismantle_outdata(47 downto 0));
 
process(iCLK)
begin
/DE2.v
72,7 → 72,7
 
wire mTXD_Done_not;
RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_27),.RST_n(KEY[0]),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_100),.RST_n(KEY[0]),
.oTxD(UART_TXD),.iRxD(UART_RXD));
assign mTXD_Done = !mTXD_Done_not;
assign LED_RED[9] = mTXD_Done_not;
88,7 → 88,7
.iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
.oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
// Control
.iCLK(OSC_27),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
.iCLK(OSC_100),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
//AI
.oAI_DATA(DATA_to_AI),
.iAI_DATA(DATA_from_AI),
103,17 → 103,19
.oAI_Done(mAI_Done),
// Control
.iCLK(OSC_27),.iRST_n(mAI_RSTn) );
.iCLK(OSC_100),.iRST_n(mAI_RSTn) );
wire [63:0] CMD_Tmp;
 
//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16],
// CMD_Tmp[15:12],CMD_Tmp[11:8],CMD_Tmp[7:4],CMD_Tmp[3:0] };
assign mSEG7_DIG = {
DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
// DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
// DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
// DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
// DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
;
wire rst=!(KEY[0]);
wire OSC_100,lock;
assign LED_GREEN[7] = lock;
pll inst_pll(.areset(rst),.inclk0(OSC_50),.c0(OSC_100),.locked(lock));
endmodule

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