URL
https://opencores.org/ocsvn/copyblaze/copyblaze/trunk
Subversion Repositories copyblaze
Compare Revisions
- This comparison shows the changes necessary to convert path
/copyblaze/trunk/copyblaze
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/rtl/vhdl/cp_Toggle.vhd
46,7 → 46,6
-------------------------------------------------------------------------------- |
-- Signaux Fonctionels |
-------------------------------------------------------------------------------- |
Stall_i : in std_ulogic; |
Freeze_i : in std_ulogic; |
|
Phase1_o : out std_ulogic; |
66,7 → 65,6
type States_TYPE is |
( |
S_NORMAL , -- |
S_STALL , -- for Handshake Wishbone instruction. STALL overrides FREEZE. |
S_FREEZE -- for external "Freeze processor" signal |
); |
|
124,18 → 122,10
|
case iFSM_State is |
when S_NORMAL => |
if ( ( iPhase2 = '1' ) and (Stall_i = '1') ) then -- STALL overrides FREEZE. |
iFSM_State <= S_STALL; |
end if; |
if ( ( iPhase2 = '1' ) and (Freeze_i = '1') ) then |
iFSM_State <= S_FREEZE; |
end if; |
|
when S_STALL => |
if ( ( iPhase2 = '1' ) and (Stall_i = '0') ) then |
iFSM_State <= S_NORMAL; |
end if; |
|
when S_FREEZE => |
if ( ( iPhase2 = '1' ) and (Freeze_i = '0') ) then |
iFSM_State <= S_NORMAL; |
148,12 → 138,10
|
with iFSM_State select |
iPhase1Out <= iPhase1 when S_NORMAL, |
'0' when S_STALL, -- Phase 1 extended |
'0' when S_FREEZE, -- Phase 1 to 0 |
'0' when others; |
with iFSM_State select |
iPhase2Out <= iPhase2 when S_NORMAL, |
'1' when S_STALL, -- Phase 2 extended |
'0' when S_FREEZE, -- Phase 2 to 0 |
'0' when others; |
|
/rtl/vhdl/cp_copyBlaze.vhd
235,7 → 235,6
-------------------------------------------------------------------------------- |
-- Signaux Fonctionels |
-------------------------------------------------------------------------------- |
Stall_i : in std_ulogic; |
Freeze_i : in std_ulogic; |
|
Phase1_o : out std_ulogic; |
480,7 → 479,6
-------------------------------------------------------------------------------- |
-- Signaux Fonctionels |
-------------------------------------------------------------------------------- |
Stall_i => '0', |
Freeze_i => iFreeze , |
|
Phase1_o => iPhase1 , |
747,21 → 745,9
-------------------------------------------------------------------------------- |
-- WISHBONE |
-------------------------------------------------------------------------------- |
-- InOuts |
--iwbRST_I <= RST_I; |
--iwbCLK_I <= CLK_I; |
|
ADR_O <= iwbADR_O; |
iwbDAT_I <= DAT_I; |
DAT_O <= iwbDAT_O; |
WE_O <= iwbWE_O ; |
SEL_O <= iwbSEL_O; |
|
STB_O <= iwbSTB_O ; |
iwbACK_I <= ACK_I; |
CYC_O <= iwbCYC ; |
|
-- Management |
-- =================== -- |
-- Wishbone Management -- |
-- =================== -- |
iwbSTB_O <= iwbCYC; |
iwbSEL_O <= (others => '0'); |
|
768,9 → 754,12
iWB_inst <= iWbRdSing or iWbWrSing; |
iWB_vHs <= iwbCYC and iwbACK_I; |
|
-- Valid PC write |
-- Valid PC write -- |
-- ************** -- |
iWB_vPC <= ((iPhase1) and (iWB_vHs)); |
|
-- Then Valid Operation Write |
-- ************************** -- |
wbvOp_Proc : process (Rst_i_n, Clk_i) |
begin |
if ( Rst_i_n = '0' ) then |
779,20 → 768,36
iWB_vOp <= iWB_vPC; |
end if; |
end process wbvOp_Proc; |
|
wbCYC_Proc : process (Rst_i_n, Clk_i, iPhase1, iPhase2, iWbRdSing, iWbWrSing, iWB_vOp) |
|
-- CYCle determination -- |
-- ******************* -- |
wbCYC_Proc : process (Rst_i_n, Clk_i, iPhase2, iWB_vOp) |
begin |
if ( falling_edge(Clk_i) and |
( (iPhase1='1') and ((iWbRdSing='1') or (iWbWrSing='1')) ) |
) then |
|
iwbCYC <= '1'; |
elsif ( ( Rst_i_n = '0' ) or ((iPhase2='1') and (iWB_vOp='1')) |
) then |
if ( ( Rst_i_n = '0' ) or ((iPhase2='1') and (iWB_vOp='1')) ) then |
iwbCYC <= '0'; |
elsif ( falling_edge(Clk_i) ) then |
if ( (iPhase1='1') and ((iWbRdSing='1') or (iWbWrSing='1')) ) then |
iwbCYC <= '1'; |
end if; |
end if; |
end process wbCYC_Proc; |
|
-- ============== -- |
-- Inputs/Outputs -- |
-- ============== -- |
--iwbRST_I <= RST_I; |
--iwbCLK_I <= CLK_I; |
|
ADR_O <= iwbADR_O; |
iwbDAT_I <= DAT_I; |
DAT_O <= iwbDAT_O; |
WE_O <= iwbWE_O ; |
SEL_O <= iwbSEL_O; |
|
STB_O <= iwbSTB_O ; |
iwbACK_I <= ACK_I; |
CYC_O <= iwbCYC ; |
|
iwbWE_O <= iWbWrSing; |
iwbDAT_O <= iSxData; |
iwbADR_O <= iSyData; |