URL
https://opencores.org/ocsvn/copyblaze/copyblaze/trunk
Subversion Repositories copyblaze
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- This comparison shows the changes necessary to convert path
/copyblaze/trunk/copyblaze
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/rtl/vhdl/cp_copyBlaze.vhd
190,7 → 190,8
-- signal iwbCLK_I : std_ulogic; |
|
signal iwbADR_O : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
signal iwbDAT_I : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
signal iwbDAT_I , |
iwbDAT : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
signal iwbDAT_O : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
signal iwbWE_O : std_ulogic; |
signal iwbSEL_O : std_ulogic_vector(1 downto 0); |
203,10 → 204,10
signal iWbWrSing : std_ulogic; -- "Single Write Cycle" Wishbone instruction |
signal iWbRdSing : std_ulogic; -- "Single Read Cycle" Wishbone instruction |
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--signal iWB_inst : std_ulogic; -- WB Instruction |
signal iWB_vHs : std_ulogic; -- WB valid Handshake |
signal iWB_vPC : std_ulogic; -- WB valid PC increment |
signal iWB_vOp : std_ulogic; -- WB valid Operation |
--signal iWB_inst : std_ulogic; -- WB Instruction |
signal iWB_validHandshake : std_ulogic; -- WB valid Handshake |
signal iWB_validPC : std_ulogic; -- WB valid PC increment |
signal iWB_validOperand : std_ulogic; -- WB valid Operation |
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-- type wbStates_TYPE is |
707,10 → 708,10
-- Banc -- |
iSxDataIn <= iScratchDataOut when ( iFetch = '1' ) else |
IN_PORT_i when ( iInput = '1' ) else |
iwbDAT_I when ( iWbRdSing = '1') else |
iwbDAT when ( iWbRdSing = '1') else |
iAluResult ; |
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iBancWrite <= iWB_vOp when ( iWbRdSing = '1') else |
iBancWrite <= iWB_validOperand when ( iWbRdSing = '1') else |
iBancWriteOP ; |
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-- Scratch -- |
739,7 → 740,7
-- Evolution of the PC: |
-- condition : in Phase1 and the processor is not in stall by wishbone |
--iPcEnable <= (iPhase1 and not(iwbStall)); |
iPcEnable <= ((iPhase1) and (iWB_vHs)) when (iwbCYC='1') else |
iPcEnable <= ((iPhase1) and (iWB_validHandshake)) when (iwbCYC='1') else |
(iPhase1); |
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-------------------------------------------------------------------------------- |
749,11 → 750,11
-- Wishbone Management -- |
-- =================== -- |
--iWB_inst <= iWbRdSing or iWbWrSing; -- wishbone instruction |
iWB_vHs <= iwbCYC and iwbACK_I; -- wishbone VALID ACKNOWLEDGE |
iWB_validHandshake <= iwbCYC and iwbACK_I; -- wishbone VALID ACKNOWLEDGE |
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-- Valid PC write -- |
-- ************** -- |
iWB_vPC <= ((iPhase1) and (iWB_vHs)); -- Valid PC incremente |
iWB_validPC <= ((iPhase1) and (iWB_validHandshake)); -- Valid PC incremente |
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-- Then Valid Operand Read/Write |
-- ************************** -- |
760,18 → 761,22
wbvOp_Proc : process (Rst_i_n, Clk_i) |
begin |
if ( Rst_i_n = '0' ) then |
iWB_vOp <= '0'; |
iWB_validOperand <= '0'; |
iwbDAT <= (others => '0'); |
elsif ( rising_edge(Clk_i) ) then |
iWB_vOp <= iWB_vPC; -- Valid Operand Read/Write |
iWB_validOperand <= iWB_validPC; -- Valid Operand Read/Write |
if ( iWB_validPC = '1' ) then |
iwbDAT <= iwbDAT_I; |
end if; |
end if; |
end process wbvOp_Proc; |
|
-- CYCle determination -- |
-- ******************* -- |
wbCYC_Proc : process (Rst_i_n, Clk_i, iPhase2, iWB_vOp) |
wbCYC_Proc : process (Rst_i_n, Clk_i, iPhase2, iWB_validOperand) |
begin |
-- reset or end of wishbone cycle : after wishbone Operand Validation |
if ( ( Rst_i_n = '0' ) or ((iPhase2='1') and (iWB_vOp='1')) ) then |
if ( ( Rst_i_n = '0' ) or ((iPhase2='1') and (iWB_validOperand='1')) ) then |
iwbCYC <= '0'; |
-- valid a begining Wishbone Cycle: in Phase1 and wishbone instruction |
elsif ( falling_edge(Clk_i) ) then |