URL
https://opencores.org/ocsvn/copyblaze/copyblaze/trunk
Subversion Repositories copyblaze
Compare Revisions
- This comparison shows the changes necessary to convert path
/copyblaze/trunk
- from Rev 23 to Rev 24
- ↔ Reverse comparison
Rev 23 → Rev 24
/copyblaze/sim/rtl_sim/bin/tb_copyBlaze_ecoSystem_wave.do
0,0 → 1,69
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
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add wave -noupdate -divider {SYSTEM} |
add wave -noupdate /tb_copyBlaze_ecoSystem/* |
add wave -noupdate -divider {TOGGLE} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/U_Toggle/* |
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add wave -noupdate -divider {INTERRUPT MODULE} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_interrupt/* |
add wave -noupdate -divider {INTERRUPT} |
add wave sim:/tb_copyBlaze_ecoSystem/iClk |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/iPhase1 |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/iPhase2 |
add wave sim:/tb_copyBlaze_ecoSystem/iExtIntEvent |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/address_o |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/instruction_i |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/interrupt_i |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/U_Interrupt/iIE |
#add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/iIRecognized |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/iIEvent |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/Interrupt_Ack_o |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/iReturnI |
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add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_programflowcontrol/u_stack/istackmem |
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#add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/interrupt_ack_o |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_bancregister/ibancregmem |
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add wave -noupdate -divider {ALU} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_alu/* |
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add wave -noupdate -divider {FLAGS} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/U_Flags/* |
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add wave -noupdate -divider {BANC REGISTER} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_bancregister/* |
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do wave_copyBlaze.do |
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do wave_WISHBONE.do |
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add wave -noupdate -divider {FLOW CONTROL} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/U_ProgramFlowControl/* |
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add wave -noupdate -divider {STACK} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_programflowcontrol/u_stack/* |
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add wave -noupdate -divider {SCRATCH PAD MEMORY} |
add wave sim:/tb_copyBlaze_ecoSystem/uut/processor/u_scratchpad/* |
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TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {0 ps} 0} |
configure wave -namecolwidth 370 |
configure wave -valuecolwidth 67 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ps |
update |
WaveRestoreZoom {0 ps} {4203665 ps} |
/copyblaze/sim/rtl_sim/bin/tb_copyBlaze_ecoSystem_run.do
0,0 → 1,41
quietly set ACTELLIBNAME proasic3 |
quietly set PROJECT_DIR "E:/User/Projets/E3CAR/03-Fpga/mP_8bit/copyblaze/copyblaze" |
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if {[file exists presynth/_info]} { |
echo "INFO: Simulation library presynth already exists" |
} else { |
vlib presynth |
} |
vmap presynth presynth |
vmap proasic3 "C:/Actel/Libero_v9.1/Designer/lib/modelsim/precompiled/vhdl/proasic3" |
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vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_Usefull_Pkg.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_Toggle.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_Interrupt.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_ProgramCounter.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_Stack.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_ProgramFlowControl.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_DecodeControl.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_FullAdder.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_CLAAdder.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_ALU.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_Flags.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_BancRegister.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_ScratchPad.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_copyBlaze.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_ROM_Code.vhd" |
vcom -93 -explicit -work presynth "${PROJECT_DIR}/rtl/vhdl/cp_copyBlaze_ecoSystem.vhd" |
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vcom -93 -explicit -work presynth "${PROJECT_DIR}/sim/rtl_sim/src/wb_gpio/WBOPRT08.vhd" |
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vcom -93 -explicit -work presynth "${PROJECT_DIR}/bench/vhdl/tb_copyBlaze_ecoSystem.vhd" |
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vsim -L proasic3 -L presynth -t 1ps presynth.tb_copyBlaze_ecoSystem |
# The following lines are commented because no testbench is associated with the project |
# add wave /tb_copyBlaze_ecoSystem/* |
# run 1000ns |
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radix hexadecimal |
do wave_tb_copyBlaze_ecoSystem.do |
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run -all |