URL
https://opencores.org/ocsvn/copyblaze/copyblaze/trunk
Subversion Repositories copyblaze
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- This comparison shows the changes necessary to convert path
/copyblaze
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/trunk/copyblaze/sim/rtl_sim/src/wb_gpio/wb_gpio_08.vhd
26,6 → 26,9
-- Implementation ----------------------------------------------------------- |
architecture rtl of wb_gpio_08 is |
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constant OPORT_ADDR : std_ulogic_vector(7 downto 0) := x"04"; |
constant IPORT_ADDR : std_ulogic_vector(7 downto 0) := x"01"; |
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signal wbactive : std_ulogic; |
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signal oport_reg : std_ulogic_vector(7 downto 0); |
38,7 → 41,7
-- synchronize incoming signals (anti-meta-state) |
syncproc: process(clk) is |
begin |
if clk'event and clk='1' then |
if (rising_edge(clk)) then |
iport_reg <= iport; |
end if; |
end process; |
48,20 → 51,20
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wb_ack_o <= wb_stb_i and wb_cyc_i; |
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wb_dat_o <= iport_reg when wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i=x"01" else |
oport_reg when wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i=x"04" else |
wb_dat_o <= iport_reg when ( wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i=IPORT_ADDR ) else |
oport_reg when ( wb_stb_i='1' and wb_cyc_i='1' and wb_adr_i=OPORT_ADDR ) else |
(others => '-'); |
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writeproc: process (reset, clk) is |
variable val : std_ulogic_vector(31 downto 0); |
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begin |
if reset='0' then |
if (reset='0') then |
oport_reg <= (others => '0'); |
elsif clk'event and clk='1' then |
if wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then |
elsif ( rising_edge(clk)) then |
if (wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1') then |
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-- decode WB_ADR_I -- |
if wb_adr_i=x"04" then |
if (wb_adr_i=OPORT_ADDR) then |
oport_reg <= wb_dat_i; |
end if; |
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