URL
https://opencores.org/ocsvn/copyblaze/copyblaze/trunk
Subversion Repositories copyblaze
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/copyblaze
- from Rev 33 to Rev 34
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Rev 33 → Rev 34
/trunk/copyblaze/bench/vhdl/tb_copyBlaze_ecoSystem_wb-timer.vhd
0,0 → 1,363
-------------------------------------------------------------------------------- |
-- Company: |
-- |
-- File: tb_copyBlaze_ecoSystem_wb-timer.vhd |
-- |
-- Description: |
-- projet copyblaze |
-- copyBlaze_ecoSystem testbench |
-- |
-- File history: |
-- v1.0: 25/11/11: Creation |
-- |
-- Targeted device: ProAsic A3P250 VQFP100 |
-- Author: AbdAllah Meziti |
-------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
-------------------------------------------------------------------------------- |
-- Entity: tb_copyBlaze_ecoSystem_wb_timer |
-- |
-- Description: |
-- |
-- REMARQUE: |
-- |
-- |
-- History: |
-- 25/11/11 AM: Creation |
-- --------------------- |
-- xx/xx/xx AM: |
-- |
-------------------------------------------------------------------------------- |
entity tb_copyBlaze_ecoSystem_wb_timer is |
end tb_copyBlaze_ecoSystem_wb_timer; |
|
-------------------------------------------------------------------------------- |
-- Architecture: behavior |
-- of entity : tb_copyBlaze_ecoSystem_wb_timer |
-------------------------------------------------------------------------------- |
architecture behavior of tb_copyBlaze_ecoSystem_wb_timer is |
|
-------------------------------------------------------------------------------- |
|
-------------------------------------------------------------------------------- |
-- Constant for testbench |
constant CST_RESET_LENGTH : positive := 7; |
constant CST_MAX_CYCLES : positive := 500; |
|
constant CST_FREQ : integer := 4; -- Mhz |
constant CST_PERIOD : time := 1 us/CST_FREQ; |
|
-- Constant for the cp_copyBlaze_ecoSystem generic |
constant CST_WIDTH_DATA : positive := 8; |
constant CST_WIDTH_PC : positive := 10; |
constant CST_WIDTH_INST : positive := 18; |
|
constant CST_DEPTH_STACK : positive := 31; |
constant CST_DEPTH_BANC : positive := 16; |
constant CST_DEPTH_SCRATCH : positive := 64; |
|
constant CST_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"3FF"; |
|
-------------------------------------------------------------------------------- |
|
-------------------------------------------------------------------------------- |
component cp_copyBlaze_ecoSystem |
generic |
( |
GEN_WIDTH_DATA : positive := 8; |
GEN_WIDTH_PC : positive := 10; |
GEN_WIDTH_INST : positive := 18; |
|
GEN_DEPTH_STACK : positive := 15; -- Taille (en octet) de la Stack |
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register |
GEN_DEPTH_SCRATCH : positive := 64; -- Taille (en octet) du Scratch Pad |
|
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"3FF" |
); |
Port ( |
-------------------------------------------------------------------------------- |
-- Signaux Systeme |
-------------------------------------------------------------------------------- |
Clk_i : in std_ulogic; |
--Rst_i_n : in std_ulogic; |
|
-------------------------------------------------------------------------------- |
-- Signaux Fonctionels |
-------------------------------------------------------------------------------- |
Interrupt_i : in std_ulogic; |
Interrupt_Ack_o : out std_ulogic; |
|
IN_PORT_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
OUT_PORT_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
PORT_ID_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
READ_STROBE_o : out std_ulogic; |
WRITE_STROBE_o : out std_ulogic; |
-------------------------------------------------------------------------------- |
-- Signaux WishBone |
-------------------------------------------------------------------------------- |
Freeze_i : in std_ulogic; |
|
-------------------------------------------------------------------------------- |
-- Signaux Wishbone Interface |
-------------------------------------------------------------------------------- |
--RST_I : in std_ulogic; |
--CLK_I : in std_ulogic; |
|
ADR_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
DAT_I : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
DAT_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); |
WE_O : out std_ulogic; |
SEL_O : out std_ulogic_vector(1 downto 0); |
|
STB_O : out std_ulogic; |
ACK_I : in std_ulogic; |
CYC_O : out std_ulogic |
); |
end component; |
|
component wb_timer_8 |
port ( |
clk : in std_ulogic; |
reset : in std_ulogic; |
-- Wishbone bus |
wb_adr_i : in std_ulogic_vector(7 downto 0); |
wb_dat_i : in std_ulogic_vector(7 downto 0); |
wb_dat_o : out std_ulogic_vector(7 downto 0); |
wb_cyc_i : in std_ulogic; |
wb_stb_i : in std_ulogic; |
wb_ack_o : out std_ulogic; |
wb_we_i : in std_ulogic; |
wb_irq0_o: out std_ulogic; |
wb_irq1_o: out std_ulogic ); |
end component; |
|
-------------------------------------------------------------------------------- |
|
-------------------------------------------------------------------------------- |
signal iClk : std_ulogic := '0'; |
signal iReset : std_ulogic; |
signal iResetN : std_ulogic; |
|
signal iInterrupt : std_ulogic; |
signal iInterrupt_Ack : std_ulogic; |
signal iIn_port : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iOut_port : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iPort_id : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iRead_strobe : std_ulogic; |
signal iWrite_strobe : std_ulogic; |
|
signal iFreeze : std_ulogic := '0'; -- Freeze the processor |
|
signal iReset_counter : natural range 0 to CST_RESET_LENGTH := CST_RESET_LENGTH; -- VERY BAD SOLUTION |
signal iCounter : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iWaveForms : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iExtIntEvent : std_ulogic;-- := '0'; |
|
signal iWbSTB : std_ulogic; |
signal iWbCYC : std_ulogic; |
signal iWbACK : std_ulogic;-- := '0';--'0'; |
signal iWbWE : std_ulogic;-- := '0';--'0'; |
|
signal iWbDAT_I : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iWbDAT_O : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
signal iWbADR : std_ulogic_vector(CST_WIDTH_DATA-1 downto 0); |
|
begin |
|
-- ***************************************** -- |
-- UUT : Unit Under Test : cp_copyBlaze_ecoSystem -- |
-- ***************************************** -- |
uut: cp_copyBlaze_ecoSystem |
generic map |
( |
GEN_WIDTH_DATA => CST_WIDTH_DATA, |
GEN_WIDTH_PC => CST_WIDTH_PC, |
GEN_WIDTH_INST => CST_WIDTH_INST, |
|
GEN_DEPTH_STACK => CST_DEPTH_STACK, |
GEN_DEPTH_BANC => CST_DEPTH_BANC, |
GEN_DEPTH_SCRATCH => CST_DEPTH_SCRATCH, |
|
GEN_INT_VECTOR => CST_INT_VECTOR |
) |
Port map |
( |
-------------------------------------------------------------------------------- |
-- Signaux Systeme |
-------------------------------------------------------------------------------- |
Clk_i => iClk, |
--Rst_i_n : in std_ulogic; |
|
-------------------------------------------------------------------------------- |
-- Signaux Fonctionels |
-------------------------------------------------------------------------------- |
Interrupt_i => iExtIntEvent,--iInterrupt, |
Interrupt_Ack_o => iInterrupt_Ack, |
|
IN_PORT_i => iIn_port, |
OUT_PORT_o => iOut_port, |
PORT_ID_o => iPort_id, |
READ_STROBE_o => iRead_strobe, |
WRITE_STROBE_o => iWrite_strobe, |
-------------------------------------------------------------------------------- |
-- Signaux WishBone |
-------------------------------------------------------------------------------- |
Freeze_i => iFreeze, |
|
-------------------------------------------------------------------------------- |
-- Signaux Wishbone Interface |
-------------------------------------------------------------------------------- |
--RST_I => iReset, |
--CLK_I => Clk_i, |
|
ADR_O => iWbADR, |
DAT_I => iWbDAT_I,--(others => '0'), |
DAT_O => iWbDAT_O,--open, |
WE_O => iWbWE,--open, |
SEL_O => open, |
|
STB_O => iWbSTB, |
ACK_I => iWbACK, |
CYC_O => iWbCYC |
); |
|
wb_timer : wb_timer_8 |
port map( |
clk => iClk, |
reset => iResetN, |
-- Wishbone bus |
wb_adr_i => iWbADR, |
wb_dat_i => iWbDAT_O, |
wb_dat_o => iWbDAT_I, |
wb_cyc_i => iWbCYC, |
wb_stb_i => iWbSTB, |
wb_ack_o => iWbACK, |
wb_we_i => iWbWE, |
wb_irq0_o => iExtIntEvent, |
wb_irq1_o => open |
); |
|
-------------------------------------------------------------------------------- |
-- Process : Interrupt_Proc |
-- Description: Interrupt Logic for cp_copyBlaze_ecoSystem |
-------------------------------------------------------------------------------- |
Interrupt_Proc: process(iReset, iClk) |
begin |
if (iReset='0') then |
iInterrupt <= '0'; |
elsif ( rising_edge(iClk) ) then |
if (iExtIntEvent='1') then |
iInterrupt <= '1'; |
elsif (iInterrupt_Ack='1') then |
iInterrupt <= '0'; |
end if; |
end if; |
end process Interrupt_Proc; |
|
-------------------------------------------------------------------------------- |
-- Process : Reset_Proc |
-- Description: Reset Logic for cp_copyBlaze_ecoSystem |
-------------------------------------------------------------------------------- |
Reset_Proc: process(iClk) |
begin |
-- delayed iReset circuit |
if ( rising_edge(iClk) ) then |
if ( iReset_counter = 0 ) then |
iReset <= '1'; |
else |
iReset <= '0'; |
iReset_counter <= iReset_counter - 1; |
end if; |
end if; |
end process Reset_Proc; |
iResetN <= not(iReset); |
|
-------------------------------------------------------------------------------- |
-- Process : IO_Proc |
-- Description: adding the output registers to the processor |
-------------------------------------------------------------------------------- |
IO_Proc: process(iClk) |
begin |
-- waveform register at iAddress 02 |
if ( rising_edge(iClk) ) then |
if (iPort_id(1)='1' and iWrite_strobe='1') then |
iWaveForms <= iOut_port; |
end if; |
end if; |
|
-- Interrupt iCounter register at iAddress 04 |
if ( rising_edge(iClk) ) then |
if (iPort_id(2)='1' and iWrite_strobe='1') then |
iCounter <= iOut_port; |
end if; |
end if; |
|
end process IO_Proc; |
|
-- ********************* -- |
-- STIMULIS FOR THE TEST -- |
-- ********************* -- |
-- Unused inputs on processor |
iIn_port <= x"28"; |
|
--iClk <= not iClk after 0.5 * CST_PERIOD; |
-------------------------------------------------------------------------------- |
-- Process : INT_Proc |
-- Description: Nominal 100MHz clock which also defines number of cycles in simulation |
-------------------------------------------------------------------------------- |
INT_Proc : process |
variable max_cycles : integer := CST_MAX_CYCLES; |
variable cycle_count : integer := 0; |
begin |
-- Define the clock cycles and the clock cycle iCounter |
while cycle_count < max_cycles loop |
|
-- wait until rising_edge(iClk) ; |
iClk <= '0'; |
wait for CST_PERIOD; |
iClk <= '1'; |
cycle_count := cycle_count + 1; |
wait for CST_PERIOD; |
|
|
--Now define stimulus relative to a given clock cycle |
case cycle_count is |
-- *************** -- |
-- INTERRUPT EVENT -- |
-- *************** -- |
--when 30 => iExtIntEvent <= '1'; |
--when 34 => iExtIntEvent <= '0'; |
-- |
--when 67 => iExtIntEvent <= '1'; -- Take care when the "iIE" bit is not set. In this case how to manage Interrupt_Ack_o |
--when 71 => iExtIntEvent <= '0'; |
|
--when 300 => iExtIntEvent <= '1'; |
--when 304 => iExtIntEvent <= '0'; |
|
-- ************ -- |
-- FREEZE EVENT -- |
-- ************ -- |
when 130 => iFreeze <= '1'; |
when 150 => iFreeze <= '0'; |
|
-- ****** -- |
-- WB ACK -- |
-- ****** -- |
--when 420 => iWbACK <= '1'; |
--when 420+1 => iWbACK <= '0'; |
|
when others => --iExtIntEvent <= iExtIntEvent; -- hold last defined value |
|
end case; |
|
end loop; |
|
wait; -- end of simulation. |
|
end process INT_Proc; |
|
end behavior; |
/trunk/copyblaze/sim/rtl_sim/src/wb_timer/wb_timer_8.vhd
0,0 → 1,170
----------------------------------------------------------------------------- |
-- Wishbone TIMER 8bit ------------------------------------------------------ |
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity wb_timer_8 is |
port ( |
clk : in std_ulogic; |
reset : in std_ulogic; |
-- Wishbone bus |
wb_adr_i : in std_ulogic_vector(7 downto 0); |
wb_dat_i : in std_ulogic_vector(7 downto 0); |
wb_dat_o : out std_ulogic_vector(7 downto 0); |
wb_cyc_i : in std_ulogic; |
wb_stb_i : in std_ulogic; |
wb_ack_o : out std_ulogic; |
wb_we_i : in std_ulogic; |
wb_irq0_o: out std_ulogic; |
wb_irq1_o: out std_ulogic ); |
end wb_timer_8; |
|
----------------------------------------------------------------------------- |
-- 0x00: TCR0 Timer Control and Status Register |
-- 0x04: COMPARE0 |
-- 0x08: COUNTER0 |
-- 0x0C: TCR1 |
-- 0x10: COMPARE1 |
-- 0x14: COUNTER1 |
-- |
-- TCRx: |
-- |
-- +-----------------------------------+-----+-----+--------+-------+ |
-- | ZEROs ( 7 downto 4) | en0 | ar0 | irq0en | trig0 | |
-- +-----------------------------------+-----+-----+--------+-------+ |
-- |
|
----------------------------------------------------------------------------- |
-- Implementation ----------------------------------------------------------- |
architecture rtl of wb_timer_8 is |
constant ADDR_TRC0 : std_ulogic_vector(7 downto 0) := x"00"; |
constant ADDR_COMPARE0 : std_ulogic_vector(7 downto 0) := x"04"; |
constant ADDR_COUNTER0 : std_ulogic_vector(7 downto 0) := x"08"; |
constant ADDR_TRC1 : std_ulogic_vector(7 downto 0) := x"0C"; |
constant ADDR_COMPARE1 : std_ulogic_vector(7 downto 0) := x"10"; |
constant ADDR_COUNTER1 : std_ulogic_vector(7 downto 0) := x"14"; |
|
signal wbactive : std_ulogic; |
|
signal counter0 : unsigned(7 downto 0); |
signal counter1 : unsigned(7 downto 0); |
|
signal compare0 : unsigned(7 downto 0); |
signal compare1 : unsigned(7 downto 0); |
|
signal en0, en1 : std_ulogic; -- Enable counter |
signal ar0, ar1 : std_ulogic; -- Auto Reload |
signal trig0, trig1 : std_ulogic; -- Triggered |
|
signal irq0en, irq1en: std_ulogic; -- Enable Interrupt |
|
signal tcr0, tcr1 : std_ulogic_vector(7 downto 0); |
|
|
begin |
|
----------------------------------------------------------------------------- |
-- Wishbone handling -------------------------------------------------------- |
wbactive <= wb_stb_i and wb_cyc_i; |
|
wb_ack_o <= wbactive; |
|
wb_dat_o <= tcr0 when wbactive='1' and wb_adr_i=ADDR_TRC0 else |
std_ulogic_vector(compare0) when wbactive='1' and wb_adr_i=ADDR_COMPARE0 else |
std_ulogic_vector(counter0) when wbactive='1' and wb_adr_i=ADDR_COUNTER0 else |
tcr1 when wbactive='1' and wb_adr_i=ADDR_TRC1 else |
std_ulogic_vector(compare1) when wbactive='1' and wb_adr_i=ADDR_COMPARE1 else |
std_ulogic_vector(counter1) when wbactive='1' and wb_adr_i=ADDR_COUNTER1 else |
(others => '-'); |
|
wb_irq0_o <= trig0 and irq0en; |
wb_irq1_o <= trig1 and irq1en; |
|
tcr0 <= "0000" & en0 & ar0 & irq0en & trig0; |
tcr1 <= "0000" & en1 & ar1 & irq1en & trig1; |
|
timerproc: process (reset, clk) is |
variable val : std_ulogic_vector(7 downto 0); |
begin |
if reset='1' then |
en0 <= '0'; -- enable |
en1 <= '0'; |
ar0 <= '0'; -- auto reload |
ar1 <= '0'; |
trig0 <= '0'; -- triggered |
trig1 <= '0'; |
irq0en <= '0'; -- IRQ enable |
irq1en <= '0'; |
compare0 <= TO_UNSIGNED(0, 8); -- compare |
compare1 <= TO_UNSIGNED(0, 8); |
counter0 <= TO_UNSIGNED(0, 8); -- actual counter |
counter1 <= TO_UNSIGNED(0, 8); |
elsif clk'event and clk='1' then |
|
-- Reset trigX on TCR access -------------------------------- |
if wbactive='1' and wb_adr_i=x"00" then |
trig0 <= '0'; |
end if; |
if wbactive='1' and wb_adr_i=x"0C" then |
trig1 <= '0'; |
end if; |
|
-- WB write register ---------------------------------------- |
if wbactive='1' and wb_we_i='1' then |
|
val := wb_dat_i; |
|
-- decode WB_ADR_I -- |
if wb_adr_i=ADDR_TRC0 then |
en0 <= val(3); |
ar0 <= val(2); |
irq0en <= val(1); |
elsif wb_adr_i=ADDR_COMPARE0 then |
compare0 <= unsigned(val); |
elsif wb_adr_i=ADDR_COUNTER0 then |
counter0 <= unsigned(val); |
elsif wb_adr_i=ADDR_TRC1 then |
en1 <= val(3); |
ar1 <= val(2); |
irq1en <= val(1); |
elsif wb_adr_i=ADDR_COMPARE1 then |
compare1 <= unsigned(val); |
elsif wb_adr_i=ADDR_COUNTER1 then |
counter1 <= unsigned(val); |
end if; |
end if; |
|
|
-- timer0 --------------------------------------------------- |
if en0='1' then |
if counter0 = compare0 then |
trig0 <= '1'; |
if ar0='1' then |
counter0 <= to_unsigned(1, 8); |
else |
en0 <= '0'; |
end if; |
else |
counter0 <= counter0 + 1; |
end if; |
end if; |
|
-- timer1 --------------------------------------------------- |
if en1='1' then |
if counter1 = compare1 then |
trig1 <= '1'; |
if ar1='1' then |
counter1 <= to_unsigned(1, 8); |
else |
en1 <= '0'; |
end if; |
else |
counter1 <= counter1 + 1; |
end if; |
end if; |
|
end if; |
end process; |
|
end rtl; |
/trunk/copyblaze/sim/rtl_sim/bin/tb_copyBlaze_ecoSystem_wb-timer_wave.do
0,0 → 1,124
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider {WISHBONE timer} |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/clk |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/reset |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_adr_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_dat_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_dat_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_cyc_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_stb_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_ack_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_we_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_irq0_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wb_irq1_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/wbactive |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/counter0 |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/counter1 |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/compare0 |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/compare1 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/en0 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/en1 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/ar0 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/ar1 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/trig0 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/trig1 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/irq0en |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/wb_timer/irq1en |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/tcr0 |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/wb_timer/tcr1 |
add wave -noupdate -divider COPYBLAZE |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/clk_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/rst_i_n |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/address_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/instruction_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/interrupt_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/interrupt_ack_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/in_port_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/out_port_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/port_id_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/read_strobe_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/write_strobe_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/freeze_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/adr_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/dat_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/dat_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/we_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/sel_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/stb_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ack_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/cyc_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iphase1 |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iphase2 |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iaaa |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ikk |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iss |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ipp |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iz |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ic |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/izi |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ici |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ialuresult |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/isxdatain |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/isxdata |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/isydata |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/isxptr |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/isyptr |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iscratchptr |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iscratchdataout |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ibancwriteop |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ibancwrite |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iscratchwrite |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ifetch |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iinput |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iouput |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ioperationselect |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ioperandselect |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iarithoper |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ilogicoper |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/ishiftbit |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ishiftsens |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iflagswrite |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iflagspush |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iflagspop |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iconditionctrl |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ijump |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/icall |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ireturn |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ireturni |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ipcenable |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iievent |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iiewrite |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iievalue |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/ifreeze |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbadr_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbdat_i |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbdat |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbdat_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbwe_o |
add wave -noupdate -radix hexadecimal /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbsel_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbstb_o |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwback_i |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbcyc |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbwrsing |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwbrdsing |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwb_validhandshake |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwb_validpc |
add wave -noupdate /tb_copyblaze_ecosystem_wb_timer/uut/processor/iwb_validoperand |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {76250000 ps} 0} |
configure wave -namecolwidth 400 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ps |
update |
WaveRestoreZoom {0 ps} {248760331 ps} |
/trunk/copyblaze/sim/rtl_sim/bin/tb_copyBlaze_ecoSystem_wb-timer_run.do
0,0 → 1,38
quietly set ACTELLIBNAME proasic3 |
do PATH.do |
|
if {[file exists presynth/_info]} { |
echo "INFO: Simulation library presynth already exists" |
} else { |
vlib presynth |
} |
vmap presynth presynth |
vmap proasic3 "C:/Actel/Libero_v9.1/Designer/lib/modelsim/precompiled/vhdl/proasic3" |
|
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Usefull_Pkg.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Toggle.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Interrupt.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_ProgramCounter.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Stack.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_ProgramFlowControl.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_FullAdder.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_CLAAdder.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Alu.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_Flags.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_BancRegister.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_ScratchPad.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_DecodeControl.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_copyBlaze.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_ROM_Code.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/rtl/vhdl/cp_copyBlaze_ecoSystem.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/sim/rtl_sim/src/wb_timer/wb_timer_8.vhd" |
vcom -93 -explicit -work presynth "C:/Users/AbdAllah/Documents/mP/mP/copyblaze/copyblaze/bench/vhdl/tb_copyBlaze_ecoSystem_wb-timer.vhd" |
|
vsim -L proasic3 -L presynth -t 1ps presynth.tb_copyBlaze_ecoSystem_wb_timer |
# The following lines are commented because no testbench is associated with the project |
# add wave /testbench/* |
# run 1000ns |
|
do tb_copyBlaze_ecoSystem_wb-timer_wave.do |
|
run -all |