URL
https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk
Subversion Repositories core1990_interlaken
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- This comparison shows the changes necessary to convert path
/core1990_interlaken
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/trunk/gateware/scripts/vivado_import_virtex7.tcl
0,0 → 1,86
# |
# File import script for the core1990 interlaken hdl project |
# |
# |
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#Script Configuration |
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set proj_name core1990_interlaken |
# Set the supportfiles directory path |
set scriptdir [pwd] |
set proj_dir $scriptdir/../ |
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#Close currently open project and create a new one. (OVERWRITES PROJECT!!) |
close_project -quiet |
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create_project -force -part xc7vx485tffg1761-2 $proj_name $proj_dir/projects/$proj_name |
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set_property target_language VHDL [current_project] |
set_property default_lib work [current_project] |
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# ---------------------------------------------------------- |
# Core1990 top file |
# ---------------------------------------------------------- |
read_vhdl -library work $proj_dir/sources/interlaken_interface.vhd |
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add_files -fileset sim_1 -norecurse $proj_dir/simulation/interlaken_interface_tb.vhd |
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# ---------------------------------------------------------- |
# CRC |
# ---------------------------------------------------------- |
read_vhdl -library work $proj_dir/sources/crc/crc-24.vhd |
read_vhdl -library work $proj_dir/sources/crc/crc-32.vhd |
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# ---------------------------------------------------------- |
# Transmitter |
# ---------------------------------------------------------- |
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read_vhdl -library work $proj_dir/sources/transmitter/framing_burst.vhd |
read_vhdl -library work $proj_dir/sources/transmitter/framing_meta.vhd |
read_vhdl -library work $proj_dir/sources/transmitter/scrambler.vhd |
read_vhdl -library work $proj_dir/sources/transmitter/encoder.vhd |
read_vhdl -library work $proj_dir/sources/transmitter/interlaken_transmitter.vhd |
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# ---------------------------------------------------------- |
# Receiver |
# ---------------------------------------------------------- |
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read_vhdl -library work $proj_dir/sources/receiver/deframing_burst.vhd |
read_vhdl -library work $proj_dir/sources/receiver/deframing_meta.vhd |
read_vhdl -library work $proj_dir/sources/receiver/descrambler.vhd |
read_vhdl -library work $proj_dir/sources/receiver/decoder.vhd |
read_vhdl -library work $proj_dir/sources/receiver/interlaken_receiver.vhd |
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# ---------------------------------------------------------- |
# IP cores |
# ---------------------------------------------------------- |
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import_ip $proj_dir/sources/ip_cores/clk_40MHz.xci |
import_ip $proj_dir/sources/ip_cores/Transceiver_10g_64b67b.xci |
import_ip $proj_dir/sources/ip_cores/RX_FIFO.xci |
import_ip $proj_dir/sources/ip_cores/TX_FIFO.xci |
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# ---------------------------------------------------------- |
# finish project initilization |
# ---------------------------------------------------------- |
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upgrade_ip [get_ips {clk_40MHz Transceiver_10g_64b67b RX_FIFO TX_FIFO} ] |
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read_xdc -verbose $proj_dir/constraints/Core1990_Constraints.xdc |
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#close [ open $proj_dir/constraints/probes.xdc w ] |
#read_xdc -verbose $proj_dir/constraints/probes.xdc |
#set_property target_constrs_file $proj_dir/constraints/probes.xdc [current_fileset -constrset] |
#set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE MoreGlobalIterations [get_runs impl_1] |
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set_property top interlaken_interface [current_fileset] |
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puts "INFO: Done!" |
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