OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /core_arm/trunk/syn/synplify
    from Rev 2 to Rev 4
    ↔ Reverse comparison
  •

Rev 2 → Rev 4

/core.sdc
0,0 → 1,16
 
define_clock -name {clk} -freq 50.0 -clockgroup default_clkgroup
define_clock -name {pci_clk_in} -freq 40.000 -clockgroup pci_clkgroup
define_clock -name {erx_clk} -freq 30.000 -clockgroup erx_clk_clkgroup
define_clock -name {etx_clk} -freq 30.000 -clockgroup etx_clk_clkgroup
 
define_output_delay -default 8.00 -ref clk:r
define_input_delay -default 10.00 -ref clk:r
define_output_delay -default 14.00 -ref pci_clk_in:r
define_input_delay -default 18.00 -ref pci_clk_in:r
define_output_delay -default 8.00 -ref erx_clk:r
define_input_delay -default 10.00 -ref erx_clk:r
define_output_delay -default 8.00 -ref etx_clk:r
define_input_delay -default 10.00 -ref etx_clk:r
 
define_global_attribute syn_useioff {1}
/core.prj
0,0 → 1,33
 
source "core_files.tcl"
add_file -constraint "core.sdc"
 
impl -add syn
 
set_option -technology VIRTEX-E
set_option -part XCV1000E
set_option -package FG1156
set_option -speed_grade -6
 
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "core"
 
set_option -frequency 45.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -modular 0
set_option -retiming 1
 
set_option -write_verilog 0
set_option -write_vhdl 0
 
set_option -write_apr_constraint 0
 
project -result_file "./core.edf"
 
set_option -compiler_compatible 0
impl -active "syn"
/.recordref --- syntmp/core.plg (nonexistent) +++ syntmp/core.plg (revision 4) @@ -0,0 +1,12 @@ +@P: Worst Slack : 0.905 +@P: clk - Estimated Frequency : 52.4 MHz +@P: clk - Requested Frequency : 50.0 MHz +@P: clk - Estimated Period : 19.095 +@P: clk - Requested Period : 20.000 +@P: clk - Slack : 0.905 +@P: core Part : xcv1000efg1156-6 +@P: core I/O primitives : 116 +@P: core I/O Register bits : 114 +@P: core Register bits (Non I/O) : 1849 (7%) +@P: core Block Rams : 6 of 96 (6%) +@P: core Total Luts : 4652 (18%)
/core_files.tcl
0,0 → 1,91
add_file -vhdl -lib work "../../vhdl/bus/amba.vhd"
add_file -vhdl -lib work "../../vhdl/libs/memdef.vhd"
add_file -vhdl -lib work "../../vhdl/config.vhd"
add_file -vhdl -lib work "../../vhdl/core/libs/corelib.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/leon_target.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/leon_device.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/leon_config.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/mmuconfig.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/sparcv8.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/leon_iface.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/bprom.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_generic.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_atc25.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_atc18.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_atc35.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_fs90.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_umc18.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_virtex.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_virtex2.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_tsmc25.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_proasic.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_axcel.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/multlib.vhd"
add_file -vhdl -lib work "../../vhdl/tech/tech_map.vhd"
add_file -vhdl -lib work "../../vhdl/core/ctrl/ctrl_comp.vhd"
add_file -vhdl -lib work "../../vhdl/core/core_config.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/serial/peri_serial_comp.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/io/peri_io_comp.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/mem/peri_mem_comp.vhd"
add_file -vhdl -lib work "../../vhdl/core/core_comp.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/mem/peri_mem_config.vhd"
add_file -vhdl -lib work "../../vhdl/sparc/macro.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/mem/sdmctrl.vhd"
add_file -vhdl -lib work "../../vhdl/peripherals/mem/mctrl.vhd"
add_file -vhdl -lib work "../../vhdl/libs/int.vhd"
add_file -vhdl -lib work "../../vhdl/bus/bus_comp.vhd"
add_file -vhdl -lib work "../../vhdl/bus/ahbmst_mp.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/cache_config.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/libs/gencmem_lib.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/libs/gendc_lib.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/libs/genic_lib.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/libs/genwb_lib.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/cache_comp.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/gencmem.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/genic.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/genwbfifo.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/genwb.vhd"
add_file -vhdl -lib work "../../vhdl/arith/cnt/arith_cnt_comp.vhd"
add_file -vhdl -lib work "../../vhdl/arith/cnt/arith_cnt8.vhd"
add_file -vhdl -lib work "../../vhdl/mem/cache/gendc.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcache.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armpmodel.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armshiefter.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armdecode.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armpctrl.vhd"
add_file -vhdl -lib work "../../vhdl/arm/arm_comp.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_imstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_festg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_destg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armdebug.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armcmd.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armldst.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_comp.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_al.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_sr.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_bl.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_ld.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_st.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_lm.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_sm.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_sw.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_cr.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_cl.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armcmd_cs.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_drstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_rrstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/libs/armctrl.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_rsstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_exstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_dmstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_mestg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu_wrstg.vhd"
add_file -vhdl -lib work "../../vhdl/arm/armiu.vhd"
add_file -vhdl -lib work "../../vhdl/arm/arm_proc.vhd"
add_file -vhdl -lib work "../../vhdl/bus/ahbarb.vhd"
add_file -vhdl -lib work "../../vhdl/bus/apbmst.vhd"
add_file -vhdl -lib work "../../vhdl/core/soc_gen.vhd"
add_file -vhdl -lib work "../../vhdl/core/ctrl/rstgen.vhd"
add_file -vhdl -lib work "../../vhdl/core/core.vhd"
 
 
/Makefile
0,0 → 1,4
CLEANFILES = *.ngc *.bgn *.bld *.dly *.drc *.ll *.mrp *.msk *.ncd *.ngd \
*.ngm *.pad *.par *.pcf *.srp *.twr *.xpi *.nav *.lst *.scr *.bit \
xst *.tlg *.log *.srs *.srr *.plg *.fse *.vhm *.srm *.srd *.edf *.edn \
*.prd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.