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/vhdl/reg_pc.vhd
0,0 → 1,220
-- VHDL Entity R6502_TC.Reg_PC.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:52 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity Reg_PC is
port(
adr_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
ld_i : in std_logic_vector (1 downto 0);
ld_pc_i : in std_logic;
offset_i : in std_logic_vector (15 downto 0);
rst_rst_n_i : in std_logic;
sel_pc_as_i : in std_logic;
sel_pc_in_i : in std_logic;
sel_pc_val_i : in std_logic_vector (1 downto 0);
adr_nxt_pc_o : out std_logic_vector (15 downto 0);
adr_pc_o : out std_logic_vector (15 downto 0)
);
 
-- Declarations
 
end Reg_PC ;
 
-- Jens-D. Gutschmidt Project: R6502_TC
-- scantara2003@yahoo.de
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
-- <<-- more -->>
-- Title: Program Counter Logic
-- Path: R6502_TC/Reg_PC/struct
-- Edited: by eda on 01 Jan 2009
--
-- VHDL Architecture R6502_TC.Reg_PC.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 22:42:52 04.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
architecture struct of Reg_PC is
 
-- Architecture declarations
 
-- Internal signal declarations
signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
signal adr_pc_low_o_i : std_logic_vector(7 downto 0);
signal adr_pc_o_i : std_logic_vector(15 downto 0);
signal as_n_o_i : std_logic;
signal ci_o_i : std_logic;
signal cout_pc_o_i : std_logic;
signal load3_o_i : std_logic;
signal load_o_i : std_logic;
signal offset_high_o_i : std_logic_vector(7 downto 0);
signal offset_low_o_i : std_logic_vector(7 downto 0);
signal val_o_i : std_logic_vector(7 downto 0);
signal val_one : std_logic_vector(7 downto 0);
signal val_zero : std_logic_vector(7 downto 0);
 
-- Implicit buffer signal declarations
signal adr_pc_o_internal : std_logic_vector (15 downto 0);
signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
 
 
-- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub'
signal mw_U_11temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_11temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_11sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_12' of 'addsub'
signal mw_U_12temp_din0 : std_logic_vector(8 downto 0);
signal mw_U_12temp_din1 : std_logic_vector(8 downto 0);
signal mw_U_12sum : unsigned(8 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
 
-- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
 
 
begin
 
-- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
mw_U_11temp_din0 <= '0' & adr_pc_low_o_i;
mw_U_11temp_din1 <= '0' & val_o_i;
u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, as_n_o_i)
variable temp_carry : std_logic;
begin
temp_carry := '0';
if (as_n_o_i = '1') then
mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry;
else
mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry;
end if;
end process u_11combo_proc;
adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8);
cout_pc_o_i <= mw_U_11sum(8);
 
-- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
mw_U_12temp_din0 <= '0' & adr_pc_high_o_i;
mw_U_12temp_din1 <= '0' & offset_high_o_i;
u_12combo_proc: process (mw_U_12temp_din0, mw_U_12temp_din1, as_n_o_i, ci_o_i)
variable temp_carry : std_logic;
begin
temp_carry := ci_o_i;
if (as_n_o_i = '1') then
mw_U_12sum <= unsigned(mw_U_12temp_din0) + unsigned(mw_U_12temp_din1) + temp_carry;
else
mw_U_12sum <= unsigned(mw_U_12temp_din0) - unsigned(mw_U_12temp_din1) - temp_carry;
end if;
end process u_12combo_proc;
adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(mw_U_12sum(7 downto 0),8);
 
-- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
end if;
end if;
end process u_0seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_4reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load3_o_i = '1') then
mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
end if;
end if;
end process u_4seq_proc;
 
-- ModuleWare code(v1.9) for instance 'U_6' of 'and'
load_o_i <= ld_pc_i and ld_i(0);
 
-- ModuleWare code(v1.9) for instance 'U_7' of 'and'
load3_o_i <= ld_pc_i and ld_i(1);
 
-- ModuleWare code(v1.9) for instance 'U_10' of 'and'
ci_o_i <= cout_pc_o_i and ld_pc_i;
 
-- ModuleWare code(v1.9) for instance 'U_1' of 'constval'
val_zero <= "00000000";
 
-- ModuleWare code(v1.9) for instance 'U_9' of 'constval'
val_one <= "00000001";
 
-- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
as_n_o_i <= not(sel_pc_as_i);
 
-- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
begin
case sel_pc_in_i is
when '0' => adr_pc_o_i <= adr_pc_o_internal;
when '1' => adr_pc_o_i <= adr_i;
when others => adr_pc_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_13' of 'mux'
u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
sel_pc_val_i)
begin
case sel_pc_val_i is
when "00" => val_o_i <= val_one;
when "01" => val_o_i <= val_zero;
when "10" => val_o_i <= offset_low_o_i;
when "11" => val_o_i <= val_zero;
when others => val_o_i <= (others => 'X');
end case;
end process u_13combo_proc;
 
-- ModuleWare code(v1.9) for instance 'U_3' of 'split'
adr_pc_low_o_i <= adr_pc_o_i(7 downto 0);
adr_pc_high_o_i <= adr_pc_o_i(15 downto 8);
 
-- ModuleWare code(v1.9) for instance 'U_5' of 'split'
offset_low_o_i <= offset_i(7 downto 0);
offset_high_o_i <= offset_i(15 downto 8);
 
-- Instance port mappings.
 
-- Implicit buffered output assignments
adr_pc_o <= adr_pc_o_internal;
adr_nxt_pc_o <= adr_nxt_pc_o_internal;
 
end struct;
vhdl/reg_pc.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/reg_sp.vhd =================================================================== --- vhdl/reg_sp.vhd (nonexistent) +++ vhdl/reg_sp.vhd (revision 18) @@ -0,0 +1,147 @@ +-- VHDL Entity R6502_TC.Reg_SP.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:53 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity Reg_SP is + port( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic; + ld_low_i : in std_logic; + ld_sp_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_sp_as_i : in std_logic; + sel_sp_in_i : in std_logic; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + +-- Declarations + +end Reg_SP ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- <<-- more -->> +-- Title: Stack Pointer Logic +-- Path: R6502_TC/Reg_SP/struct +-- Edited: by eda on 01 Jan 2009 +-- +-- VHDL Architecture R6502_TC.Reg_SP.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:53 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of Reg_SP is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_sp_low_o_i : std_logic_vector(7 downto 0); + signal load_o_i : std_logic; + signal result_low1_o_i : std_logic_vector(7 downto 0); + signal result_low_o_i : std_logic_vector(7 downto 0); + signal sp_as_n_o_i : std_logic; + signal val_one : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal adr_sp_o_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'addsub' + signal mw_U_11temp_din0 : std_logic_vector(8 downto 0); + signal mw_U_11temp_din1 : std_logic_vector(8 downto 0); + signal mw_U_11sum : unsigned(8 downto 0); + + -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub' + mw_U_11temp_din0 <= '0' & adr_sp_low_o_i; + mw_U_11temp_din1 <= '0' & val_one; + u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1, sp_as_n_o_i) + variable temp_carry : std_logic; + begin + temp_carry := '0'; + if (sp_as_n_o_i = '1') then + mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; + else + mw_U_11sum <= unsigned(mw_U_11temp_din0) - unsigned(mw_U_11temp_din1) - temp_carry; + end if; + end process u_11combo_proc; + result_low_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); + + -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' + adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= result_low1_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.9) for instance 'U_6' of 'and' + load_o_i <= ld_sp_i and ld_low_i; + + -- ModuleWare code(v1.9) for instance 'U_3' of 'buff' + adr_sp_o_internal(15 DOWNTO 8) <= val_one; + + -- ModuleWare code(v1.9) for instance 'U_4' of 'constval' + val_one <= "00000001"; + + -- ModuleWare code(v1.9) for instance 'U_2' of 'inv' + sp_as_n_o_i <= not(sel_sp_as_i); + + -- ModuleWare code(v1.9) for instance 'U_8' of 'mux' + u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) + begin + case sel_sp_in_i is + when '0' => result_low1_o_i <= result_low_o_i; + when '1' => result_low1_o_i <= adr_low_i; + when others => result_low1_o_i <= (others => 'X'); + end case; + end process u_8combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_10' of 'tap' + adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); + + -- Instance port mappings. + + -- Implicit buffered output assignments + adr_sp_o <= adr_sp_o_internal; + +end struct;
vhdl/reg_sp.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/r6502_tc.vhd =================================================================== --- vhdl/r6502_tc.vhd (nonexistent) +++ vhdl/r6502_tc.vhd (revision 18) @@ -0,0 +1,119 @@ +-- VHDL Entity R6502_TC.R6502_TC.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:06 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity R6502_TC is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end R6502_TC ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- <<-- more -->> +-- Title: Top Level +-- Path: R6502_TC/R6502_TC/struct +-- Edited: by eda on 04 Jan 2009 +-- +-- VHDL Architecture R6502_TC.R6502_TC.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:06 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +library R6502_TC; + +architecture struct of R6502_TC is + + -- Architecture declarations + + -- Internal signal declarations + + + -- Component Declarations + component Core + port ( + clk_clk_i : in std_logic ; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic ; + nmi_n_i : in std_logic ; + rdy_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : Core use entity R6502_TC.Core; + -- pragma synthesis_on + + +begin + + -- Instance port mappings. + U_0 : Core + port map ( + clk_clk_i => clk_clk_i, + d_i => d_i, + irq_n_i => irq_n_i, + nmi_n_i => nmi_n_i, + rdy_i => rdy_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + d_o => d_o, + rd_o => rd_o, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + +end struct;
vhdl/r6502_tc.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/fsm_execution_unit.vhd =================================================================== --- vhdl/fsm_execution_unit.vhd (nonexistent) +++ vhdl/fsm_execution_unit.vhd (revision 18) @@ -0,0 +1,5061 @@ +-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:53 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity FSM_Execution_Unit is + port( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic; + nmi_i : in std_logic; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic; + reg_0flag_i : in std_logic; + reg_1flag_i : in std_logic; + reg_7flag_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + fetch_o : out std_logic; + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic; + ld_sp_o : out std_logic; + load_regs_o : out std_logic; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic; + sel_pc_as_o : out std_logic; + sel_pc_in_o : out std_logic; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic; + sel_sp_in_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end FSM_Execution_Unit ; + +-- Jens-D. Gutschmidt Project: R6502_TC + +-- scantara2003@yahoo.de + +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG + +-- + +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by + +-- the Free Software Foundation, either version 3 of the License, or any later version. + +-- + +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +-- + +-- You should have received a copy of the GNU General Public License along with this program. If not, see . + +-- + +-- CVS Revisins History + +-- + +-- $Log: not supported by cvs2svn $ + +-- <<-- more -->> + +-- Title: FSM Execution Unit for all op codes + +-- Path: R6502_TC/FSM_Execution_Unit/fsm + +-- Edited: by eda on 04 Jan 2009 + +-- +-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:55 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of FSM_Execution_Unit is + + -- Architecture Declarations + signal reg_F : std_logic_vector( 7 DOWNTO 0 ); + signal reg_PC : std_logic_vector(15 DOWNTO 0); + signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); + signal reg_sel_pc_as : std_logic; + signal reg_sel_pc_in : std_logic; + signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); + signal reg_sel_sp_as : std_logic; + signal reg_sel_sp_in : std_logic; + signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); + signal sig_PC : std_logic_vector(15 DOWNTO 0); + signal sig_RD : std_logic; + signal sig_RWn : std_logic; + signal sig_SYNC : std_logic; + signal sig_WR : std_logic; + signal zw_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); + signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_REG_NMI : std_logic; + signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); + signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); + signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_so : std_logic; + signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); + + subtype state_type is + std_logic_vector(7 downto 0); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Hard encoding + constant FETCH : state_type := "00000000"; + constant s1 : state_type := "00000001"; + constant s2 : state_type := "00000011"; + constant s5 : state_type := "00000010"; + constant s3 : state_type := "00000110"; + constant s4 : state_type := "00000111"; + constant s12 : state_type := "00000101"; + constant s16 : state_type := "00000100"; + constant s17 : state_type := "00001100"; + constant s24 : state_type := "00001101"; + constant s25 : state_type := "00001111"; + constant s271 : state_type := "00001110"; + constant s273 : state_type := "00001010"; + constant s304 : state_type := "00001011"; + constant s307 : state_type := "00001001"; + constant s177 : state_type := "00001000"; + constant s180 : state_type := "00011000"; + constant s181 : state_type := "00011001"; + constant s182 : state_type := "00011011"; + constant s183 : state_type := "00011010"; + constant s184 : state_type := "00011110"; + constant s185 : state_type := "00011111"; + constant s186 : state_type := "00011101"; + constant s187 : state_type := "00011100"; + constant s188 : state_type := "00010100"; + constant s189 : state_type := "00010101"; + constant s190 : state_type := "00010111"; + constant s191 : state_type := "00010110"; + constant s192 : state_type := "00010010"; + constant s193 : state_type := "00010011"; + constant s377 : state_type := "00010001"; + constant s381 : state_type := "00010000"; + constant s378 : state_type := "00110000"; + constant s382 : state_type := "00110001"; + constant s379 : state_type := "00110011"; + constant s383 : state_type := "00110010"; + constant s384 : state_type := "00110110"; + constant s380 : state_type := "00110111"; + constant s385 : state_type := "00110101"; + constant s386 : state_type := "00110100"; + constant s387 : state_type := "00111100"; + constant s388 : state_type := "00111101"; + constant s389 : state_type := "00111111"; + constant s391 : state_type := "00111110"; + constant s392 : state_type := "00111010"; + constant s390 : state_type := "00111011"; + constant s393 : state_type := "00111001"; + constant s394 : state_type := "00111000"; + constant s395 : state_type := "00101000"; + constant s396 : state_type := "00101001"; + constant s397 : state_type := "00101011"; + constant s398 : state_type := "00101010"; + constant s399 : state_type := "00101110"; + constant s400 : state_type := "00101111"; + constant s401 : state_type := "00101101"; + constant s526 : state_type := "00101100"; + constant s527 : state_type := "00100100"; + constant s528 : state_type := "00100101"; + constant s529 : state_type := "00100111"; + constant s530 : state_type := "00100110"; + constant s531 : state_type := "00100010"; + constant s544 : state_type := "00100011"; + constant s545 : state_type := "00100001"; + constant s546 : state_type := "00100000"; + constant s547 : state_type := "01100000"; + constant s549 : state_type := "01100001"; + constant s550 : state_type := "01100011"; + constant s404 : state_type := "01100010"; + constant s556 : state_type := "01100110"; + constant s557 : state_type := "01100111"; + constant s579 : state_type := "01100101"; + constant s201 : state_type := "01100100"; + constant s202 : state_type := "01101100"; + constant s210 : state_type := "01101101"; + constant s211 : state_type := "01101111"; + constant s215 : state_type := "01101110"; + constant s217 : state_type := "01101010"; + constant s218 : state_type := "01101011"; + constant s222 : state_type := "01101001"; + constant s223 : state_type := "01101000"; + constant s224 : state_type := "01111000"; + constant s225 : state_type := "01111001"; + constant s226 : state_type := "01111011"; + constant s243 : state_type := "01111010"; + constant s244 : state_type := "01111110"; + constant s247 : state_type := "01111111"; + constant s344 : state_type := "01111101"; + constant s343 : state_type := "01111100"; + constant s250 : state_type := "01110100"; + constant s251 : state_type := "01110101"; + constant s351 : state_type := "01110111"; + constant s361 : state_type := "01110110"; + constant s360 : state_type := "01110010"; + constant s403 : state_type := "01110011"; + constant s406 : state_type := "01110001"; + constant s407 : state_type := "01110000"; + constant s409 : state_type := "01010000"; + constant s412 : state_type := "01010001"; + constant s413 : state_type := "01010011"; + constant s416 : state_type := "01010010"; + constant s418 : state_type := "01010110"; + constant s510 : state_type := "01010111"; + constant s553 : state_type := "01010101"; + constant s555 : state_type := "01010100"; + constant s558 : state_type := "01011100"; + constant s560 : state_type := "01011101"; + constant s561 : state_type := "01011111"; + constant s563 : state_type := "01011110"; + constant s564 : state_type := "01011010"; + constant s565 : state_type := "01011011"; + constant s566 : state_type := "01011001"; + constant s266 : state_type := "01011000"; + constant s301 : state_type := "01001000"; + constant s302 : state_type := "01001001"; + constant RES : state_type := "01001011"; + constant s511 : state_type := "01001010"; + constant s559 : state_type := "01001110"; + constant s562 : state_type := "01001111"; + constant s567 : state_type := "01001101"; + constant s568 : state_type := "01001100"; + constant s569 : state_type := "01000100"; + constant s570 : state_type := "01000101"; + constant s571 : state_type := "01000111"; + constant s572 : state_type := "01000110"; + constant s573 : state_type := "01000010"; + constant s574 : state_type := "01000011"; + constant s548 : state_type := "01000001"; + constant s551 : state_type := "01000000"; + constant s552 : state_type := "11000000"; + constant s575 : state_type := "11000001"; + constant s576 : state_type := "11000011"; + constant s577 : state_type := "11000010"; + constant s532 : state_type := "11000110"; + constant s533 : state_type := "11000111"; + constant s534 : state_type := "11000101"; + constant s535 : state_type := "11000100"; + constant s536 : state_type := "11001100"; + constant s537 : state_type := "11001101"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal d_o_cld : std_logic_vector ( 7 downto 0 ); + signal rd_o_cld : std_logic ; + signal sync_o_cld : std_logic ; + signal wr_n_o_cld : std_logic ; + signal wr_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= RES; + -- Default Reset Values + d_o_cld <= X"00"; + rd_o_cld <= '0'; + sync_o_cld <= '0'; + wr_n_o_cld <= '1'; + wr_o_cld <= '0'; + reg_F <= "00000100"; + reg_PC <= X"0000"; + reg_PC1 <= X"0000"; + reg_sel_pc_as <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_rb_in <= "00"; + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_sp_as <= '0'; + reg_sel_sp_in <= '0'; + sig_PC <= X"0000"; + zw_PC <= X"0000"; + zw_REG_ALU <= '0' & X"00"; + zw_REG_NMI <= '0'; + zw_REG_OP <= X"00"; + zw_REG_sig_PC <= X"0000"; + zw_b1 <= X"00"; + zw_b2 <= X"00"; + zw_b3 <= X"00"; + zw_b4 <= X"00"; + zw_so <= '0'; + zw_w1 <= X"0000"; + zw_w2 <= X"0000"; + zw_w3 <= X"0000"; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); + reg_PC <= reg_PC; + reg_PC1 <= reg_PC1; + reg_sel_pc_as <= reg_sel_pc_as; + reg_sel_pc_in <= reg_sel_pc_in; + reg_sel_pc_val <= reg_sel_pc_val; + reg_sel_rb_in <= reg_sel_rb_in; + reg_sel_rb_out <= reg_sel_rb_out; + reg_sel_reg <= reg_sel_reg; + reg_sel_sp_as <= reg_sel_sp_as; + reg_sel_sp_in <= reg_sel_sp_in; + sig_PC <= sig_PC; + zw_PC <= zw_PC; + zw_REG_ALU <= zw_REG_ALU; + zw_REG_NMI <= zw_REG_NMI or nmi_i; + zw_REG_OP <= zw_REG_OP; + zw_REG_sig_PC <= zw_REG_sig_PC; + zw_b1 <= zw_b1; + zw_b2 <= zw_b2; + zw_b3 <= zw_b3; + zw_b4 <= zw_b4; + zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); + zw_w1 <= zw_w1; + zw_w2 <= zw_w2; + zw_w3 <= zw_w3; + d_o_cld <= sig_D_OUT; + rd_o_cld <= sig_RD; + sync_o_cld <= sig_SYNC; + wr_n_o_cld <= sig_RWn; + wr_o_cld <= sig_WR; + + -- Combined Actions + case current_state is + when FETCH => + zw_REG_OP <= d_i; + if ((nmi_i = '1') and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + zw_REG_NMI <= '0'; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + zw_b1(0) <= reg_F(7); + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + zw_b3 <= adr_nxt_pc_i (15 downto 8); + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"00") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"18") and (rdy_i = '1')) then + elsif ((d_i = X"D8") and (rdy_i = '1')) then + elsif ((d_i = X"58") and (rdy_i = '1')) then + elsif ((d_i = X"B8") and (rdy_i = '1')) then + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + zw_b4 <= X"FF"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"FF"; + elsif ((d_i = X"88") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"FF"; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + zw_b4 <= X"01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"01"; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + zw_b4 <= X"01"; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"20") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + reg_sel_reg <= "10"; + reg_sel_rb_in <= "11"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + elsif ((d_i = X"48") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"08") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"68") and (rdy_i = '1')) then + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"28") and (rdy_i = '1')) then + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"40") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"60") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + zw_b1(0) <= reg_F(7); + elsif ((d_i = X"38") and (rdy_i = '1')) then + elsif ((d_i = X"F8") and (rdy_i = '1')) then + elsif ((d_i = X"78") and (rdy_i = '1')) then + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "00"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "11"; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + reg_sel_rb_out <= "00"; + reg_sel_reg <= "10"; + reg_sel_rb_in <= "00"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"98") and (rdy_i = '1')) then + reg_sel_rb_out <= "10"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "01"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "01"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "00"; + reg_sel_rb_in <= "10"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + reg_sel_rb_out <= "01"; + reg_sel_reg <= "11"; + reg_sel_rb_in <= "11"; + reg_sel_sp_in <= '1'; + reg_sel_sp_as <= '0'; + end if; + when s1 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s2 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s5 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s3 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s4 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s12 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s16 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s17 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s24 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(6) <= '0'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s25 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s271 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + zw_b1 <= d_i; + end if; + when s273 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + zw_b2 <= d_i; + end if; + when s304 => + if (rdy_i = '1') then + sig_PC <= zw_b2 & adr_pc_i(7 downto 0); + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + zw_b1 <= d_i; + end if; + when s307 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s177 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s180 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s181 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s182 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s183 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s184 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s185 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s186 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s187 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s188 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s189 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s190 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s191 => + sig_PC <= zw_b3 & zw_b1; + when s192 => + sig_PC <= d_i & zw_b1; + when s193 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s377 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s381 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s378 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s382 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s383 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s384 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s385 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s386 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F <= d_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s387 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s388 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s389 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + reg_F <= d_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + end if; + when s391 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end if; + when s392 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s390 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s393 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s394 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + end if; + when s395 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s396 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s397 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end if; + when s399 => + sig_PC <= adr_sp_i; + when s400 => + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + when s401 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1 (7 downto 0); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s526 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s527 => + sig_PC <= adr_sp_i; + when s528 => + sig_PC <= adr_sp_i; + when s529 => + sig_PC <= X"FFFE"; + when s530 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_F(2) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s531 => + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + zw_b1 <= d_i; + end if; + when s544 => + sig_PC <= adr_sp_i; + when s545 => + sig_PC <= adr_sp_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + when s546 => + sig_PC <= adr_pc_i; + when s547 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + zw_w1 (7 downto 0) <= d_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + end if; + when s549 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_w1 (7 downto 0); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s550 => + sig_PC <= adr_sp_i; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + when s404 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s556 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s557 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s579 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s201 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + sig_PC <= X"00" & d_i; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s202 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s210 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s211 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s215 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s217 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s218 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s222 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s223 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s224 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s225 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s226 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s243 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s244 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s247 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s344 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s343 => + if (rdy_i = '1') then + zw_b1 <= d_alu_i; + end if; + when s251 => + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s351 => + if (rdy_i = '1' and + zw_REG_OP = X"24") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end if; + when s361 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= d_i(7); + reg_F(6) <= d_i(6); + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s360 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s403 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end if; + when s406 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s407 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s409 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s412 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s416 => + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + zw_b1 <= d_i(6 downto 0) & '0'; + zw_b2(0) <= d_i(7); + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + zw_b1 <= '0' & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + zw_b1 <= d_i(6 downto 0) & reg_F(0); + zw_b2(0) <= d_i(7); + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + zw_b1 <= reg_F(0) & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + end if; + when s418 => + sig_PC <= adr_pc_i; + reg_F(0) <= zw_b2(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s510 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s553 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s555 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s558 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s560 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s561 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s563 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s564 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s565 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s566 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s266 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "10"; + zw_b2 <= d_i; + end if; + when s301 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); + end if; + when s302 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when RES => + reg_sel_pc_in <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_pc_as <= '0'; + sig_PC <= adr_nxt_pc_i; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + when s511 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s559 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s562 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s567 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s568 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s569 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s570 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s571 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s572 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s573 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s574 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s548 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s551 => + sig_PC <= adr_sp_i; + when s552 => + sig_PC <= adr_sp_i; + when s575 => + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + zw_b1 <= d_i; + end if; + when s576 => + sig_PC <= X"FFFE"; + when s577 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_F(2) <= '1'; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when s532 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s533 => + sig_PC <= adr_sp_i; + when s534 => + sig_PC <= adr_sp_i; + when s535 => + if (rdy_i = '1') then + sig_PC <= X"FFFB"; + reg_sel_pc_in <= '1'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "11"; + zw_b1 <= d_i; + end if; + when s536 => + sig_PC <= X"FFFA"; + when s537 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_sel_pc_in <= '0'; + reg_sel_pc_as <= '0'; + reg_sel_pc_val <= "00"; + reg_sel_sp_in <= '0'; + reg_sel_sp_as <= '1'; + end if; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + adr_nxt_pc_i, + current_state, + d_i, + irq_n_i, + nmi_i, + rdy_i, + reg_F, + zw_REG_OP, + zw_b2, + zw_b3 + ) + ----------------------------------------------------------------- + begin + case current_state is + when FETCH => + if ((nmi_i = '1') and (rdy_i = '1')) then + next_state <= s532; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + next_state <= s548; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + next_state <= s510; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + next_state <= s266; + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + next_state <= s351; + elsif ((d_i = X"00") and (rdy_i = '1')) then + next_state <= s526; + elsif ((d_i = X"18") and (rdy_i = '1')) then + next_state <= s12; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + next_state <= s16; + elsif ((d_i = X"58") and (rdy_i = '1')) then + next_state <= s17; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + next_state <= s24; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + next_state <= s226; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"88") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + next_state <= s226; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + next_state <= s271; + elsif ((d_i = X"20") and (rdy_i = '1')) then + next_state <= s397; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + next_state <= s1; + elsif ((d_i = X"48") and (rdy_i = '1')) then + next_state <= s377; + elsif ((d_i = X"08") and (rdy_i = '1')) then + next_state <= s378; + elsif ((d_i = X"68") and (rdy_i = '1')) then + next_state <= s379; + elsif ((d_i = X"28") and (rdy_i = '1')) then + next_state <= s380; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"40") and (rdy_i = '1')) then + next_state <= s387; + elsif ((d_i = X"60") and (rdy_i = '1')) then + next_state <= s390; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + next_state <= s511; + elsif ((d_i = X"38") and (rdy_i = '1')) then + next_state <= s2; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + next_state <= s5; + elsif ((d_i = X"78") and (rdy_i = '1')) then + next_state <= s3; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + next_state <= s404; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + next_state <= s556; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + next_state <= s557; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + next_state <= s579; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"98") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + next_state <= s4; + elsif (rdy_i = '1') then + next_state <= s1; + else + next_state <= FETCH; + end if; + when s1 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s1; + end if; + when s2 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s2; + end if; + when s5 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s5; + end if; + when s3 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s3; + end if; + when s4 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s4; + end if; + when s12 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s12; + end if; + when s16 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s16; + end if; + when s17 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s17; + end if; + when s24 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s24; + end if; + when s25 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s25; + end if; + when s271 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + next_state <= s307; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + next_state <= s273; + else + next_state <= s271; + end if; + when s273 => + if (rdy_i = '1') then + next_state <= s304; + else + next_state <= s273; + end if; + when s304 => + if (rdy_i = '1') then + next_state <= s307; + else + next_state <= s304; + end if; + when s307 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s307; + end if; + when s177 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + next_state <= s184; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + next_state <= s185; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + next_state <= s183; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + next_state <= s182; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + next_state <= s180; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + next_state <= s181; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + next_state <= s186; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + next_state <= s185; + else + next_state <= s177; + end if; + when s180 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s180; + end if; + when s181 => + if (rdy_i = '1') then + next_state <= s189; + else + next_state <= s181; + end if; + when s182 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s182; + end if; + when s183 => + if (rdy_i = '1') then + next_state <= s187; + else + next_state <= s183; + end if; + when s184 => + next_state <= FETCH; + when s185 => + if (rdy_i = '1') then + next_state <= s190; + else + next_state <= s185; + end if; + when s186 => + if (rdy_i = '1') then + next_state <= s188; + else + next_state <= s186; + end if; + when s187 => + next_state <= FETCH; + when s188 => + if (rdy_i = '1') then + next_state <= s192; + else + next_state <= s188; + end if; + when s189 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s189; + end if; + when s190 => + next_state <= FETCH; + when s191 => + next_state <= s193; + when s192 => + next_state <= s193; + when s193 => + next_state <= FETCH; + when s377 => + if (rdy_i = '1') then + next_state <= s381; + else + next_state <= s377; + end if; + when s381 => + next_state <= FETCH; + when s378 => + if (rdy_i = '1') then + next_state <= s382; + else + next_state <= s378; + end if; + when s382 => + next_state <= FETCH; + when s379 => + if (rdy_i = '1') then + next_state <= s383; + else + next_state <= s379; + end if; + when s383 => + if (rdy_i = '1') then + next_state <= s384; + else + next_state <= s383; + end if; + when s384 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s384; + end if; + when s380 => + if (rdy_i = '1') then + next_state <= s385; + else + next_state <= s380; + end if; + when s385 => + if (rdy_i = '1') then + next_state <= s386; + else + next_state <= s385; + end if; + when s386 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s386; + end if; + when s387 => + if (rdy_i = '1') then + next_state <= s388; + else + next_state <= s387; + end if; + when s388 => + if (rdy_i = '1') then + next_state <= s389; + else + next_state <= s388; + end if; + when s389 => + if (rdy_i = '1') then + next_state <= s391; + else + next_state <= s389; + end if; + when s391 => + if (rdy_i = '1') then + next_state <= s392; + else + next_state <= s391; + end if; + when s392 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s392; + end if; + when s390 => + if (rdy_i = '1') then + next_state <= s393; + else + next_state <= s390; + end if; + when s393 => + if (rdy_i = '1') then + next_state <= s394; + else + next_state <= s393; + end if; + when s394 => + if (rdy_i = '1') then + next_state <= s395; + else + next_state <= s394; + end if; + when s395 => + if (rdy_i = '1') then + next_state <= s396; + else + next_state <= s395; + end if; + when s396 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s396; + end if; + when s397 => + if (rdy_i = '1') then + next_state <= s398; + else + next_state <= s397; + end if; + when s398 => + if (rdy_i = '1') then + next_state <= s399; + else + next_state <= s398; + end if; + when s399 => + next_state <= s400; + when s400 => + next_state <= s401; + when s401 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s401; + end if; + when s526 => + if (rdy_i = '1') then + next_state <= s527; + else + next_state <= s526; + end if; + when s527 => + next_state <= s528; + when s528 => + next_state <= s529; + when s529 => + next_state <= s531; + when s530 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s530; + end if; + when s531 => + if (rdy_i = '1') then + next_state <= s530; + else + next_state <= s531; + end if; + when s544 => + next_state <= s550; + when s545 => + next_state <= s546; + when s546 => + next_state <= s547; + when s547 => + if (rdy_i = '1') then + next_state <= s549; + else + next_state <= s547; + end if; + when s549 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s549; + end if; + when s550 => + next_state <= s545; + when s404 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s404; + end if; + when s556 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s556; + end if; + when s557 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s557; + end if; + when s579 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s579; + end if; + when s201 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + next_state <= s224; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + next_state <= s217; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + next_state <= s202; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + next_state <= s210; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + next_state <= s211; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + next_state <= s215; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + next_state <= s218; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + next_state <= s217; + else + next_state <= s201; + end if; + when s202 => + if (rdy_i = '1') then + next_state <= s224; + else + next_state <= s202; + end if; + when s210 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s210; + end if; + when s211 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s211; + end if; + when s215 => + if (rdy_i = '1') then + next_state <= s223; + else + next_state <= s215; + end if; + when s217 => + if (rdy_i = '1') then + next_state <= s224; + else + next_state <= s217; + end if; + when s218 => + if (rdy_i = '1') then + next_state <= s222; + else + next_state <= s218; + end if; + when s222 => + if (rdy_i = '1') then + next_state <= s202; + else + next_state <= s222; + end if; + when s223 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s223; + end if; + when s224 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s224; + end if; + when s225 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s224; + else + next_state <= s225; + end if; + when s226 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + next_state <= s343; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + next_state <= s247; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + next_state <= s243; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + next_state <= s244; + else + next_state <= s226; + end if; + when s243 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s243; + end if; + when s244 => + if (rdy_i = '1') then + next_state <= s344; + else + next_state <= s244; + end if; + when s247 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s247; + end if; + when s344 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s344; + end if; + when s343 => + if (rdy_i = '1') then + next_state <= s250; + else + next_state <= s343; + end if; + when s250 => + if (rdy_i = '1') then + next_state <= s251; + else + next_state <= s250; + end if; + when s251 => + next_state <= FETCH; + when s351 => + if (rdy_i = '1' and + zw_REG_OP = X"24") then + next_state <= s361; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + next_state <= s360; + else + next_state <= s351; + end if; + when s361 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s361; + end if; + when s360 => + if (rdy_i = '1') then + next_state <= s361; + else + next_state <= s360; + end if; + when s403 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + next_state <= s407; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + next_state <= s413; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + next_state <= s409; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + next_state <= s406; + else + next_state <= s403; + end if; + when s406 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s406; + end if; + when s407 => + if (rdy_i = '1') then + next_state <= s412; + else + next_state <= s407; + end if; + when s409 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s409; + end if; + when s412 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s412; + end if; + when s413 => + if (rdy_i = '1') then + next_state <= s416; + else + next_state <= s413; + end if; + when s416 => + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + next_state <= s418; + else + next_state <= s416; + end if; + when s418 => + next_state <= FETCH; + when s510 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + next_state <= s565; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + next_state <= s560; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + next_state <= s553; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + next_state <= s555; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + next_state <= s555; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + next_state <= s558; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + next_state <= s561; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s510; + end if; + when s553 => + if (rdy_i = '1') then + next_state <= s565; + else + next_state <= s553; + end if; + when s555 => + if (rdy_i = '1') then + next_state <= s564; + else + next_state <= s555; + end if; + when s558 => + if (rdy_i = '1') then + next_state <= s566; + else + next_state <= s558; + end if; + when s560 => + if (rdy_i = '1') then + next_state <= s565; + else + next_state <= s560; + end if; + when s561 => + if (rdy_i = '1') then + next_state <= s563; + else + next_state <= s561; + end if; + when s563 => + if (rdy_i = '1') then + next_state <= s553; + else + next_state <= s563; + end if; + when s564 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s565; + else + next_state <= s564; + end if; + when s565 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s565; + end if; + when s566 => + if (rdy_i = '1') then + next_state <= s564; + else + next_state <= s566; + end if; + when s266 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s301; + else + next_state <= s266; + end if; + when s301 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s302; + else + next_state <= s301; + end if; + when s302 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s302; + end if; + when RES => + next_state <= s544; + when s511 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + next_state <= s574; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + next_state <= s569; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + next_state <= s559; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + next_state <= s562; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + next_state <= s567; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + next_state <= s568; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + next_state <= s570; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s511; + end if; + when s559 => + if (rdy_i = '1') then + next_state <= s574; + else + next_state <= s559; + end if; + when s562 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s562; + end if; + when s567 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s567; + end if; + when s568 => + if (rdy_i = '1') then + next_state <= s571; + else + next_state <= s568; + end if; + when s569 => + if (rdy_i = '1') then + next_state <= s574; + else + next_state <= s569; + end if; + when s570 => + if (rdy_i = '1') then + next_state <= s572; + else + next_state <= s570; + end if; + when s571 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s571; + end if; + when s572 => + if (rdy_i = '1') then + next_state <= s559; + else + next_state <= s572; + end if; + when s573 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s574; + else + next_state <= s573; + end if; + when s574 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s574; + end if; + when s548 => + if (rdy_i = '1') then + next_state <= s551; + else + next_state <= s548; + end if; + when s551 => + next_state <= s552; + when s552 => + next_state <= s576; + when s575 => + if (rdy_i = '1') then + next_state <= s577; + else + next_state <= s575; + end if; + when s576 => + next_state <= s575; + when s577 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s577; + end if; + when s532 => + if (rdy_i = '1') then + next_state <= s533; + else + next_state <= s532; + end if; + when s533 => + next_state <= s534; + when s534 => + next_state <= s536; + when s535 => + if (rdy_i = '1') then + next_state <= s537; + else + next_state <= s535; + end if; + when s536 => + next_state <= s535; + when s537 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s537; + end if; + when others => + next_state <= RES; + end case; + end process nextstate_proc; + + ----------------------------------------------------------------- + output_proc : process ( + adr_nxt_pc_i, + adr_pc_i, + adr_sp_i, + current_state, + d_alu_i, + d_i, + d_regs_out_i, + irq_n_i, + nmi_i, + q_a_i, + q_x_i, + q_y_i, + rdy_i, + reg_F, + reg_sel_pc_as, + reg_sel_pc_in, + reg_sel_pc_val, + reg_sel_rb_in, + reg_sel_rb_out, + reg_sel_reg, + reg_sel_sp_as, + reg_sel_sp_in, + sig_PC, + zw_ALU, + zw_ALU1, + zw_ALU2, + zw_ALU3, + zw_ALU4, + zw_ALU5, + zw_ALU6, + zw_REG_OP, + zw_b1, + zw_b2, + zw_b3, + zw_b4, + zw_w1 + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + a_o <= sig_PC; + adr_o <= X"0000"; + ch_a_o <= X"00"; + ch_b_o <= X"00"; + d_regs_in_o <= X"00"; + fetch_o <= '0'; + ld_o <= "00"; + ld_pc_o <= '0'; + ld_sp_o <= '0'; + load_regs_o <= '0'; + offset_o <= X"0000"; + sel_pc_as_o <= reg_sel_pc_as; + sel_pc_in_o <= reg_sel_pc_in; + sel_pc_val_o <= reg_sel_pc_val; + sel_rb_in_o <= reg_sel_rb_in; + sel_rb_out_o <= reg_sel_rb_out; + sel_reg_o <= reg_sel_reg; + sel_sp_as_o <= reg_sel_sp_as; + sel_sp_in_o <= reg_sel_sp_in; + -- Default Assignment To Internals + sig_D_OUT <= X"00"; + sig_RD <= '1'; + sig_RWn <= '1'; + sig_SYNC <= '0'; + sig_WR <= '0'; + zw_ALU <= '0' & X"00"; + zw_ALU1 <= '0' & X"00"; + zw_ALU2 <= '0' & X"00"; + zw_ALU3 <= '0' & X"00"; + zw_ALU4 <= '0' & X"00"; + zw_ALU5 <= '0' & X"00"; + zw_ALU6 <= '0' & X"00"; + + -- Combined Actions + case current_state is + when FETCH => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= NOT (rdy_i); + if ((nmi_i = '1') and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"00") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"18") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"58") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"88") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"20") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"48") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"08") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"68") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"28") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"40") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"60") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"38") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"78") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"98") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s1 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s2 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s5 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s3 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s4 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + adr_o <= X"01" & d_regs_out_i; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + d_regs_in_o <= adr_sp_i (7 downto 0); + ch_a_o <= adr_sp_i (7 downto 0); + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1') then + ch_a_o <= d_regs_out_i; + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s12 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s16 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s17 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s24 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s25 => + if (rdy_i = '1') then + d_regs_in_o <= d_alu_i; + ch_a_o <= d_regs_out_i; + ch_b_o <= zw_b4; + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s273 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s307 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s177 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s180 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s181 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s182 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s183 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s184 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s185 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s187 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s188 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s189 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s190 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s191 => + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + when s192 => + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + when s193 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s377 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= q_a_i; + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s381 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s378 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s382 => + sig_SYNC <= '1'; + fetch_o <= '1'; + when s379 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s384 => + if (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s380 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s386 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s387 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s388 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s389 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s392 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s390 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s393 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s395 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s396 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s397 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + end if; + when s398 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s399 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s401 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s526 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s527 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s528 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F OR X"10"; + when s530 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s544 => + ld_o <= "11"; + ld_sp_o <= '1'; + when s545 => + adr_o <= X"FFFB"; + ld_o <= "11"; + ld_pc_o <= '1'; + when s546 => + ld_o <= "11"; + ld_pc_o <= '1'; + when s549 => + if (rdy_i = '1') then + adr_o <= d_i & zw_w1 (7 downto 0); + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s550 => + ld_o <= "11"; + ld_sp_o <= '1'; + when s404 => + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & '0'; + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & '0'; + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s556 => + if (rdy_i = '1') then + ch_a_o <= '0' & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= '0' & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s557 => + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & reg_F(0); + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s579 => + if (rdy_i = '1') then + ch_a_o <= reg_F(0) & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s201 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + ld_o <= "11"; + ld_pc_o <= '1'; + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s202 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s210 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s211 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s215 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s217 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s222 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s223 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s224 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s225 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s226 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end if; + when s243 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s244 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s247 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s343 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= zw_b4; + end if; + when s250 => + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b1; + end if; + when s251 => + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + when s351 => + if (rdy_i = '1' and + zw_REG_OP = X"24") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s361 => + if (rdy_i = '1') then + ch_a_o <= q_a_i AND d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s360 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s403 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s406 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s407 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s409 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s416 => + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + sig_D_OUT <= d_i(6 downto 0) & '0'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + sig_D_OUT <= '0' & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + sig_D_OUT <= d_i(6 downto 0) & reg_F(0); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + sig_D_OUT <= reg_F(0) & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + end if; + when s418 => + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + fetch_o <= '1'; + when s510 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s553 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s555 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s558 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s560 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s563 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s564 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s565 => + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s566 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s266 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s301 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1') then + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s302 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when RES => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_pc_o <= '1'; + + ld_sp_o <= '1'; + sig_RWn <= '1'; + sig_RD <= '1'; + when s511 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s559 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s562 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s567 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s568 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s569 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s571 => + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s572 => + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s573 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s574 => + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s548 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s551 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s552 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + when s577 => + if (rdy_i = '1') then + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when s532 => + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s533 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s534 => + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + when s537 => + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + fetch_o <= '1'; + end if; + when others => + null; + end case; + end process output_proc; + + -- Concurrent Statements + -- Clocked output assignments + d_o <= d_o_cld; + rd_o <= rd_o_cld; + sync_o <= sync_o_cld; + wr_n_o <= wr_n_o_cld; + wr_o <= wr_o_cld; +end fsm; Index: vhdl/core.vhd =================================================================== --- vhdl/core.vhd (nonexistent) +++ vhdl/core.vhd (revision 18) @@ -0,0 +1,341 @@ +-- VHDL Entity R6502_TC.Core.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:05 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity Core is + port( + clk_clk_i : in std_logic; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic; + nmi_n_i : in std_logic; + rdy_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic + ); + +-- Declarations + +end Core ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version +-- 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +-- PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- <<-- more -->> +-- Title: Core +-- Path: R6502_TC/Core/struct +-- Edited: by eda on 04 Jan 2009 +-- +-- VHDL Architecture R6502_TC.Core.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:06 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library R6502_TC; + +architecture struct of Core is + + -- Architecture declarations + + -- Internal signal declarations + signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); + signal adr_o_i : std_logic_vector(15 downto 0); + signal adr_pc_o_i : std_logic_vector(15 downto 0); + signal adr_sp_o_i : std_logic_vector(15 downto 0); + signal ch_a_o_i : std_logic_vector(7 downto 0); + signal ch_b_o_i : std_logic_vector(7 downto 0); + signal d_alu_n_o_i : std_logic; + signal d_alu_o_i : std_logic_vector(7 downto 0); + signal d_alu_or_o_i : std_logic; + signal d_regs_in_o_i : std_logic_vector(7 downto 0); + signal d_regs_out_o_i : std_logic_vector(7 downto 0); + signal fetch_o_i : std_logic; + signal ld_o_i : std_logic_vector(1 downto 0); + signal ld_pc_o_i : std_logic; + signal ld_sp_o_i : std_logic; + signal load_regs_o_i : std_logic; + signal nmi_o_i : std_logic; + signal offset_o_i : std_logic_vector(15 downto 0); + signal q_a_o_i : std_logic_vector(7 downto 0); + signal q_x_o_i : std_logic_vector(7 downto 0); + signal q_y_o_i : std_logic_vector(7 downto 0); + signal reg_0flag_o_i : std_logic; + signal reg_1flag_o_i : std_logic; + signal reg_7flag_o_i : std_logic; + signal sel_pc_as_o_i : std_logic; + signal sel_pc_in_o_i : std_logic; + signal sel_pc_val_o_i : std_logic_vector(1 downto 0); + signal sel_rb_in_o_i : std_logic_vector(1 downto 0); + signal sel_rb_out_o_i : std_logic_vector(1 downto 0); + signal sel_reg_o_i : std_logic_vector(1 downto 0); + signal sel_sp_as_o_i : std_logic; + signal sel_sp_in_o_i : std_logic; + + + -- ModuleWare signal declarations(v1.9) for instance 'U_11' of 'add' + signal mw_U_11temp_din0 : std_logic_vector(8 downto 0); + signal mw_U_11temp_din1 : std_logic_vector(8 downto 0); + signal mw_U_11sum : unsigned(8 downto 0); + + -- Component Declarations + component FSM_Execution_Unit + port ( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic ; + nmi_i : in std_logic ; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic ; + reg_0flag_i : in std_logic ; + reg_1flag_i : in std_logic ; + reg_7flag_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + fetch_o : out std_logic ; + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic ; + ld_sp_o : out std_logic ; + load_regs_o : out std_logic ; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic ; + sel_pc_as_o : out std_logic ; + sel_pc_in_o : out std_logic ; + sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); + sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); + sel_reg_o : out std_logic_vector ( 1 downto 0 ); + sel_sp_as_o : out std_logic ; + sel_sp_in_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + component FSM_NMI + port ( + clk_clk_i : in std_logic ; + fetch_i : in std_logic ; + nmi_n_i : in std_logic ; + rst_rst_n_i : in std_logic ; + nmi_o : out std_logic + ); + end component; + component RegBank_AXY + port ( + clk_clk_i : in std_logic ; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + end component; + component Reg_PC + port ( + adr_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic ; + ld_i : in std_logic_vector (1 downto 0); + ld_pc_i : in std_logic ; + offset_i : in std_logic_vector (15 downto 0); + rst_rst_n_i : in std_logic ; + sel_pc_as_i : in std_logic ; + sel_pc_in_i : in std_logic ; + sel_pc_val_i : in std_logic_vector (1 downto 0); + adr_nxt_pc_o : out std_logic_vector (15 downto 0); + adr_pc_o : out std_logic_vector (15 downto 0) + ); + end component; + component Reg_SP + port ( + adr_low_i : in std_logic_vector (7 downto 0); + clk_clk_i : in std_logic ; + ld_low_i : in std_logic ; + ld_sp_i : in std_logic ; + rst_rst_n_i : in std_logic ; + sel_sp_as_i : in std_logic ; + sel_sp_in_i : in std_logic ; + adr_sp_o : out std_logic_vector (15 downto 0) + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : FSM_Execution_Unit use entity R6502_TC.FSM_Execution_Unit; + for all : FSM_NMI use entity R6502_TC.FSM_NMI; + for all : RegBank_AXY use entity R6502_TC.RegBank_AXY; + for all : Reg_PC use entity R6502_TC.Reg_PC; + for all : Reg_SP use entity R6502_TC.Reg_SP; + -- pragma synthesis_on + + +begin + + -- ModuleWare code(v1.9) for instance 'U_11' of 'add' + mw_U_11temp_din0 <= '0' & ch_a_o_i; + mw_U_11temp_din1 <= '0' & ch_b_o_i; + u_11combo_proc: process (mw_U_11temp_din0, mw_U_11temp_din1) + variable temp_carry : std_logic; + begin + temp_carry := '0'; + mw_U_11sum <= unsigned(mw_U_11temp_din0) + unsigned(mw_U_11temp_din1) + temp_carry; + end process u_11combo_proc; + d_alu_o_i <= conv_std_logic_vector(mw_U_11sum(7 downto 0),8); + reg_0flag_o_i <= mw_U_11sum(8) ; + + -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' + reg_1flag_o_i <= not(d_alu_or_o_i); + + -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' + reg_7flag_o_i <= not(d_alu_n_o_i); + + -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' + d_alu_n_o_i <= not(d_alu_o_i(7)); + + -- ModuleWare code(v1.9) for instance 'U_7' of 'por' + d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); + + -- Instance port mappings. + U_4 : FSM_Execution_Unit + port map ( + adr_nxt_pc_i => adr_nxt_pc_o_i, + adr_pc_i => adr_pc_o_i, + adr_sp_i => adr_sp_o_i, + clk_clk_i => clk_clk_i, + d_alu_i => d_alu_o_i, + d_i => d_i, + d_regs_out_i => d_regs_out_o_i, + irq_n_i => irq_n_i, + nmi_i => nmi_o_i, + q_a_i => q_a_o_i, + q_x_i => q_x_o_i, + q_y_i => q_y_o_i, + rdy_i => rdy_i, + reg_0flag_i => reg_0flag_o_i, + reg_1flag_i => reg_1flag_o_i, + reg_7flag_i => reg_7flag_o_i, + rst_rst_n_i => rst_rst_n_i, + so_n_i => so_n_i, + a_o => a_o, + adr_o => adr_o_i, + ch_a_o => ch_a_o_i, + ch_b_o => ch_b_o_i, + d_o => d_o, + d_regs_in_o => d_regs_in_o_i, + fetch_o => fetch_o_i, + ld_o => ld_o_i, + ld_pc_o => ld_pc_o_i, + ld_sp_o => ld_sp_o_i, + load_regs_o => load_regs_o_i, + offset_o => offset_o_i, + rd_o => rd_o, + sel_pc_as_o => sel_pc_as_o_i, + sel_pc_in_o => sel_pc_in_o_i, + sel_pc_val_o => sel_pc_val_o_i, + sel_rb_in_o => sel_rb_in_o_i, + sel_rb_out_o => sel_rb_out_o_i, + sel_reg_o => sel_reg_o_i, + sel_sp_as_o => sel_sp_as_o_i, + sel_sp_in_o => sel_sp_in_o_i, + sync_o => sync_o, + wr_n_o => wr_n_o, + wr_o => wr_o + ); + U_6 : FSM_NMI + port map ( + clk_clk_i => clk_clk_i, + fetch_i => fetch_o_i, + nmi_n_i => nmi_n_i, + rst_rst_n_i => rst_rst_n_i, + nmi_o => nmi_o_i + ); + U_2 : RegBank_AXY + port map ( + clk_clk_i => clk_clk_i, + d_regs_in_i => d_regs_in_o_i, + load_regs_i => load_regs_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_rb_in_i => sel_rb_in_o_i, + sel_rb_out_i => sel_rb_out_o_i, + sel_reg_i => sel_reg_o_i, + d_regs_out_o => d_regs_out_o_i, + q_a_o => q_a_o_i, + q_x_o => q_x_o_i, + q_y_o => q_y_o_i + ); + U_0 : Reg_PC + port map ( + adr_i => adr_o_i, + clk_clk_i => clk_clk_i, + ld_i => ld_o_i, + ld_pc_i => ld_pc_o_i, + offset_i => offset_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_pc_as_i => sel_pc_as_o_i, + sel_pc_in_i => sel_pc_in_o_i, + sel_pc_val_i => sel_pc_val_o_i, + adr_nxt_pc_o => adr_nxt_pc_o_i, + adr_pc_o => adr_pc_o_i + ); + U_1 : Reg_SP + port map ( + adr_low_i => adr_o_i(7 DOWNTO 0), + clk_clk_i => clk_clk_i, + ld_low_i => ld_o_i(0), + ld_sp_i => ld_sp_o_i, + rst_rst_n_i => rst_rst_n_i, + sel_sp_as_i => sel_sp_as_o_i, + sel_sp_in_i => sel_sp_in_o_i, + adr_sp_o => adr_sp_o_i + ); + +end struct;
vhdl/core.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/fsm_nmi.vhd =================================================================== --- vhdl/fsm_nmi.vhd (nonexistent) +++ vhdl/fsm_nmi.vhd (revision 18) @@ -0,0 +1,167 @@ +-- VHDL Entity R6502_TC.FSM_NMI.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:05 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity FSM_NMI is + port( + clk_clk_i : in std_logic; + fetch_i : in std_logic; + nmi_n_i : in std_logic; + rst_rst_n_i : in std_logic; + nmi_o : out std_logic + ); + +-- Declarations + +end FSM_NMI ; + +-- Jens-D. Gutschmidt Project: R6502_TC + +-- scantara2003@yahoo.de + +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG + +-- + +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by + +-- the Free Software Foundation, either version 3 of the License, or any later version. + +-- + +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +-- + +-- You should have received a copy of the GNU General Public License along with this program. If not, see . + +-- + +-- CVS Revisins History + +-- + +-- $Log: not supported by cvs2svn $ + +-- <<-- more -->> + +-- Title: FSM for NMI + +-- Path: R6502_TC/FSM_NMI/fsm + +-- Edited: by eda on 03 Jan 2009 + +-- +-- VHDL Architecture R6502_TC.FSM_NMI.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:43:05 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of FSM_NMI is + + type state_type is ( + idle, + idle1, + idle2, + IMP + ); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal nmi_o_cld : std_logic ; + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= idle; + -- Default Reset Values + nmi_o_cld <= '0'; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + nmi_o_cld <= '0'; + + -- Combined Actions + case current_state is + when IMP => + nmi_o_cld <= '1'; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + current_state, + fetch_i, + nmi_n_i + ) + ----------------------------------------------------------------- + begin + case current_state is + -- <<< REQ1 + when idle => + if (nmi_n_i = '1') then + next_state <= idle1; + else + next_state <= idle; + end if; + when idle1 => + if (nmi_n_i = '0') then + next_state <= idle2; + else + next_state <= idle1; + end if; + when idle2 => + if (nmi_n_i = '0') then + next_state <= IMP; + else + next_state <= idle; + end if; + when IMP => + if (fetch_i = '1') then + next_state <= idle; + else + next_state <= IMP; + end if; + when others => + next_state <= idle; + end case; + end process nextstate_proc; + + -- Concurrent Statements + -- Clocked output assignments + nmi_o <= nmi_o_cld; +end fsm;
vhdl/fsm_nmi.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/regbank_axy.vhd =================================================================== --- vhdl/regbank_axy.vhd (nonexistent) +++ vhdl/regbank_axy.vhd (revision 18) @@ -0,0 +1,191 @@ +-- VHDL Entity R6502_TC.RegBank_AXY.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:53 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity RegBank_AXY is + port( + clk_clk_i : in std_logic; + d_regs_in_i : in std_logic_vector (7 downto 0); + load_regs_i : in std_logic; + rst_rst_n_i : in std_logic; + sel_rb_in_i : in std_logic_vector (1 downto 0); + sel_rb_out_i : in std_logic_vector (1 downto 0); + sel_reg_i : in std_logic_vector (1 downto 0); + d_regs_out_o : out std_logic_vector (7 downto 0); + q_a_o : out std_logic_vector (7 downto 0); + q_x_o : out std_logic_vector (7 downto 0); + q_y_o : out std_logic_vector (7 downto 0) + ); + +-- Declarations + +end RegBank_AXY ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- <<-- more -->> +-- Title: Register Bank for register A, X and Y +-- Path: R6502_TC/RegBank_AXY/struct +-- Edited: by eda on 02 Jan 2009 +-- +-- VHDL Architecture R6502_TC.RegBank_AXY.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 22:42:53 04.01.2009 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + + +architecture struct of RegBank_AXY is + + -- Architecture declarations + + -- Internal signal declarations + signal ld : std_logic_vector(2 downto 0); + signal load1_o_i : std_logic; + signal load2_o_i : std_logic; + signal load_o_i : std_logic; + signal q_mux_o_i : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal q_a_o_internal : std_logic_vector (7 downto 0); + signal q_x_o_internal : std_logic_vector (7 downto 0); + signal q_y_o_internal : std_logic_vector (7 downto 0); + + + -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff' + signal mw_U_0reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff' + signal mw_U_4reg_cval : std_logic_vector(7 downto 0); + + -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff' + signal mw_U_5reg_cval : std_logic_vector(7 downto 0); + + +begin + + -- ModuleWare code(v1.9) for instance 'U_0' of 'adff' + q_a_o_internal <= mw_U_0reg_cval; + u_0seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_0reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load_o_i = '1') then + mw_U_0reg_cval <= q_mux_o_i; + end if; + end if; + end process u_0seq_proc; + + -- ModuleWare code(v1.9) for instance 'U_4' of 'adff' + q_x_o_internal <= mw_U_4reg_cval; + u_4seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_4reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load1_o_i = '1') then + mw_U_4reg_cval <= q_mux_o_i; + end if; + end if; + end process u_4seq_proc; + + -- ModuleWare code(v1.9) for instance 'U_5' of 'adff' + q_y_o_internal <= mw_U_5reg_cval; + u_5seq_proc: process (clk_clk_i, rst_rst_n_i) + begin + if (rst_rst_n_i = '0') then + mw_U_5reg_cval <= "00000000"; + elsif (clk_clk_i'event and clk_clk_i='1') then + if (load2_o_i = '1') then + mw_U_5reg_cval <= q_mux_o_i; + end if; + end if; + end process u_5seq_proc; + + -- ModuleWare code(v1.9) for instance 'U_6' of 'and' + load_o_i <= load_regs_i and ld(0); + + -- ModuleWare code(v1.9) for instance 'U_7' of 'and' + load1_o_i <= load_regs_i and ld(1); + + -- ModuleWare code(v1.9) for instance 'U_8' of 'and' + load2_o_i <= load_regs_i and ld(2); + + -- ModuleWare code(v1.9) for instance 'U_11' of 'constval' + val_zero <= "00000000"; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1' + u_1combo_proc: process (sel_reg_i) + begin + ld <= (others => '0'); + case sel_reg_i is + when "00" => ld(0) <= '1'; + when "01" => ld(1) <= '1'; + when "10" => ld(2) <= '1'; + when others => ld <= (others => '0'); + end case; + end process u_1combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_2' of 'mux' + u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, + val_zero, sel_rb_out_i) + begin + case sel_rb_out_i is + when "00" => d_regs_out_o <= q_a_o_internal; + when "01" => d_regs_out_o <= q_x_o_internal; + when "10" => d_regs_out_o <= q_y_o_internal; + when "11" => d_regs_out_o <= val_zero; + when others => d_regs_out_o <= (others => 'X'); + end case; + end process u_2combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_3' of 'mux' + u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, + d_regs_in_i, sel_rb_in_i) + begin + case sel_rb_in_i is + when "00" => q_mux_o_i <= q_a_o_internal; + when "01" => q_mux_o_i <= q_y_o_internal; + when "10" => q_mux_o_i <= q_x_o_internal; + when "11" => q_mux_o_i <= d_regs_in_i; + when others => q_mux_o_i <= (others => 'X'); + end case; + end process u_3combo_proc; + + -- Instance port mappings. + + -- Implicit buffered output assignments + q_a_o <= q_a_o_internal; + q_x_o <= q_x_o_internal; + q_y_o <= q_y_o_internal; + +end struct;
vhdl/regbank_axy.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/R6502_TC_config.vhd =================================================================== --- vhdl/R6502_TC_config.vhd (nonexistent) +++ vhdl/R6502_TC_config.vhd (revision 18) @@ -0,0 +1,38 @@ +-- Generation properties: +-- Format : flat +-- Generic mappings : exclude +-- Leaf-level entities : direct binding +-- Regular libraries : use work +-- View name : include +-- +library work; +configuration R6502_TC_config of R6502_TC is + for struct + for all : Core + use entity work.Core(struct); + for struct + for all : FSM_Execution_Unit + use entity work.FSM_Execution_Unit(fsm); + end for; + for all : FSM_NMI + use entity work.FSM_NMI(fsm); + end for; + for all : RegBank_AXY + use entity work.RegBank_AXY(struct); + for struct + end for; + end for; + for all : Reg_PC + use entity work.Reg_PC(struct); + for struct + end for; + end for; + for all : Reg_SP + use entity work.Reg_SP(struct); + for struct + end for; + end for; + end for; + end for; + end for; +end R6502_TC_config; Index: vhdl/testbench.vhd =================================================================== --- vhdl/testbench.vhd (nonexistent) +++ vhdl/testbench.vhd (revision 18) @@ -0,0 +1,1144 @@ +-- VHDL Entity R6502_TC.Testbench.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 13:06:53 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity Testbench is + port( + IRQn : in std_logic; + NMIn : in std_logic; + RDY : in std_logic; + RSTn : in std_logic; + clk : in std_logic; + clk1 : in std_logic; + so_n_i : in std_logic; + A : out std_logic_vector (15 downto 0); + CPU_DOUT : out std_logic_vector ( 7 downto 0 ); + RAM_DOUT : out std_logic_vector (7 downto 0); + RD : out std_logic; + SYNC : out std_logic; + WR : out std_logic + ); + +-- Declarations + +end Testbench ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $log$ +-- +-- Title: Testbench for the 6502 Core +-- Path: R6502_TC/Testbench/struct +-- Edited: by eda on 08 Apr 2008 +-- +-- VHDL Architecture R6502_TC.Testbench.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 13:06:54 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library R6502_TC; + +architecture struct of Testbench is + + -- Architecture declarations + + -- Internal signal declarations + signal dout : std_logic_vector(7 downto 0); + signal dout1 : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal CPU_DOUT_internal : std_logic_vector ( 7 downto 0 ); + signal RAM_DOUT_internal : std_logic_vector (7 downto 0); + signal WR_internal : std_logic; + signal A_internal : std_logic_vector (15 downto 0); + + + -- ModuleWare signal declarations(v1.9) for instance 'U_2' of 'ramsp' + type MW_U_2RAM_TYPE is array (((2**16) -1) downto 0) of std_logic_vector(7 downto 0); + signal mw_U_2ram_table : MW_U_2RAM_TYPE := (others => "00000000"); + signal mw_U_2addr_reg: std_logic_vector(15 downto 0); + + -- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'rom' + type MW_U_3ROM_TYPE is array(65535 downto 0) of std_logic_vector(7 downto 0); + signal mw_U_3rom_table : MW_U_3ROM_TYPE; + signal mw_U_3addr_int : INTEGER := 0 ; + + -- Component Declarations + component R6502_TC + port ( + clk_clk_i : in std_logic ; + d_i : in std_logic_vector (7 downto 0); + irq_n_i : in std_logic ; + nmi_n_i : in std_logic ; + rdy_i : in std_logic ; + rst_rst_n_i : in std_logic ; + so_n_i : in std_logic ; + a_o : out std_logic_vector (15 downto 0); + d_o : out std_logic_vector (7 downto 0); + rd_o : out std_logic ; + sync_o : out std_logic ; + wr_n_o : out std_logic ; + wr_o : out std_logic + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : R6502_TC use entity R6502_TC.R6502_TC; + -- pragma synthesis_on + + +begin + + -- ModuleWare code(v1.9) for instance 'U_1' of 'mux' + u_1combo_proc: process(dout, dout1, A_internal(15)) + begin + case A_internal(15) is + when '0' => RAM_DOUT_internal <= dout; + when '1' => RAM_DOUT_internal <= dout1; + when others => RAM_DOUT_internal <= (others => 'X'); + end case; + end process u_1combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_2' of 'ramsp' + --attribute block_ram : boolean; + --attribute block_ram of mem : signal is false; + u_2ram_p_proc: process (clk1) + begin + if (clk1'event and clk1='1') then + if (WR_internal = '1') then + mw_U_2ram_table(CONV_INTEGER(unsigned(A_internal))) <= CPU_DOUT_internal; + end if; + mw_U_2addr_reg <= A_internal; + end if; + end process u_2ram_p_proc; + dout <= mw_U_2ram_table(CONV_INTEGER(unsigned(mw_U_2addr_reg))); + + -- ModuleWare code(v1.9) for instance 'U_3' of 'rom' + mw_U_3addr_int <= (CONV_INTEGER(unsigned(A_internal(15 DOWNTO 0)))); + u_3rom_table_proc : process ( mw_U_3addr_int ) + begin + case mw_U_3addr_int is + when 32768 => mw_U_3rom_table(32768) <= "11111111"; + when 32769 => mw_U_3rom_table(32769) <= "11111111"; + when 32770 => mw_U_3rom_table(32770) <= "11111111"; + when 32771 => mw_U_3rom_table(32771) <= "11111111"; + when 32772 => mw_U_3rom_table(32772) <= "11111111"; + when 32773 => mw_U_3rom_table(32773) <= "11111111"; + when 32774 => mw_U_3rom_table(32774) <= "11111111"; + when 32775 => mw_U_3rom_table(32775) <= "11111111"; + when 32776 => mw_U_3rom_table(32776) <= "11111111"; + when 32777 => mw_U_3rom_table(32777) <= "11111111"; + when 32778 => mw_U_3rom_table(32778) <= "11111111"; + when 32779 => mw_U_3rom_table(32779) <= "11111111"; + when 32780 => mw_U_3rom_table(32780) <= "11111111"; + when 32781 => mw_U_3rom_table(32781) <= "11111111"; + when 32782 => mw_U_3rom_table(32782) <= "11111111"; + when 32783 => mw_U_3rom_table(32783) <= "11111111"; + when 32784 => mw_U_3rom_table(32784) <= "11111111"; + when 32785 => mw_U_3rom_table(32785) <= "11111111"; + when 32786 => mw_U_3rom_table(32786) <= "11111111"; + when 32787 => mw_U_3rom_table(32787) <= "11111111"; + when 32788 => mw_U_3rom_table(32788) <= "11111111"; + when 32789 => mw_U_3rom_table(32789) <= "11111111"; + when 32790 => mw_U_3rom_table(32790) <= "11111111"; + when 32791 => mw_U_3rom_table(32791) <= "11111111"; + when 32792 => mw_U_3rom_table(32792) <= "11111111"; + when 32793 => mw_U_3rom_table(32793) <= "11111111"; + when 32794 => mw_U_3rom_table(32794) <= "11111111"; + when 32795 => mw_U_3rom_table(32795) <= "11111111"; + when 32796 => mw_U_3rom_table(32796) <= "11111111"; + when 32797 => mw_U_3rom_table(32797) <= "11111111"; + when 32798 => mw_U_3rom_table(32798) <= "11111111"; + when 32799 => mw_U_3rom_table(32799) <= "00000000"; + when 57344 => mw_U_3rom_table(57344) <= "00010100"; + when 57345 => mw_U_3rom_table(57345) <= "00000000"; + when 57346 => mw_U_3rom_table(57346) <= "00001010"; + when 57347 => mw_U_3rom_table(57347) <= "00000000"; + when 57348 => mw_U_3rom_table(57348) <= "00000100"; + when 57349 => mw_U_3rom_table(57349) <= "00000000"; + when 57350 => mw_U_3rom_table(57350) <= "00000011"; + when 57351 => mw_U_3rom_table(57351) <= "00000000"; + when 57352 => mw_U_3rom_table(57352) <= "00000010"; + when 57353 => mw_U_3rom_table(57353) <= "00000000"; + when 57354 => mw_U_3rom_table(57354) <= "00000001"; + when 57355 => mw_U_3rom_table(57355) <= "00000000"; + when 57356 => mw_U_3rom_table(57356) <= "00000000"; + when 57357 => mw_U_3rom_table(57357) <= "00000100"; + when 57358 => mw_U_3rom_table(57358) <= "11010010"; + when 57359 => mw_U_3rom_table(57359) <= "00000100"; + when 57360 => mw_U_3rom_table(57360) <= "11010010"; + when 57361 => mw_U_3rom_table(57361) <= "00000010"; + when 57362 => mw_U_3rom_table(57362) <= "10011100"; + when 57363 => mw_U_3rom_table(57363) <= "00000010"; + when 57364 => mw_U_3rom_table(57364) <= "10011100"; + when 57365 => mw_U_3rom_table(57365) <= "00000000"; + when 57366 => mw_U_3rom_table(57366) <= "00101010"; + when 57367 => mw_U_3rom_table(57367) <= "00000000"; + when 57368 => mw_U_3rom_table(57368) <= "00101010"; + when 57369 => mw_U_3rom_table(57369) <= "00010010"; + when 57370 => mw_U_3rom_table(57370) <= "00110100"; + when 57371 => mw_U_3rom_table(57371) <= "00000110"; + when 57372 => mw_U_3rom_table(57372) <= "00010001"; + when 57373 => mw_U_3rom_table(57373) <= "00010010"; + when 57374 => mw_U_3rom_table(57374) <= "00110100"; + when 57375 => mw_U_3rom_table(57375) <= "00010010"; + when 57376 => mw_U_3rom_table(57376) <= "00000001"; + when 57377 => mw_U_3rom_table(57377) <= "00000000"; + when 57378 => mw_U_3rom_table(57378) <= "00000001"; + when 57379 => mw_U_3rom_table(57379) <= "00000000"; + when 57380 => mw_U_3rom_table(57380) <= "00000001"; + when 57381 => mw_U_3rom_table(57381) <= "00000000"; + when 57382 => mw_U_3rom_table(57382) <= "00000000"; + when 57383 => mw_U_3rom_table(57383) <= "00000000"; + when 57384 => mw_U_3rom_table(57384) <= "00000001"; + when 57385 => mw_U_3rom_table(57385) <= "00000000"; + when 57386 => mw_U_3rom_table(57386) <= "00000000"; + when 57387 => mw_U_3rom_table(57387) <= "00000000"; + when 57388 => mw_U_3rom_table(57388) <= "00000001"; + when 57389 => mw_U_3rom_table(57389) <= "00100011"; + when 57390 => mw_U_3rom_table(57390) <= "01000000"; + when 57391 => mw_U_3rom_table(57391) <= "00000001"; + when 57392 => mw_U_3rom_table(57392) <= "00100011"; + when 57393 => mw_U_3rom_table(57393) <= "00000000"; + when 57394 => mw_U_3rom_table(57394) <= "00000011"; + when 57395 => mw_U_3rom_table(57395) <= "11111111"; + when 57396 => mw_U_3rom_table(57396) <= "11111100"; + when 57397 => mw_U_3rom_table(57397) <= "00000000"; + when 57398 => mw_U_3rom_table(57398) <= "00001010"; + when 57399 => mw_U_3rom_table(57399) <= "00000000"; + when 57400 => mw_U_3rom_table(57400) <= "00010101"; + when 57401 => mw_U_3rom_table(57401) <= "11100000"; + when 57402 => mw_U_3rom_table(57402) <= "00100101"; + when 57403 => mw_U_3rom_table(57403) <= "11100000"; + when 57404 => mw_U_3rom_table(57404) <= "00100011"; + when 57405 => mw_U_3rom_table(57405) <= "00000000"; + when 57406 => mw_U_3rom_table(57406) <= "01100100"; + when 57407 => mw_U_3rom_table(57407) <= "00000000"; + when 57408 => mw_U_3rom_table(57408) <= "11111111"; + when 57409 => mw_U_3rom_table(57409) <= "11111111"; + when 57410 => mw_U_3rom_table(57410) <= "11111111"; + when 57411 => mw_U_3rom_table(57411) <= "11111111"; + when 57412 => mw_U_3rom_table(57412) <= "11111111"; + when 57413 => mw_U_3rom_table(57413) <= "11111111"; + when 57414 => mw_U_3rom_table(57414) <= "11111111"; + when 57415 => mw_U_3rom_table(57415) <= "11111111"; + when 57416 => mw_U_3rom_table(57416) <= "11111111"; + when 57417 => mw_U_3rom_table(57417) <= "11111111"; + when 57418 => mw_U_3rom_table(57418) <= "11111111"; + when 57419 => mw_U_3rom_table(57419) <= "11111111"; + when 57420 => mw_U_3rom_table(57420) <= "11111111"; + when 57421 => mw_U_3rom_table(57421) <= "11111111"; + when 57422 => mw_U_3rom_table(57422) <= "11111111"; + when 57423 => mw_U_3rom_table(57423) <= "11111111"; + when 57424 => mw_U_3rom_table(57424) <= "11111111"; + when 57425 => mw_U_3rom_table(57425) <= "11111111"; + when 57426 => mw_U_3rom_table(57426) <= "11111111"; + when 57427 => mw_U_3rom_table(57427) <= "11111111"; + when 57428 => mw_U_3rom_table(57428) <= "11111111"; + when 57429 => mw_U_3rom_table(57429) <= "11111111"; + when 57430 => mw_U_3rom_table(57430) <= "11111111"; + when 57431 => mw_U_3rom_table(57431) <= "11111111"; + when 57432 => mw_U_3rom_table(57432) <= "11111111"; + when 57433 => mw_U_3rom_table(57433) <= "00010010"; + when 57434 => mw_U_3rom_table(57434) <= "00110100"; + when 57435 => mw_U_3rom_table(57435) <= "00000000"; + when 57436 => mw_U_3rom_table(57436) <= "00000000"; + when 57437 => mw_U_3rom_table(57437) <= "00000000"; + when 57438 => mw_U_3rom_table(57438) <= "00000000"; + when 57439 => mw_U_3rom_table(57439) <= "00000000"; + when 61440 => mw_U_3rom_table(61440) <= "00000110"; + when 61441 => mw_U_3rom_table(61441) <= "10101101"; + when 61442 => mw_U_3rom_table(61442) <= "01011011"; + when 61443 => mw_U_3rom_table(61443) <= "10000101"; + when 61444 => mw_U_3rom_table(61444) <= "11100000"; + when 61445 => mw_U_3rom_table(61445) <= "00000101"; + when 61446 => mw_U_3rom_table(61446) <= "10101101"; + when 61447 => mw_U_3rom_table(61447) <= "01011010"; + when 61448 => mw_U_3rom_table(61448) <= "10000101"; + when 61449 => mw_U_3rom_table(61449) <= "11100000"; + when 61450 => mw_U_3rom_table(61450) <= "00000100"; + when 61451 => mw_U_3rom_table(61451) <= "10101101"; + when 61452 => mw_U_3rom_table(61452) <= "01011001"; + when 61453 => mw_U_3rom_table(61453) <= "10000101"; + when 61454 => mw_U_3rom_table(61454) <= "11100000"; + when 61455 => mw_U_3rom_table(61455) <= "00000011"; + when 61456 => mw_U_3rom_table(61456) <= "10101101"; + when 61457 => mw_U_3rom_table(61457) <= "01011000"; + when 61458 => mw_U_3rom_table(61458) <= "10000101"; + when 61459 => mw_U_3rom_table(61459) <= "11100000"; + when 61460 => mw_U_3rom_table(61460) <= "00000010"; + when 61461 => mw_U_3rom_table(61461) <= "10101101"; + when 61462 => mw_U_3rom_table(61462) <= "01010111"; + when 61463 => mw_U_3rom_table(61463) <= "10000101"; + when 61464 => mw_U_3rom_table(61464) <= "11100000"; + when 61465 => mw_U_3rom_table(61465) <= "00000001"; + when 61466 => mw_U_3rom_table(61466) <= "10101101"; + when 61467 => mw_U_3rom_table(61467) <= "01010110"; + when 61468 => mw_U_3rom_table(61468) <= "10000101"; + when 61469 => mw_U_3rom_table(61469) <= "11100000"; + when 61470 => mw_U_3rom_table(61470) <= "00000000"; + when 61471 => mw_U_3rom_table(61471) <= "10101101"; + when 61472 => mw_U_3rom_table(61472) <= "10000101"; + when 61473 => mw_U_3rom_table(61473) <= "11100000"; + when 61474 => mw_U_3rom_table(61474) <= "00001100"; + when 61475 => mw_U_3rom_table(61475) <= "10101101"; + when 61476 => mw_U_3rom_table(61476) <= "01100001"; + when 61477 => mw_U_3rom_table(61477) <= "10000101"; + when 61478 => mw_U_3rom_table(61478) <= "11100000"; + when 61479 => mw_U_3rom_table(61479) <= "00001011"; + when 61480 => mw_U_3rom_table(61480) <= "10101101"; + when 61481 => mw_U_3rom_table(61481) <= "01100000"; + when 61482 => mw_U_3rom_table(61482) <= "10000101"; + when 61483 => mw_U_3rom_table(61483) <= "11100000"; + when 61484 => mw_U_3rom_table(61484) <= "00001010"; + when 61485 => mw_U_3rom_table(61485) <= "10101101"; + when 61486 => mw_U_3rom_table(61486) <= "01011111"; + when 61487 => mw_U_3rom_table(61487) <= "10000101"; + when 61488 => mw_U_3rom_table(61488) <= "11100000"; + when 61489 => mw_U_3rom_table(61489) <= "00001001"; + when 61490 => mw_U_3rom_table(61490) <= "10101101"; + when 61491 => mw_U_3rom_table(61491) <= "01011110"; + when 61492 => mw_U_3rom_table(61492) <= "10000101"; + when 61493 => mw_U_3rom_table(61493) <= "11100000"; + when 61494 => mw_U_3rom_table(61494) <= "00001000"; + when 61495 => mw_U_3rom_table(61495) <= "10101101"; + when 61496 => mw_U_3rom_table(61496) <= "01011101"; + when 61497 => mw_U_3rom_table(61497) <= "10000101"; + when 61498 => mw_U_3rom_table(61498) <= "11100000"; + when 61499 => mw_U_3rom_table(61499) <= "00000111"; + when 61500 => mw_U_3rom_table(61500) <= "10101101"; + when 61501 => mw_U_3rom_table(61501) <= "01011100"; + when 61502 => mw_U_3rom_table(61502) <= "10000101"; + when 61503 => mw_U_3rom_table(61503) <= "11100000"; + when 61504 => mw_U_3rom_table(61504) <= "10101101"; + when 61505 => mw_U_3rom_table(61505) <= "01101000"; + when 61506 => mw_U_3rom_table(61506) <= "10000101"; + when 61507 => mw_U_3rom_table(61507) <= "11100000"; + when 61508 => mw_U_3rom_table(61508) <= "00010010"; + when 61509 => mw_U_3rom_table(61509) <= "10101101"; + when 61510 => mw_U_3rom_table(61510) <= "01100111"; + when 61511 => mw_U_3rom_table(61511) <= "10000101"; + when 61512 => mw_U_3rom_table(61512) <= "11100000"; + when 61513 => mw_U_3rom_table(61513) <= "00010001"; + when 61514 => mw_U_3rom_table(61514) <= "10101101"; + when 61515 => mw_U_3rom_table(61515) <= "01100110"; + when 61516 => mw_U_3rom_table(61516) <= "10000101"; + when 61517 => mw_U_3rom_table(61517) <= "11100000"; + when 61518 => mw_U_3rom_table(61518) <= "00010000"; + when 61519 => mw_U_3rom_table(61519) <= "10101101"; + when 61520 => mw_U_3rom_table(61520) <= "01100101"; + when 61521 => mw_U_3rom_table(61521) <= "10000101"; + when 61522 => mw_U_3rom_table(61522) <= "11100000"; + when 61523 => mw_U_3rom_table(61523) <= "00001111"; + when 61524 => mw_U_3rom_table(61524) <= "10101101"; + when 61525 => mw_U_3rom_table(61525) <= "01100100"; + when 61526 => mw_U_3rom_table(61526) <= "10000101"; + when 61527 => mw_U_3rom_table(61527) <= "11100000"; + when 61528 => mw_U_3rom_table(61528) <= "00001110"; + when 61529 => mw_U_3rom_table(61529) <= "10101101"; + when 61530 => mw_U_3rom_table(61530) <= "01100011"; + when 61531 => mw_U_3rom_table(61531) <= "10000101"; + when 61532 => mw_U_3rom_table(61532) <= "11100000"; + when 61533 => mw_U_3rom_table(61533) <= "00001101"; + when 61534 => mw_U_3rom_table(61534) <= "10101101"; + when 61535 => mw_U_3rom_table(61535) <= "01100010"; + when 61536 => mw_U_3rom_table(61536) <= "11100000"; + when 61537 => mw_U_3rom_table(61537) <= "00011001"; + when 61538 => mw_U_3rom_table(61538) <= "10101101"; + when 61539 => mw_U_3rom_table(61539) <= "01101110"; + when 61540 => mw_U_3rom_table(61540) <= "10000101"; + when 61541 => mw_U_3rom_table(61541) <= "11100000"; + when 61542 => mw_U_3rom_table(61542) <= "00011000"; + when 61543 => mw_U_3rom_table(61543) <= "10101101"; + when 61544 => mw_U_3rom_table(61544) <= "01101101"; + when 61545 => mw_U_3rom_table(61545) <= "10000101"; + when 61546 => mw_U_3rom_table(61546) <= "11100000"; + when 61547 => mw_U_3rom_table(61547) <= "00010111"; + when 61548 => mw_U_3rom_table(61548) <= "10101101"; + when 61549 => mw_U_3rom_table(61549) <= "01101100"; + when 61550 => mw_U_3rom_table(61550) <= "10000101"; + when 61551 => mw_U_3rom_table(61551) <= "11100000"; + when 61552 => mw_U_3rom_table(61552) <= "00010110"; + when 61553 => mw_U_3rom_table(61553) <= "10101101"; + when 61554 => mw_U_3rom_table(61554) <= "01101011"; + when 61555 => mw_U_3rom_table(61555) <= "10000101"; + when 61556 => mw_U_3rom_table(61556) <= "11100000"; + when 61557 => mw_U_3rom_table(61557) <= "00010101"; + when 61558 => mw_U_3rom_table(61558) <= "10101101"; + when 61559 => mw_U_3rom_table(61559) <= "01101010"; + when 61560 => mw_U_3rom_table(61560) <= "10000101"; + when 61561 => mw_U_3rom_table(61561) <= "11100000"; + when 61562 => mw_U_3rom_table(61562) <= "00010100"; + when 61563 => mw_U_3rom_table(61563) <= "10101101"; + when 61564 => mw_U_3rom_table(61564) <= "01101001"; + when 61565 => mw_U_3rom_table(61565) <= "10000101"; + when 61566 => mw_U_3rom_table(61566) <= "11100000"; + when 61567 => mw_U_3rom_table(61567) <= "00010011"; + when 61568 => mw_U_3rom_table(61568) <= "01110101"; + when 61569 => mw_U_3rom_table(61569) <= "10000101"; + when 61570 => mw_U_3rom_table(61570) <= "11100000"; + when 61571 => mw_U_3rom_table(61571) <= "00011111"; + when 61572 => mw_U_3rom_table(61572) <= "10101101"; + when 61573 => mw_U_3rom_table(61573) <= "01110100"; + when 61574 => mw_U_3rom_table(61574) <= "10000101"; + when 61575 => mw_U_3rom_table(61575) <= "11100000"; + when 61576 => mw_U_3rom_table(61576) <= "00011110"; + when 61577 => mw_U_3rom_table(61577) <= "10101101"; + when 61578 => mw_U_3rom_table(61578) <= "01110011"; + when 61579 => mw_U_3rom_table(61579) <= "10000101"; + when 61580 => mw_U_3rom_table(61580) <= "11100000"; + when 61581 => mw_U_3rom_table(61581) <= "00011101"; + when 61582 => mw_U_3rom_table(61582) <= "10101101"; + when 61583 => mw_U_3rom_table(61583) <= "01110010"; + when 61584 => mw_U_3rom_table(61584) <= "10000101"; + when 61585 => mw_U_3rom_table(61585) <= "11100000"; + when 61586 => mw_U_3rom_table(61586) <= "00011100"; + when 61587 => mw_U_3rom_table(61587) <= "10101101"; + when 61588 => mw_U_3rom_table(61588) <= "01110001"; + when 61589 => mw_U_3rom_table(61589) <= "10000101"; + when 61590 => mw_U_3rom_table(61590) <= "11100000"; + when 61591 => mw_U_3rom_table(61591) <= "00011011"; + when 61592 => mw_U_3rom_table(61592) <= "10101101"; + when 61593 => mw_U_3rom_table(61593) <= "01110000"; + when 61594 => mw_U_3rom_table(61594) <= "10000101"; + when 61595 => mw_U_3rom_table(61595) <= "11100000"; + when 61596 => mw_U_3rom_table(61596) <= "00011010"; + when 61597 => mw_U_3rom_table(61597) <= "10101101"; + when 61598 => mw_U_3rom_table(61598) <= "01101111"; + when 61599 => mw_U_3rom_table(61599) <= "10000101"; + when 61600 => mw_U_3rom_table(61600) <= "00100110"; + when 61601 => mw_U_3rom_table(61601) <= "10101101"; + when 61602 => mw_U_3rom_table(61602) <= "01111011"; + when 61603 => mw_U_3rom_table(61603) <= "10000101"; + when 61604 => mw_U_3rom_table(61604) <= "11100000"; + when 61605 => mw_U_3rom_table(61605) <= "00100101"; + when 61606 => mw_U_3rom_table(61606) <= "10101101"; + when 61607 => mw_U_3rom_table(61607) <= "01111010"; + when 61608 => mw_U_3rom_table(61608) <= "10000101"; + when 61609 => mw_U_3rom_table(61609) <= "11100000"; + when 61610 => mw_U_3rom_table(61610) <= "00100100"; + when 61611 => mw_U_3rom_table(61611) <= "10101101"; + when 61612 => mw_U_3rom_table(61612) <= "01111001"; + when 61613 => mw_U_3rom_table(61613) <= "10000101"; + when 61614 => mw_U_3rom_table(61614) <= "11100000"; + when 61615 => mw_U_3rom_table(61615) <= "00100011"; + when 61616 => mw_U_3rom_table(61616) <= "10101101"; + when 61617 => mw_U_3rom_table(61617) <= "01111000"; + when 61618 => mw_U_3rom_table(61618) <= "10000101"; + when 61619 => mw_U_3rom_table(61619) <= "11100000"; + when 61620 => mw_U_3rom_table(61620) <= "00100010"; + when 61621 => mw_U_3rom_table(61621) <= "10101101"; + when 61622 => mw_U_3rom_table(61622) <= "01110111"; + when 61623 => mw_U_3rom_table(61623) <= "10000101"; + when 61624 => mw_U_3rom_table(61624) <= "11100000"; + when 61625 => mw_U_3rom_table(61625) <= "00100001"; + when 61626 => mw_U_3rom_table(61626) <= "10101101"; + when 61627 => mw_U_3rom_table(61627) <= "01110110"; + when 61628 => mw_U_3rom_table(61628) <= "10000101"; + when 61629 => mw_U_3rom_table(61629) <= "11100000"; + when 61630 => mw_U_3rom_table(61630) <= "00100000"; + when 61631 => mw_U_3rom_table(61631) <= "10101101"; + when 61632 => mw_U_3rom_table(61632) <= "10000101"; + when 61633 => mw_U_3rom_table(61633) <= "11100000"; + when 61634 => mw_U_3rom_table(61634) <= "00101100"; + when 61635 => mw_U_3rom_table(61635) <= "10101101"; + when 61636 => mw_U_3rom_table(61636) <= "10000001"; + when 61637 => mw_U_3rom_table(61637) <= "10000101"; + when 61638 => mw_U_3rom_table(61638) <= "11100000"; + when 61639 => mw_U_3rom_table(61639) <= "00101011"; + when 61640 => mw_U_3rom_table(61640) <= "10101101"; + when 61641 => mw_U_3rom_table(61641) <= "10000000"; + when 61642 => mw_U_3rom_table(61642) <= "10000101"; + when 61643 => mw_U_3rom_table(61643) <= "11100000"; + when 61644 => mw_U_3rom_table(61644) <= "00101010"; + when 61645 => mw_U_3rom_table(61645) <= "10101101"; + when 61646 => mw_U_3rom_table(61646) <= "01111111"; + when 61647 => mw_U_3rom_table(61647) <= "10000101"; + when 61648 => mw_U_3rom_table(61648) <= "11100000"; + when 61649 => mw_U_3rom_table(61649) <= "00101001"; + when 61650 => mw_U_3rom_table(61650) <= "10101101"; + when 61651 => mw_U_3rom_table(61651) <= "01111110"; + when 61652 => mw_U_3rom_table(61652) <= "10000101"; + when 61653 => mw_U_3rom_table(61653) <= "11100000"; + when 61654 => mw_U_3rom_table(61654) <= "00101000"; + when 61655 => mw_U_3rom_table(61655) <= "10101101"; + when 61656 => mw_U_3rom_table(61656) <= "01111101"; + when 61657 => mw_U_3rom_table(61657) <= "10000101"; + when 61658 => mw_U_3rom_table(61658) <= "11100000"; + when 61659 => mw_U_3rom_table(61659) <= "00100111"; + when 61660 => mw_U_3rom_table(61660) <= "10101101"; + when 61661 => mw_U_3rom_table(61661) <= "01111100"; + when 61662 => mw_U_3rom_table(61662) <= "10000101"; + when 61663 => mw_U_3rom_table(61663) <= "11100000"; + when 61664 => mw_U_3rom_table(61664) <= "10101101"; + when 61665 => mw_U_3rom_table(61665) <= "10001000"; + when 61666 => mw_U_3rom_table(61666) <= "10000101"; + when 61667 => mw_U_3rom_table(61667) <= "11100000"; + when 61668 => mw_U_3rom_table(61668) <= "00110010"; + when 61669 => mw_U_3rom_table(61669) <= "10101101"; + when 61670 => mw_U_3rom_table(61670) <= "10000111"; + when 61671 => mw_U_3rom_table(61671) <= "10000101"; + when 61672 => mw_U_3rom_table(61672) <= "11100000"; + when 61673 => mw_U_3rom_table(61673) <= "00110001"; + when 61674 => mw_U_3rom_table(61674) <= "10101101"; + when 61675 => mw_U_3rom_table(61675) <= "10000110"; + when 61676 => mw_U_3rom_table(61676) <= "10000101"; + when 61677 => mw_U_3rom_table(61677) <= "11100000"; + when 61678 => mw_U_3rom_table(61678) <= "00110000"; + when 61679 => mw_U_3rom_table(61679) <= "10101101"; + when 61680 => mw_U_3rom_table(61680) <= "10000101"; + when 61681 => mw_U_3rom_table(61681) <= "10000101"; + when 61682 => mw_U_3rom_table(61682) <= "11100000"; + when 61683 => mw_U_3rom_table(61683) <= "00101111"; + when 61684 => mw_U_3rom_table(61684) <= "10101101"; + when 61685 => mw_U_3rom_table(61685) <= "10000100"; + when 61686 => mw_U_3rom_table(61686) <= "10000101"; + when 61687 => mw_U_3rom_table(61687) <= "11100000"; + when 61688 => mw_U_3rom_table(61688) <= "00101110"; + when 61689 => mw_U_3rom_table(61689) <= "10101101"; + when 61690 => mw_U_3rom_table(61690) <= "10000011"; + when 61691 => mw_U_3rom_table(61691) <= "10000101"; + when 61692 => mw_U_3rom_table(61692) <= "11100000"; + when 61693 => mw_U_3rom_table(61693) <= "00101101"; + when 61694 => mw_U_3rom_table(61694) <= "10101101"; + when 61695 => mw_U_3rom_table(61695) <= "10000010"; + when 61696 => mw_U_3rom_table(61696) <= "11100000"; + when 61697 => mw_U_3rom_table(61697) <= "00111001"; + when 61698 => mw_U_3rom_table(61698) <= "10101101"; + when 61699 => mw_U_3rom_table(61699) <= "10001110"; + when 61700 => mw_U_3rom_table(61700) <= "10000101"; + when 61701 => mw_U_3rom_table(61701) <= "11100000"; + when 61702 => mw_U_3rom_table(61702) <= "00111000"; + when 61703 => mw_U_3rom_table(61703) <= "10101101"; + when 61704 => mw_U_3rom_table(61704) <= "10001101"; + when 61705 => mw_U_3rom_table(61705) <= "10000101"; + when 61706 => mw_U_3rom_table(61706) <= "11100000"; + when 61707 => mw_U_3rom_table(61707) <= "00110111"; + when 61708 => mw_U_3rom_table(61708) <= "10101101"; + when 61709 => mw_U_3rom_table(61709) <= "10001100"; + when 61710 => mw_U_3rom_table(61710) <= "10000101"; + when 61711 => mw_U_3rom_table(61711) <= "11100000"; + when 61712 => mw_U_3rom_table(61712) <= "00110110"; + when 61713 => mw_U_3rom_table(61713) <= "10101101"; + when 61714 => mw_U_3rom_table(61714) <= "10001011"; + when 61715 => mw_U_3rom_table(61715) <= "10000101"; + when 61716 => mw_U_3rom_table(61716) <= "11100000"; + when 61717 => mw_U_3rom_table(61717) <= "00110101"; + when 61718 => mw_U_3rom_table(61718) <= "10101101"; + when 61719 => mw_U_3rom_table(61719) <= "10001010"; + when 61720 => mw_U_3rom_table(61720) <= "10000101"; + when 61721 => mw_U_3rom_table(61721) <= "11100000"; + when 61722 => mw_U_3rom_table(61722) <= "00110100"; + when 61723 => mw_U_3rom_table(61723) <= "10101101"; + when 61724 => mw_U_3rom_table(61724) <= "10001001"; + when 61725 => mw_U_3rom_table(61725) <= "10000101"; + when 61726 => mw_U_3rom_table(61726) <= "11100000"; + when 61727 => mw_U_3rom_table(61727) <= "00110011"; + when 61728 => mw_U_3rom_table(61728) <= "10010101"; + when 61729 => mw_U_3rom_table(61729) <= "10000101"; + when 61730 => mw_U_3rom_table(61730) <= "11100000"; + when 61731 => mw_U_3rom_table(61731) <= "00111111"; + when 61732 => mw_U_3rom_table(61732) <= "10101101"; + when 61733 => mw_U_3rom_table(61733) <= "10010100"; + when 61734 => mw_U_3rom_table(61734) <= "10000101"; + when 61735 => mw_U_3rom_table(61735) <= "11100000"; + when 61736 => mw_U_3rom_table(61736) <= "00111110"; + when 61737 => mw_U_3rom_table(61737) <= "10101101"; + when 61738 => mw_U_3rom_table(61738) <= "10010011"; + when 61739 => mw_U_3rom_table(61739) <= "10000101"; + when 61740 => mw_U_3rom_table(61740) <= "11100000"; + when 61741 => mw_U_3rom_table(61741) <= "00111101"; + when 61742 => mw_U_3rom_table(61742) <= "10101101"; + when 61743 => mw_U_3rom_table(61743) <= "10010010"; + when 61744 => mw_U_3rom_table(61744) <= "10000101"; + when 61745 => mw_U_3rom_table(61745) <= "11100000"; + when 61746 => mw_U_3rom_table(61746) <= "00111100"; + when 61747 => mw_U_3rom_table(61747) <= "10101101"; + when 61748 => mw_U_3rom_table(61748) <= "10010001"; + when 61749 => mw_U_3rom_table(61749) <= "10000101"; + when 61750 => mw_U_3rom_table(61750) <= "11100000"; + when 61751 => mw_U_3rom_table(61751) <= "00111011"; + when 61752 => mw_U_3rom_table(61752) <= "10101101"; + when 61753 => mw_U_3rom_table(61753) <= "10010000"; + when 61754 => mw_U_3rom_table(61754) <= "10000101"; + when 61755 => mw_U_3rom_table(61755) <= "11100000"; + when 61756 => mw_U_3rom_table(61756) <= "00111010"; + when 61757 => mw_U_3rom_table(61757) <= "10101101"; + when 61758 => mw_U_3rom_table(61758) <= "10001111"; + when 61759 => mw_U_3rom_table(61759) <= "10000101"; + when 61760 => mw_U_3rom_table(61760) <= "01000110"; + when 61761 => mw_U_3rom_table(61761) <= "10101101"; + when 61762 => mw_U_3rom_table(61762) <= "10011011"; + when 61763 => mw_U_3rom_table(61763) <= "10000101"; + when 61764 => mw_U_3rom_table(61764) <= "11100000"; + when 61765 => mw_U_3rom_table(61765) <= "01000101"; + when 61766 => mw_U_3rom_table(61766) <= "10101101"; + when 61767 => mw_U_3rom_table(61767) <= "10011010"; + when 61768 => mw_U_3rom_table(61768) <= "10000101"; + when 61769 => mw_U_3rom_table(61769) <= "11100000"; + when 61770 => mw_U_3rom_table(61770) <= "01000100"; + when 61771 => mw_U_3rom_table(61771) <= "10101101"; + when 61772 => mw_U_3rom_table(61772) <= "10011001"; + when 61773 => mw_U_3rom_table(61773) <= "10000101"; + when 61774 => mw_U_3rom_table(61774) <= "11100000"; + when 61775 => mw_U_3rom_table(61775) <= "01000011"; + when 61776 => mw_U_3rom_table(61776) <= "10101101"; + when 61777 => mw_U_3rom_table(61777) <= "10011000"; + when 61778 => mw_U_3rom_table(61778) <= "10000101"; + when 61779 => mw_U_3rom_table(61779) <= "11100000"; + when 61780 => mw_U_3rom_table(61780) <= "01000010"; + when 61781 => mw_U_3rom_table(61781) <= "10101101"; + when 61782 => mw_U_3rom_table(61782) <= "10010111"; + when 61783 => mw_U_3rom_table(61783) <= "10000101"; + when 61784 => mw_U_3rom_table(61784) <= "11100000"; + when 61785 => mw_U_3rom_table(61785) <= "01000001"; + when 61786 => mw_U_3rom_table(61786) <= "10101101"; + when 61787 => mw_U_3rom_table(61787) <= "10010110"; + when 61788 => mw_U_3rom_table(61788) <= "10000101"; + when 61789 => mw_U_3rom_table(61789) <= "11100000"; + when 61790 => mw_U_3rom_table(61790) <= "01000000"; + when 61791 => mw_U_3rom_table(61791) <= "10101101"; + when 61792 => mw_U_3rom_table(61792) <= "00110101"; + when 61793 => mw_U_3rom_table(61793) <= "01010110"; + when 61794 => mw_U_3rom_table(61794) <= "00110010"; + when 61795 => mw_U_3rom_table(61795) <= "01010110"; + when 61796 => mw_U_3rom_table(61796) <= "00110001"; + when 61797 => mw_U_3rom_table(61797) <= "01010110"; + when 61798 => mw_U_3rom_table(61798) <= "00100001"; + when 61799 => mw_U_3rom_table(61799) <= "01010110"; + when 61800 => mw_U_3rom_table(61800) <= "00101001"; + when 61801 => mw_U_3rom_table(61801) <= "11110001"; + when 61802 => mw_U_3rom_table(61802) <= "01100011"; + when 61803 => mw_U_3rom_table(61803) <= "01101101"; + when 61804 => mw_U_3rom_table(61804) <= "01010110"; + when 61805 => mw_U_3rom_table(61805) <= "01100101"; + when 61806 => mw_U_3rom_table(61806) <= "00000000"; + when 61807 => mw_U_3rom_table(61807) <= "01010110"; + when 61808 => mw_U_3rom_table(61808) <= "01111001"; + when 61809 => mw_U_3rom_table(61809) <= "01010110"; + when 61810 => mw_U_3rom_table(61810) <= "01110101"; + when 61811 => mw_U_3rom_table(61811) <= "01010110"; + when 61812 => mw_U_3rom_table(61812) <= "01110010"; + when 61813 => mw_U_3rom_table(61813) <= "01010110"; + when 61814 => mw_U_3rom_table(61814) <= "01110010"; + when 61815 => mw_U_3rom_table(61815) <= "01010110"; + when 61816 => mw_U_3rom_table(61816) <= "01110001"; + when 61817 => mw_U_3rom_table(61817) <= "01010110"; + when 61818 => mw_U_3rom_table(61818) <= "01100001"; + when 61819 => mw_U_3rom_table(61819) <= "01010110"; + when 61820 => mw_U_3rom_table(61820) <= "01101001"; + when 61821 => mw_U_3rom_table(61821) <= "10011100"; + when 61822 => mw_U_3rom_table(61822) <= "10000101"; + when 61823 => mw_U_3rom_table(61823) <= "11100000"; + when 61824 => mw_U_3rom_table(61824) <= "11101010"; + when 61825 => mw_U_3rom_table(61825) <= "00000001"; + when 61826 => mw_U_3rom_table(61826) <= "00010000"; + when 61827 => mw_U_3rom_table(61827) <= "11101010"; + when 61828 => mw_U_3rom_table(61828) <= "00000001"; + when 61829 => mw_U_3rom_table(61829) <= "00110000"; + when 61830 => mw_U_3rom_table(61830) <= "11101010"; + when 61831 => mw_U_3rom_table(61831) <= "00000001"; + when 61832 => mw_U_3rom_table(61832) <= "11010000"; + when 61833 => mw_U_3rom_table(61833) <= "11101010"; + when 61834 => mw_U_3rom_table(61834) <= "00000001"; + when 61835 => mw_U_3rom_table(61835) <= "11110000"; + when 61836 => mw_U_3rom_table(61836) <= "11101010"; + when 61837 => mw_U_3rom_table(61837) <= "00000001"; + when 61838 => mw_U_3rom_table(61838) <= "10110000"; + when 61839 => mw_U_3rom_table(61839) <= "11101010"; + when 61840 => mw_U_3rom_table(61840) <= "00000001"; + when 61841 => mw_U_3rom_table(61841) <= "10010000"; + when 61842 => mw_U_3rom_table(61842) <= "01010110"; + when 61843 => mw_U_3rom_table(61843) <= "00000110"; + when 61844 => mw_U_3rom_table(61844) <= "01010110"; + when 61845 => mw_U_3rom_table(61845) <= "00010110"; + when 61846 => mw_U_3rom_table(61846) <= "00001010"; + when 61847 => mw_U_3rom_table(61847) <= "11110001"; + when 61848 => mw_U_3rom_table(61848) <= "01100011"; + when 61849 => mw_U_3rom_table(61849) <= "00101101"; + when 61850 => mw_U_3rom_table(61850) <= "01010110"; + when 61851 => mw_U_3rom_table(61851) <= "00100101"; + when 61852 => mw_U_3rom_table(61852) <= "00000000"; + when 61853 => mw_U_3rom_table(61853) <= "01010110"; + when 61854 => mw_U_3rom_table(61854) <= "00111001"; + when 61855 => mw_U_3rom_table(61855) <= "01010110"; + when 61856 => mw_U_3rom_table(61856) <= "01010110"; + when 61857 => mw_U_3rom_table(61857) <= "11011001"; + when 61858 => mw_U_3rom_table(61858) <= "01010110"; + when 61859 => mw_U_3rom_table(61859) <= "11010101"; + when 61860 => mw_U_3rom_table(61860) <= "01010110"; + when 61861 => mw_U_3rom_table(61861) <= "11010010"; + when 61862 => mw_U_3rom_table(61862) <= "01010110"; + when 61863 => mw_U_3rom_table(61863) <= "11010001"; + when 61864 => mw_U_3rom_table(61864) <= "01010110"; + when 61865 => mw_U_3rom_table(61865) <= "11000001"; + when 61866 => mw_U_3rom_table(61866) <= "01010110"; + when 61867 => mw_U_3rom_table(61867) <= "11001001"; + when 61868 => mw_U_3rom_table(61868) <= "10111000"; + when 61869 => mw_U_3rom_table(61869) <= "01011000"; + when 61870 => mw_U_3rom_table(61870) <= "11011000"; + when 61871 => mw_U_3rom_table(61871) <= "00011000"; + when 61872 => mw_U_3rom_table(61872) <= "00000000"; + when 61873 => mw_U_3rom_table(61873) <= "11110001"; + when 61874 => mw_U_3rom_table(61874) <= "01100011"; + when 61875 => mw_U_3rom_table(61875) <= "00101100"; + when 61876 => mw_U_3rom_table(61876) <= "01010110"; + when 61877 => mw_U_3rom_table(61877) <= "00100100"; + when 61878 => mw_U_3rom_table(61878) <= "01010110"; + when 61879 => mw_U_3rom_table(61879) <= "00110100"; + when 61880 => mw_U_3rom_table(61880) <= "01010110"; + when 61881 => mw_U_3rom_table(61881) <= "10001001"; + when 61882 => mw_U_3rom_table(61882) <= "11101010"; + when 61883 => mw_U_3rom_table(61883) <= "00000001"; + when 61884 => mw_U_3rom_table(61884) <= "01110000"; + when 61885 => mw_U_3rom_table(61885) <= "11101010"; + when 61886 => mw_U_3rom_table(61886) <= "00000001"; + when 61887 => mw_U_3rom_table(61887) <= "01010000"; + when 61888 => mw_U_3rom_table(61888) <= "11001010"; + when 61889 => mw_U_3rom_table(61889) <= "11110001"; + when 61890 => mw_U_3rom_table(61890) <= "01100011"; + when 61891 => mw_U_3rom_table(61891) <= "11001110"; + when 61892 => mw_U_3rom_table(61892) <= "01010110"; + when 61893 => mw_U_3rom_table(61893) <= "11000110"; + when 61894 => mw_U_3rom_table(61894) <= "11110001"; + when 61895 => mw_U_3rom_table(61895) <= "01100011"; + when 61896 => mw_U_3rom_table(61896) <= "11011110"; + when 61897 => mw_U_3rom_table(61897) <= "01010110"; + when 61898 => mw_U_3rom_table(61898) <= "11010110"; + when 61899 => mw_U_3rom_table(61899) <= "00111010"; + when 61900 => mw_U_3rom_table(61900) <= "11110001"; + when 61901 => mw_U_3rom_table(61901) <= "01100011"; + when 61902 => mw_U_3rom_table(61902) <= "11001100"; + when 61903 => mw_U_3rom_table(61903) <= "01010110"; + when 61904 => mw_U_3rom_table(61904) <= "11000100"; + when 61905 => mw_U_3rom_table(61905) <= "01010110"; + when 61906 => mw_U_3rom_table(61906) <= "11000000"; + when 61907 => mw_U_3rom_table(61907) <= "11110001"; + when 61908 => mw_U_3rom_table(61908) <= "01100011"; + when 61909 => mw_U_3rom_table(61909) <= "11101100"; + when 61910 => mw_U_3rom_table(61910) <= "01010110"; + when 61911 => mw_U_3rom_table(61911) <= "11100100"; + when 61912 => mw_U_3rom_table(61912) <= "01010110"; + when 61913 => mw_U_3rom_table(61913) <= "11100000"; + when 61914 => mw_U_3rom_table(61914) <= "11110001"; + when 61915 => mw_U_3rom_table(61915) <= "01100011"; + when 61916 => mw_U_3rom_table(61916) <= "11001101"; + when 61917 => mw_U_3rom_table(61917) <= "01010110"; + when 61918 => mw_U_3rom_table(61918) <= "11000101"; + when 61919 => mw_U_3rom_table(61919) <= "00000000"; + when 61920 => mw_U_3rom_table(61920) <= "11001000"; + when 61921 => mw_U_3rom_table(61921) <= "11101000"; + when 61922 => mw_U_3rom_table(61922) <= "11110001"; + when 61923 => mw_U_3rom_table(61923) <= "01100011"; + when 61924 => mw_U_3rom_table(61924) <= "11101110"; + when 61925 => mw_U_3rom_table(61925) <= "01010110"; + when 61926 => mw_U_3rom_table(61926) <= "11100110"; + when 61927 => mw_U_3rom_table(61927) <= "11110001"; + when 61928 => mw_U_3rom_table(61928) <= "01100011"; + when 61929 => mw_U_3rom_table(61929) <= "11111110"; + when 61930 => mw_U_3rom_table(61930) <= "01010110"; + when 61931 => mw_U_3rom_table(61931) <= "11110110"; + when 61932 => mw_U_3rom_table(61932) <= "00011010"; + when 61933 => mw_U_3rom_table(61933) <= "11110001"; + when 61934 => mw_U_3rom_table(61934) <= "01100011"; + when 61935 => mw_U_3rom_table(61935) <= "01001101"; + when 61936 => mw_U_3rom_table(61936) <= "01010110"; + when 61937 => mw_U_3rom_table(61937) <= "01000101"; + when 61938 => mw_U_3rom_table(61938) <= "00000000"; + when 61939 => mw_U_3rom_table(61939) <= "01010110"; + when 61940 => mw_U_3rom_table(61940) <= "01011001"; + when 61941 => mw_U_3rom_table(61941) <= "01010110"; + when 61942 => mw_U_3rom_table(61942) <= "01010101"; + when 61943 => mw_U_3rom_table(61943) <= "01010110"; + when 61944 => mw_U_3rom_table(61944) <= "01010010"; + when 61945 => mw_U_3rom_table(61945) <= "01010110"; + when 61946 => mw_U_3rom_table(61946) <= "01010001"; + when 61947 => mw_U_3rom_table(61947) <= "01010110"; + when 61948 => mw_U_3rom_table(61948) <= "01000001"; + when 61949 => mw_U_3rom_table(61949) <= "01010110"; + when 61950 => mw_U_3rom_table(61950) <= "01001001"; + when 61951 => mw_U_3rom_table(61951) <= "10001000"; + when 61952 => mw_U_3rom_table(61952) <= "01100011"; + when 61953 => mw_U_3rom_table(61953) <= "10101101"; + when 61954 => mw_U_3rom_table(61954) <= "01010110"; + when 61955 => mw_U_3rom_table(61955) <= "10100101"; + when 61956 => mw_U_3rom_table(61956) <= "00000000"; + when 61957 => mw_U_3rom_table(61957) <= "01010110"; + when 61958 => mw_U_3rom_table(61958) <= "10111001"; + when 61959 => mw_U_3rom_table(61959) <= "01010110"; + when 61960 => mw_U_3rom_table(61960) <= "10110101"; + when 61961 => mw_U_3rom_table(61961) <= "01010110"; + when 61962 => mw_U_3rom_table(61962) <= "10110010"; + when 61963 => mw_U_3rom_table(61963) <= "01010110"; + when 61964 => mw_U_3rom_table(61964) <= "10110001"; + when 61965 => mw_U_3rom_table(61965) <= "01010110"; + when 61966 => mw_U_3rom_table(61966) <= "10100001"; + when 61967 => mw_U_3rom_table(61967) <= "01010110"; + when 61968 => mw_U_3rom_table(61968) <= "10101001"; + when 61969 => mw_U_3rom_table(61969) <= "11110001"; + when 61970 => mw_U_3rom_table(61970) <= "01100011"; + when 61971 => mw_U_3rom_table(61971) <= "00100000"; + when 61972 => mw_U_3rom_table(61972) <= "00000000"; + when 61973 => mw_U_3rom_table(61973) <= "01010110"; + when 61974 => mw_U_3rom_table(61974) <= "00100000"; + when 61975 => mw_U_3rom_table(61975) <= "00000000"; + when 61976 => mw_U_3rom_table(61976) <= "01010110"; + when 61977 => mw_U_3rom_table(61977) <= "01001100"; + when 61978 => mw_U_3rom_table(61978) <= "00000000"; + when 61979 => mw_U_3rom_table(61979) <= "01010110"; + when 61980 => mw_U_3rom_table(61980) <= "01101100"; + when 61981 => mw_U_3rom_table(61981) <= "00000000"; + when 61982 => mw_U_3rom_table(61982) <= "01010110"; + when 61983 => mw_U_3rom_table(61983) <= "01111100"; + when 61984 => mw_U_3rom_table(61984) <= "01010110"; + when 61985 => mw_U_3rom_table(61985) <= "00000001"; + when 61986 => mw_U_3rom_table(61986) <= "01010110"; + when 61987 => mw_U_3rom_table(61987) <= "00001001"; + when 61988 => mw_U_3rom_table(61988) <= "11101010"; + when 61989 => mw_U_3rom_table(61989) <= "11110001"; + when 61990 => mw_U_3rom_table(61990) <= "01100011"; + when 61991 => mw_U_3rom_table(61991) <= "01001110"; + when 61992 => mw_U_3rom_table(61992) <= "01010110"; + when 61993 => mw_U_3rom_table(61993) <= "01000110"; + when 61994 => mw_U_3rom_table(61994) <= "01010110"; + when 61995 => mw_U_3rom_table(61995) <= "01010110"; + when 61996 => mw_U_3rom_table(61996) <= "01001010"; + when 61997 => mw_U_3rom_table(61997) <= "11110001"; + when 61998 => mw_U_3rom_table(61998) <= "01100011"; + when 61999 => mw_U_3rom_table(61999) <= "10101100"; + when 62000 => mw_U_3rom_table(62000) <= "01010110"; + when 62001 => mw_U_3rom_table(62001) <= "10100100"; + when 62002 => mw_U_3rom_table(62002) <= "01010110"; + when 62003 => mw_U_3rom_table(62003) <= "10110100"; + when 62004 => mw_U_3rom_table(62004) <= "01010110"; + when 62005 => mw_U_3rom_table(62005) <= "10100000"; + when 62006 => mw_U_3rom_table(62006) <= "11110001"; + when 62007 => mw_U_3rom_table(62007) <= "01100011"; + when 62008 => mw_U_3rom_table(62008) <= "10101110"; + when 62009 => mw_U_3rom_table(62009) <= "01010110"; + when 62010 => mw_U_3rom_table(62010) <= "10100110"; + when 62011 => mw_U_3rom_table(62011) <= "01010110"; + when 62012 => mw_U_3rom_table(62012) <= "10110110"; + when 62013 => mw_U_3rom_table(62013) <= "01010110"; + when 62014 => mw_U_3rom_table(62014) <= "10100010"; + when 62015 => mw_U_3rom_table(62015) <= "11110001"; + when 62016 => mw_U_3rom_table(62016) <= "11110001"; + when 62017 => mw_U_3rom_table(62017) <= "01100011"; + when 62018 => mw_U_3rom_table(62018) <= "01111110"; + when 62019 => mw_U_3rom_table(62019) <= "01010110"; + when 62020 => mw_U_3rom_table(62020) <= "01110110"; + when 62021 => mw_U_3rom_table(62021) <= "01101010"; + when 62022 => mw_U_3rom_table(62022) <= "11110001"; + when 62023 => mw_U_3rom_table(62023) <= "01100011"; + when 62024 => mw_U_3rom_table(62024) <= "00101110"; + when 62025 => mw_U_3rom_table(62025) <= "01010110"; + when 62026 => mw_U_3rom_table(62026) <= "00100110"; + when 62027 => mw_U_3rom_table(62027) <= "01010110"; + when 62028 => mw_U_3rom_table(62028) <= "00110110"; + when 62029 => mw_U_3rom_table(62029) <= "00101010"; + when 62030 => mw_U_3rom_table(62030) <= "00101000"; + when 62031 => mw_U_3rom_table(62031) <= "01101000"; + when 62032 => mw_U_3rom_table(62032) <= "00001000"; + when 62033 => mw_U_3rom_table(62033) <= "01001000"; + when 62034 => mw_U_3rom_table(62034) <= "11110001"; + when 62035 => mw_U_3rom_table(62035) <= "01100011"; + when 62036 => mw_U_3rom_table(62036) <= "00001101"; + when 62037 => mw_U_3rom_table(62037) <= "01010110"; + when 62038 => mw_U_3rom_table(62038) <= "00000101"; + when 62039 => mw_U_3rom_table(62039) <= "00000000"; + when 62040 => mw_U_3rom_table(62040) <= "01010110"; + when 62041 => mw_U_3rom_table(62041) <= "00011001"; + when 62042 => mw_U_3rom_table(62042) <= "01010110"; + when 62043 => mw_U_3rom_table(62043) <= "00010101"; + when 62044 => mw_U_3rom_table(62044) <= "01010110"; + when 62045 => mw_U_3rom_table(62045) <= "00010010"; + when 62046 => mw_U_3rom_table(62046) <= "01010110"; + when 62047 => mw_U_3rom_table(62047) <= "00010001"; + when 62048 => mw_U_3rom_table(62048) <= "01010110"; + when 62049 => mw_U_3rom_table(62049) <= "10010001"; + when 62050 => mw_U_3rom_table(62050) <= "01010110"; + when 62051 => mw_U_3rom_table(62051) <= "10000001"; + when 62052 => mw_U_3rom_table(62052) <= "01111000"; + when 62053 => mw_U_3rom_table(62053) <= "11111000"; + when 62054 => mw_U_3rom_table(62054) <= "00111000"; + when 62055 => mw_U_3rom_table(62055) <= "11110001"; + when 62056 => mw_U_3rom_table(62056) <= "01100011"; + when 62057 => mw_U_3rom_table(62057) <= "11101101"; + when 62058 => mw_U_3rom_table(62058) <= "01010110"; + when 62059 => mw_U_3rom_table(62059) <= "11100101"; + when 62060 => mw_U_3rom_table(62060) <= "00000000"; + when 62061 => mw_U_3rom_table(62061) <= "01010110"; + when 62062 => mw_U_3rom_table(62062) <= "11111001"; + when 62063 => mw_U_3rom_table(62063) <= "01010110"; + when 62064 => mw_U_3rom_table(62064) <= "11110101"; + when 62065 => mw_U_3rom_table(62065) <= "01010110"; + when 62066 => mw_U_3rom_table(62066) <= "11110010"; + when 62067 => mw_U_3rom_table(62067) <= "01010110"; + when 62068 => mw_U_3rom_table(62068) <= "11110001"; + when 62069 => mw_U_3rom_table(62069) <= "01010110"; + when 62070 => mw_U_3rom_table(62070) <= "11100001"; + when 62071 => mw_U_3rom_table(62071) <= "01010110"; + when 62072 => mw_U_3rom_table(62072) <= "11101001"; + when 62073 => mw_U_3rom_table(62073) <= "01100000"; + when 62074 => mw_U_3rom_table(62074) <= "01000000"; + when 62075 => mw_U_3rom_table(62075) <= "11110001"; + when 62076 => mw_U_3rom_table(62076) <= "01100011"; + when 62077 => mw_U_3rom_table(62077) <= "01101110"; + when 62078 => mw_U_3rom_table(62078) <= "01010110"; + when 62079 => mw_U_3rom_table(62079) <= "01100110"; + when 62080 => mw_U_3rom_table(62080) <= "10011000"; + when 62081 => mw_U_3rom_table(62081) <= "10011010"; + when 62082 => mw_U_3rom_table(62082) <= "10001010"; + when 62083 => mw_U_3rom_table(62083) <= "10111010"; + when 62084 => mw_U_3rom_table(62084) <= "10101000"; + when 62085 => mw_U_3rom_table(62085) <= "10101010"; + when 62086 => mw_U_3rom_table(62086) <= "11110001"; + when 62087 => mw_U_3rom_table(62087) <= "01100011"; + when 62088 => mw_U_3rom_table(62088) <= "10001100"; + when 62089 => mw_U_3rom_table(62089) <= "01010110"; + when 62090 => mw_U_3rom_table(62090) <= "10000100"; + when 62091 => mw_U_3rom_table(62091) <= "01010110"; + when 62092 => mw_U_3rom_table(62092) <= "10010100"; + when 62093 => mw_U_3rom_table(62093) <= "11110001"; + when 62094 => mw_U_3rom_table(62094) <= "01100011"; + when 62095 => mw_U_3rom_table(62095) <= "10001110"; + when 62096 => mw_U_3rom_table(62096) <= "01010110"; + when 62097 => mw_U_3rom_table(62097) <= "10000110"; + when 62098 => mw_U_3rom_table(62098) <= "01010110"; + when 62099 => mw_U_3rom_table(62099) <= "10010110"; + when 62100 => mw_U_3rom_table(62100) <= "11110001"; + when 62101 => mw_U_3rom_table(62101) <= "01100011"; + when 62102 => mw_U_3rom_table(62102) <= "10001101"; + when 62103 => mw_U_3rom_table(62103) <= "01010110"; + when 62104 => mw_U_3rom_table(62104) <= "10000101"; + when 62105 => mw_U_3rom_table(62105) <= "00000000"; + when 62106 => mw_U_3rom_table(62106) <= "01010110"; + when 62107 => mw_U_3rom_table(62107) <= "10011001"; + when 62108 => mw_U_3rom_table(62108) <= "01010110"; + when 62109 => mw_U_3rom_table(62109) <= "10010101"; + when 62110 => mw_U_3rom_table(62110) <= "01010110"; + when 62111 => mw_U_3rom_table(62111) <= "10010010"; + when 62112 => mw_U_3rom_table(62112) <= "11100010"; + when 62113 => mw_U_3rom_table(62113) <= "01010110"; + when 62114 => mw_U_3rom_table(62114) <= "10011111"; + when 62115 => mw_U_3rom_table(62115) <= "11100101"; + when 62116 => mw_U_3rom_table(62116) <= "01010110"; + when 62117 => mw_U_3rom_table(62117) <= "10001111"; + when 62118 => mw_U_3rom_table(62118) <= "11101000"; + when 62119 => mw_U_3rom_table(62119) <= "01010110"; + when 62120 => mw_U_3rom_table(62120) <= "01111111"; + when 62121 => mw_U_3rom_table(62121) <= "11101011"; + when 62122 => mw_U_3rom_table(62122) <= "01010110"; + when 62123 => mw_U_3rom_table(62123) <= "01101111"; + when 62124 => mw_U_3rom_table(62124) <= "11101110"; + when 62125 => mw_U_3rom_table(62125) <= "01010110"; + when 62126 => mw_U_3rom_table(62126) <= "01011111"; + when 62127 => mw_U_3rom_table(62127) <= "11110001"; + when 62128 => mw_U_3rom_table(62128) <= "01010110"; + when 62129 => mw_U_3rom_table(62129) <= "01001111"; + when 62130 => mw_U_3rom_table(62130) <= "11110100"; + when 62131 => mw_U_3rom_table(62131) <= "01010110"; + when 62132 => mw_U_3rom_table(62132) <= "00111111"; + when 62133 => mw_U_3rom_table(62133) <= "11110111"; + when 62134 => mw_U_3rom_table(62134) <= "01010110"; + when 62135 => mw_U_3rom_table(62135) <= "00101111"; + when 62136 => mw_U_3rom_table(62136) <= "11111010"; + when 62137 => mw_U_3rom_table(62137) <= "01010110"; + when 62138 => mw_U_3rom_table(62138) <= "00011111"; + when 62139 => mw_U_3rom_table(62139) <= "11111101"; + when 62140 => mw_U_3rom_table(62140) <= "01010110"; + when 62141 => mw_U_3rom_table(62141) <= "00001111"; + when 62142 => mw_U_3rom_table(62142) <= "00000000"; + when 62143 => mw_U_3rom_table(62143) <= "10000000"; + when 62144 => mw_U_3rom_table(62144) <= "01000111"; + when 62145 => mw_U_3rom_table(62145) <= "01010110"; + when 62146 => mw_U_3rom_table(62146) <= "00110111"; + when 62147 => mw_U_3rom_table(62147) <= "01010110"; + when 62148 => mw_U_3rom_table(62148) <= "00100111"; + when 62149 => mw_U_3rom_table(62149) <= "01010110"; + when 62150 => mw_U_3rom_table(62150) <= "00010111"; + when 62151 => mw_U_3rom_table(62151) <= "01010110"; + when 62152 => mw_U_3rom_table(62152) <= "00000111"; + when 62153 => mw_U_3rom_table(62153) <= "01111010"; + when 62154 => mw_U_3rom_table(62154) <= "11111010"; + when 62155 => mw_U_3rom_table(62155) <= "01011010"; + when 62156 => mw_U_3rom_table(62156) <= "11011010"; + when 62157 => mw_U_3rom_table(62157) <= "00000010"; + when 62158 => mw_U_3rom_table(62158) <= "11010000"; + when 62159 => mw_U_3rom_table(62159) <= "01010110"; + when 62160 => mw_U_3rom_table(62160) <= "11111111"; + when 62161 => mw_U_3rom_table(62161) <= "11010011"; + when 62162 => mw_U_3rom_table(62162) <= "01010110"; + when 62163 => mw_U_3rom_table(62163) <= "11101111"; + when 62164 => mw_U_3rom_table(62164) <= "11010110"; + when 62165 => mw_U_3rom_table(62165) <= "01010110"; + when 62166 => mw_U_3rom_table(62166) <= "11011111"; + when 62167 => mw_U_3rom_table(62167) <= "11011001"; + when 62168 => mw_U_3rom_table(62168) <= "01010110"; + when 62169 => mw_U_3rom_table(62169) <= "11001111"; + when 62170 => mw_U_3rom_table(62170) <= "11011100"; + when 62171 => mw_U_3rom_table(62171) <= "01010110"; + when 62172 => mw_U_3rom_table(62172) <= "10111111"; + when 62173 => mw_U_3rom_table(62173) <= "11011111"; + when 62174 => mw_U_3rom_table(62174) <= "01010110"; + when 62175 => mw_U_3rom_table(62175) <= "10101111"; + when 62176 => mw_U_3rom_table(62176) <= "01010110"; + when 62177 => mw_U_3rom_table(62177) <= "00010100"; + when 62178 => mw_U_3rom_table(62178) <= "11110001"; + when 62179 => mw_U_3rom_table(62179) <= "01100011"; + when 62180 => mw_U_3rom_table(62180) <= "10011100"; + when 62181 => mw_U_3rom_table(62181) <= "01010110"; + when 62182 => mw_U_3rom_table(62182) <= "01100100"; + when 62183 => mw_U_3rom_table(62183) <= "01010110"; + when 62184 => mw_U_3rom_table(62184) <= "01110100"; + when 62185 => mw_U_3rom_table(62185) <= "01010110"; + when 62186 => mw_U_3rom_table(62186) <= "11110111"; + when 62187 => mw_U_3rom_table(62187) <= "01010110"; + when 62188 => mw_U_3rom_table(62188) <= "11100111"; + when 62189 => mw_U_3rom_table(62189) <= "01010110"; + when 62190 => mw_U_3rom_table(62190) <= "11010111"; + when 62191 => mw_U_3rom_table(62191) <= "01010110"; + when 62192 => mw_U_3rom_table(62192) <= "11000111"; + when 62193 => mw_U_3rom_table(62193) <= "01010110"; + when 62194 => mw_U_3rom_table(62194) <= "10110111"; + when 62195 => mw_U_3rom_table(62195) <= "01010110"; + when 62196 => mw_U_3rom_table(62196) <= "10100111"; + when 62197 => mw_U_3rom_table(62197) <= "01010110"; + when 62198 => mw_U_3rom_table(62198) <= "10010111"; + when 62199 => mw_U_3rom_table(62199) <= "01010110"; + when 62200 => mw_U_3rom_table(62200) <= "10000111"; + when 62201 => mw_U_3rom_table(62201) <= "01010110"; + when 62202 => mw_U_3rom_table(62202) <= "01110111"; + when 62203 => mw_U_3rom_table(62203) <= "01010110"; + when 62204 => mw_U_3rom_table(62204) <= "01100111"; + when 62205 => mw_U_3rom_table(62205) <= "01010110"; + when 62206 => mw_U_3rom_table(62206) <= "01010111"; + when 62207 => mw_U_3rom_table(62207) <= "01010110"; + when 62208 => mw_U_3rom_table(62208) <= "11111111"; + when 62209 => mw_U_3rom_table(62209) <= "11111111"; + when 62210 => mw_U_3rom_table(62210) <= "11111111"; + when 62211 => mw_U_3rom_table(62211) <= "11111111"; + when 62212 => mw_U_3rom_table(62212) <= "11111111"; + when 62213 => mw_U_3rom_table(62213) <= "11111111"; + when 62214 => mw_U_3rom_table(62214) <= "11111111"; + when 62215 => mw_U_3rom_table(62215) <= "11111111"; + when 62216 => mw_U_3rom_table(62216) <= "11111111"; + when 62217 => mw_U_3rom_table(62217) <= "11111111"; + when 62218 => mw_U_3rom_table(62218) <= "11111111"; + when 62219 => mw_U_3rom_table(62219) <= "11111111"; + when 62220 => mw_U_3rom_table(62220) <= "11111111"; + when 62221 => mw_U_3rom_table(62221) <= "11111111"; + when 62222 => mw_U_3rom_table(62222) <= "11111111"; + when 62223 => mw_U_3rom_table(62223) <= "11111111"; + when 62224 => mw_U_3rom_table(62224) <= "11111111"; + when 62225 => mw_U_3rom_table(62225) <= "11111111"; + when 62226 => mw_U_3rom_table(62226) <= "11111111"; + when 62227 => mw_U_3rom_table(62227) <= "11111111"; + when 62228 => mw_U_3rom_table(62228) <= "11111111"; + when 62229 => mw_U_3rom_table(62229) <= "11111111"; + when 62230 => mw_U_3rom_table(62230) <= "11111111"; + when 62231 => mw_U_3rom_table(62231) <= "11111111"; + when 62232 => mw_U_3rom_table(62232) <= "11111111"; + when 62233 => mw_U_3rom_table(62233) <= "11111111"; + when 62234 => mw_U_3rom_table(62234) <= "11111111"; + when 62235 => mw_U_3rom_table(62235) <= "11111111"; + when 62236 => mw_U_3rom_table(62236) <= "11111111"; + when 62237 => mw_U_3rom_table(62237) <= "11111111"; + when 62238 => mw_U_3rom_table(62238) <= "01010110"; + when 62239 => mw_U_3rom_table(62239) <= "00000100"; + when 65504 => mw_U_3rom_table(65504) <= "11111111"; + when 65505 => mw_U_3rom_table(65505) <= "11111111"; + when 65506 => mw_U_3rom_table(65506) <= "11110000"; + when 65507 => mw_U_3rom_table(65507) <= "00000000"; + when 65508 => mw_U_3rom_table(65508) <= "11111111"; + when 65509 => mw_U_3rom_table(65509) <= "11111111"; + when 65510 => mw_U_3rom_table(65510) <= "11111111"; + when 65511 => mw_U_3rom_table(65511) <= "11111111"; + when 65512 => mw_U_3rom_table(65512) <= "11111111"; + when 65513 => mw_U_3rom_table(65513) <= "11111111"; + when 65514 => mw_U_3rom_table(65514) <= "11111111"; + when 65515 => mw_U_3rom_table(65515) <= "11111111"; + when 65516 => mw_U_3rom_table(65516) <= "11111111"; + when 65517 => mw_U_3rom_table(65517) <= "11111111"; + when 65518 => mw_U_3rom_table(65518) <= "11111111"; + when 65519 => mw_U_3rom_table(65519) <= "11111111"; + when 65520 => mw_U_3rom_table(65520) <= "11111111"; + when 65521 => mw_U_3rom_table(65521) <= "11111111"; + when 65522 => mw_U_3rom_table(65522) <= "11111111"; + when 65523 => mw_U_3rom_table(65523) <= "11111111"; + when 65524 => mw_U_3rom_table(65524) <= "11111111"; + when 65525 => mw_U_3rom_table(65525) <= "11111111"; + when 65526 => mw_U_3rom_table(65526) <= "11111111"; + when 65527 => mw_U_3rom_table(65527) <= "11111111"; + when 65528 => mw_U_3rom_table(65528) <= "11111111"; + when 65529 => mw_U_3rom_table(65529) <= "11111111"; + when 65530 => mw_U_3rom_table(65530) <= "11111111"; + when 65531 => mw_U_3rom_table(65531) <= "11111111"; + when 65532 => mw_U_3rom_table(65532) <= "11111111"; + when 65533 => mw_U_3rom_table(65533) <= "11111111"; + when 65534 => mw_U_3rom_table(65534) <= "11111111"; + when 65535 => mw_U_3rom_table(65535) <= "11111111"; + when others => mw_U_3rom_table(mw_U_3addr_int) <= (others => 'X') ; + end case; + end process ; + + u_3rom_read_proc : process ( clk1 ) + begin + if (clk1'event and clk1='1') then + dout1 <= mw_U_3rom_table(mw_U_3addr_int); + end if; + end process ; + + -- Instance port mappings. + U_0 : R6502_TC + port map ( + clk_clk_i => clk, + d_i => RAM_DOUT_internal, + irq_n_i => IRQn, + nmi_n_i => NMIn, + rdy_i => RDY, + rst_rst_n_i => RSTn, + so_n_i => so_n_i, + a_o => A_internal, + d_o => CPU_DOUT_internal, + rd_o => RD, + sync_o => SYNC, + wr_n_o => open, + wr_o => WR_internal + ); + + -- Implicit buffered output assignments + CPU_DOUT <= CPU_DOUT_internal; + RAM_DOUT <= RAM_DOUT_internal; + WR <= WR_internal; + A <= A_internal; + +end struct;
vhdl/testbench.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/add_sub.vhd =================================================================== --- vhdl/add_sub.vhd (nonexistent) +++ vhdl/add_sub.vhd (revision 18) @@ -0,0 +1,137 @@ +-- VHDL Entity R6502_TC.ADD_SUB.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:54 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity ADD_SUB is + port( + ch_a_i : in std_logic_vector ( 7 downto 0 ) := X"00"; + ch_b_i : in std_logic_vector ( 7 downto 0 ) := X"00"; + reg_0flag_i : in std_logic := '0'; + reg_7flag_core_i : in std_logic := '0'; + sel : in std_logic_vector ( 1 downto 0 ) := "00"; + q_a_o : out std_logic_vector ( 7 downto 0 ) := X"00"; + reg_0flag_o : out std_logic := '0'; + reg_6flag_o : out std_logic := '0'; + zw_alu : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu1 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu2 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu3 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu4 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu5 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu6 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00" + ); + +-- Declarations + +end ADD_SUB ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- +-- Title: Adder and Substractor +-- Path: R6502_TC/ADD_SUB/flow +-- Edited: by eda on 08 Apr 2008 +-- +-- VHDL Architecture R6502_TC.ADD_SUB.flow +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:54 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +architecture flow of ADD_SUB is + +begin + + ----------------------------------------------------------------- + process0_proc : process (ch_a_i, ch_b_i, reg_0flag_i, reg_7flag_core_i, sel, zw_alu, zw_alu1, zw_alu2, zw_alu3, zw_alu4, zw_alu5, zw_alu6) + ----------------------------------------------------------------- + begin + case sel(1 downto 0) is + when "01" => + reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7); + reg_0flag_o <= zw_ALU4(4); + q_a_o <= zw_ALU(7 downto 0); + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & + (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & + (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & ch_a_i(7 downto 4)) + unsigned + ('0' & ch_b_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & ch_a_i(3 downto 0)) + unsigned + ('0' & ch_b_i(3 downto 0)) + reg_0flag_i; + when "00" => + reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7); + reg_0flag_o <= zw_ALU(8); + q_a_o <= zw_ALU(7 downto 0); + zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & ch_b_i) + reg_0flag_i; + when "10" => + reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7); + reg_0flag_o <= zw_ALU(8); + q_a_o <= zw_ALU(7 downto 0); + zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & NOT (ch_b_i)) + reg_0flag_i; + when "11" => + reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7); + reg_0flag_o <= zw_ALU2(4); + q_a_o <= zw_ALU(7 downto 0); + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & ch_a_i(7 downto 4)) + unsigned + ('0' & NOT (ch_b_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & ch_a_i(3 downto 0)) + unsigned + ('0' & NOT (ch_b_i(3 downto 0))) + reg_0flag_i; + when others => + reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7); + reg_0flag_o <= zw_ALU(8); + q_a_o <= zw_ALU(7 downto 0); + zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & ch_b_i) + reg_0flag_i; + end case; + end process process0_proc; + + +end flow;
vhdl/add_sub.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/alu.vhd =================================================================== --- vhdl/alu.vhd (nonexistent) +++ vhdl/alu.vhd (revision 18) @@ -0,0 +1,210 @@ +-- VHDL Entity R6502_TC.ALU.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:54 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity ALU is + port( + ch_a_i : in std_logic_vector (7 downto 0); + ch_b_i : in std_logic_vector (7 downto 0); + reg_0flag_core_i : in std_logic; + reg_3flag_core_i : in std_logic; + reg_7flag_core_i : in std_logic; + sel_alu_as_i : in std_logic; + sel_alu_out_i : in std_logic_vector (2 downto 0); + d_alu_o : out std_logic_vector (7 downto 0); + reg_0flag_o : out std_logic; + reg_1flag_o : out std_logic; + reg_6flag_o : out std_logic; + reg_7flag_o : out std_logic + ); + +-- Declarations + +end ALU ; + +-- Jens-D. Gutschmidt Project: R6502_TC +-- scantara2003@yahoo.de +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG +-- +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or any later version. +-- +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License along with this program. If not, see . +-- +-- CVS Revisins History +-- +-- $Log: not supported by cvs2svn $ +-- +-- Title: ALU +-- Path: R6502_TC/ALU/struct +-- Edited: by eda on 08 Apr 2008 +-- +-- VHDL Architecture R6502_TC.ALU.struct +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:54 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library R6502_TC; + +architecture struct of ALU is + + -- Architecture declarations + + -- Internal signal declarations + signal din : std_logic; + signal din0 : std_logic; + signal din1 : std_logic; + signal din2 : std_logic; + signal din3 : std_logic; + signal dout : std_logic; + signal q_a : std_logic_vector(7 downto 0); + signal q_and : std_logic_vector(7 downto 0); + signal q_aneg : std_logic_vector(7 downto 0); + signal q_bneg : std_logic_vector(7 downto 0); + signal q_or : std_logic_vector(7 downto 0); + signal q_xor : std_logic_vector(7 downto 0); + signal sel : std_logic_vector(1 downto 0); + signal val_one : std_logic_vector(7 downto 0); + signal val_two : std_logic_vector(7 downto 0); + signal val_zero : std_logic_vector(7 downto 0); + + -- Implicit buffer signal declarations + signal d_alu_o_internal : std_logic_vector (7 downto 0); + + + -- Component Declarations + component ADD_SUB + port ( + ch_a_i : in std_logic_vector ( 7 downto 0 ) := X"00"; + ch_b_i : in std_logic_vector ( 7 downto 0 ) := X"00"; + reg_0flag_i : in std_logic := '0'; + reg_7flag_core_i : in std_logic := '0'; + sel : in std_logic_vector ( 1 downto 0 ) := "00"; + q_a_o : out std_logic_vector ( 7 downto 0 ) := X"00"; + reg_0flag_o : out std_logic := '0'; + reg_6flag_o : out std_logic := '0'; + zw_alu : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu1 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu2 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu3 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu4 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu5 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00"; + zw_alu6 : inout std_logic_vector ( 8 downto 0 ) := '0' & X"00" + ); + end component; + + -- Optional embedded configurations + -- pragma synthesis_off + for all : ADD_SUB use entity R6502_TC.ADD_SUB; + -- pragma synthesis_on + + +begin + -- Architecture concurrent statements + -- HDL Embedded Text Block 3 eb3 + -- eb1 1 + val_zero (7 downto 0) <= X"00"; + val_one (7 downto 0) <= X"01"; + val_two (7 downto 0) <= X"02"; + sel(0) <= reg_3flag_core_i AND sel_alu_out_i(0); + sel(1) <= sel_alu_as_i; + + + -- ModuleWare code(v1.9) for instance 'U_3' of 'inv' + q_aneg <= not(ch_a_i); + + -- ModuleWare code(v1.9) for instance 'U_4' of 'inv' + q_bneg <= not(ch_b_i); + + -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' + reg_1flag_o <= not(din); + + -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' + reg_7flag_o <= not(din1); + + -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' + din1 <= not(d_alu_o_internal(7)); + + -- ModuleWare code(v1.9) for instance 'U_14' of 'inv' + din3 <= not(sel_alu_out_i(0)); + + -- ModuleWare code(v1.9) for instance 'U_5' of 'mux' + u_5combo_proc: process(q_and, q_or, q_xor, q_aneg, q_bneg, q_a, + val_zero, sel_alu_out_i) + begin + case sel_alu_out_i is + when "000" => d_alu_o_internal <= q_and; + when "001" => d_alu_o_internal <= q_or; + when "010" => d_alu_o_internal <= q_xor; + when "011" => d_alu_o_internal <= q_aneg; + when "100" => d_alu_o_internal <= q_bneg; + when "101" => d_alu_o_internal <= q_a; + when "110" => d_alu_o_internal <= q_a; + when "111" => d_alu_o_internal <= val_zero; + when others => d_alu_o_internal <= (others => 'X'); + end case; + end process u_5combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_7' of 'por' + din <= d_alu_o_internal(0) or d_alu_o_internal(1) or d_alu_o_internal(2) or d_alu_o_internal(3) or d_alu_o_internal(4) or d_alu_o_internal(5) or d_alu_o_internal(6) or d_alu_o_internal(7); + + -- ModuleWare code(v1.9) for instance 'U_0' of 'sand' + q_and <= ch_a_i and ch_b_i; + + -- ModuleWare code(v1.9) for instance 'U_11' of 'sand' + din0 <= sel_alu_out_i(0) and reg_0flag_core_i; + + -- ModuleWare code(v1.9) for instance 'U_13' of 'sand' + din2 <= din3 and sel_alu_as_i; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'sor' + q_or <= ch_a_i or ch_b_i; + + -- ModuleWare code(v1.9) for instance 'U_12' of 'sor' + dout <= din0 or din2; + + -- ModuleWare code(v1.9) for instance 'U_2' of 'sxor' + q_xor <= ch_a_i xor ch_b_i; + + -- Instance port mappings. + U_6 : ADD_SUB + port map ( + ch_a_i => ch_a_i, + ch_b_i => ch_b_i, + reg_0flag_i => dout, + reg_7flag_core_i => reg_7flag_core_i, + sel => sel, + q_a_o => q_a, + reg_0flag_o => reg_0flag_o, + reg_6flag_o => reg_6flag_o, + zw_alu => open, + zw_alu1 => open, + zw_alu2 => open, + zw_alu3 => open, + zw_alu4 => open, + zw_alu5 => open, + zw_alu6 => open + ); + + -- Implicit buffered output assignments + d_alu_o <= d_alu_o_internal; + +end struct;
vhdl/alu.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: vhdl/fsm_core_v2_0.vhd =================================================================== --- vhdl/fsm_core_v2_0.vhd (nonexistent) +++ vhdl/fsm_core_v2_0.vhd (revision 18) @@ -0,0 +1,5446 @@ +-- VHDL Entity R6502_TC.fsm_core_V2_0.symbol +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:55 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +entity fsm_core_V2_0 is + port( + adr_nxt_pc_i : in std_logic_vector (15 downto 0); + adr_nxt_sp_i : in std_logic_vector (15 downto 0); + adr_pc_i : in std_logic_vector (15 downto 0); + adr_sp_i : in std_logic_vector (15 downto 0); + clk_clk_i : in std_logic; + cout_pc_i : in std_logic; + d_alu_i : in std_logic_vector ( 7 downto 0 ); + d_i : in std_logic_vector ( 7 downto 0 ); + d_regs_out_i : in std_logic_vector ( 7 downto 0 ); + irq_n_i : in std_logic; + nmi_i : in std_logic; + q_a_i : in std_logic_vector ( 7 downto 0 ); + q_x_i : in std_logic_vector ( 7 downto 0 ); + q_y_i : in std_logic_vector ( 7 downto 0 ); + rdy_i : in std_logic; + reg_0flag_i : in std_logic; + reg_1flag_i : in std_logic; + reg_6flag_i : in std_logic; + reg_7flag_i : in std_logic; + rst_rst_n_i : in std_logic; + so_n_i : in std_logic; + a_o : out std_logic_vector (15 downto 0); + adr_o : out std_logic_vector (15 downto 0); + ch_a_o : out std_logic_vector ( 7 downto 0 ); + ch_b_o : out std_logic_vector ( 7 downto 0 ); + d_o : out std_logic_vector ( 7 downto 0 ); + d_regs_in_o : out std_logic_vector ( 7 downto 0 ); + ld_o : out std_logic_vector ( 1 downto 0 ); + ld_pc_o : out std_logic; + ld_sp_o : out std_logic; + load_regs_o : out std_logic; + offset_o : out std_logic_vector ( 15 downto 0 ); + rd_o : out std_logic; + reg_0flag_o : out std_logic; + reg_1flag_o : out std_logic; + reg_3flag_o : out std_logic; + reg_7flag_o : out std_logic; + sync_o : out std_logic; + wr_n_o : out std_logic; + wr_o : out std_logic; + sel_alu_as_o_i : inout std_logic; + sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 ); + sel_pc_as_o_i : inout std_logic; + sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 ); + sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 ); + sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 ); + sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 ); + sel_reg_o_i : inout std_logic_vector ( 1 downto 0 ); + sel_sp_as_o_i : inout std_logic; + sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 ); + sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 ) + ); + +-- Declarations + +end fsm_core_V2_0 ; + +-- Jens-D. Gutschmidt Project: R6502_TC + +-- scantara2003@yahoo.de + +-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG + +-- + +-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by + +-- the Free Software Foundation, either version 3 of the License, or any later version. + +-- + +-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + +-- + +-- You should have received a copy of the GNU General Public License along with this program. If not, see . + +-- + +-- CVS Revisins History + +-- + +-- $Log: not supported by cvs2svn $ + +-- + +-- Title: FSM for all op codes + +-- Path: R6502_TC/fsm_core_V2_0/fsm + +-- Edited: by eda on 08 Apr 2008 + +-- +-- VHDL Architecture R6502_TC.fsm_core_V2_0.fsm +-- +-- Created: +-- by - eda.UNKNOWN (ENTWICKL4-XP-PR) +-- at - 19:06:56 08.04.2008 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +architecture fsm of fsm_core_V2_0 is + + -- Architecture Declarations + signal reg_F : std_logic_vector( 7 DOWNTO 0 ); + signal reg_PC : std_logic_vector(15 DOWNTO 0); + signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 ); + signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); + signal sig_PC : std_logic_vector(15 DOWNTO 0); + signal sig_RD : std_logic; + signal sig_RWn : std_logic; + signal sig_SYNC : std_logic; + signal sig_WR : std_logic; + signal zw_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 ); + signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); + signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); + signal zw_REG_NMI : std_logic; + signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); + signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); + signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); + signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); + signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); + + subtype state_type is + std_logic_vector(7 downto 0); + + -- State vector declaration + attribute state_vector : string; + attribute state_vector of fsm : architecture is "current_state"; + + -- Hard encoding + constant FETCH : state_type := "00000000"; + constant s1 : state_type := "00000001"; + constant s2 : state_type := "00000011"; + constant s5 : state_type := "00000010"; + constant s3 : state_type := "00000110"; + constant s4 : state_type := "00000111"; + constant s12 : state_type := "00000101"; + constant s16 : state_type := "00000100"; + constant s17 : state_type := "00001100"; + constant s24 : state_type := "00001101"; + constant s25 : state_type := "00001111"; + constant s271 : state_type := "00001110"; + constant s273 : state_type := "00001010"; + constant s304 : state_type := "00001011"; + constant s307 : state_type := "00001001"; + constant s177 : state_type := "00001000"; + constant s180 : state_type := "00011000"; + constant s181 : state_type := "00011001"; + constant s182 : state_type := "00011011"; + constant s183 : state_type := "00011010"; + constant s184 : state_type := "00011110"; + constant s185 : state_type := "00011111"; + constant s186 : state_type := "00011101"; + constant s187 : state_type := "00011100"; + constant s188 : state_type := "00010100"; + constant s189 : state_type := "00010101"; + constant s190 : state_type := "00010111"; + constant s191 : state_type := "00010110"; + constant s192 : state_type := "00010010"; + constant s193 : state_type := "00010011"; + constant s377 : state_type := "00010001"; + constant s381 : state_type := "00010000"; + constant s378 : state_type := "00110000"; + constant s382 : state_type := "00110001"; + constant s379 : state_type := "00110011"; + constant s383 : state_type := "00110010"; + constant s384 : state_type := "00110110"; + constant s380 : state_type := "00110111"; + constant s385 : state_type := "00110101"; + constant s386 : state_type := "00110100"; + constant s387 : state_type := "00111100"; + constant s388 : state_type := "00111101"; + constant s389 : state_type := "00111111"; + constant s391 : state_type := "00111110"; + constant s392 : state_type := "00111010"; + constant s390 : state_type := "00111011"; + constant s393 : state_type := "00111001"; + constant s394 : state_type := "00111000"; + constant s395 : state_type := "00101000"; + constant s396 : state_type := "00101001"; + constant s397 : state_type := "00101011"; + constant s398 : state_type := "00101010"; + constant s399 : state_type := "00101110"; + constant s400 : state_type := "00101111"; + constant s401 : state_type := "00101101"; + constant s526 : state_type := "00101100"; + constant s527 : state_type := "00100100"; + constant s528 : state_type := "00100101"; + constant s529 : state_type := "00100111"; + constant s530 : state_type := "00100110"; + constant s531 : state_type := "00100010"; + constant s544 : state_type := "00100011"; + constant s545 : state_type := "00100001"; + constant s546 : state_type := "00100000"; + constant s547 : state_type := "01100000"; + constant s549 : state_type := "01100001"; + constant s550 : state_type := "01100011"; + constant s404 : state_type := "01100010"; + constant s556 : state_type := "01100110"; + constant s557 : state_type := "01100111"; + constant s579 : state_type := "01100101"; + constant s201 : state_type := "01100100"; + constant s202 : state_type := "01101100"; + constant s210 : state_type := "01101101"; + constant s211 : state_type := "01101111"; + constant s215 : state_type := "01101110"; + constant s217 : state_type := "01101010"; + constant s218 : state_type := "01101011"; + constant s222 : state_type := "01101001"; + constant s223 : state_type := "01101000"; + constant s224 : state_type := "01111000"; + constant s225 : state_type := "01111001"; + constant s226 : state_type := "01111011"; + constant s243 : state_type := "01111010"; + constant s244 : state_type := "01111110"; + constant s247 : state_type := "01111111"; + constant s344 : state_type := "01111101"; + constant s343 : state_type := "01111100"; + constant s250 : state_type := "01110100"; + constant s251 : state_type := "01110101"; + constant s351 : state_type := "01110111"; + constant s361 : state_type := "01110110"; + constant s360 : state_type := "01110010"; + constant s403 : state_type := "01110011"; + constant s406 : state_type := "01110001"; + constant s407 : state_type := "01110000"; + constant s409 : state_type := "01010000"; + constant s412 : state_type := "01010001"; + constant s413 : state_type := "01010011"; + constant s416 : state_type := "01010010"; + constant s418 : state_type := "01010110"; + constant s510 : state_type := "01010111"; + constant s553 : state_type := "01010101"; + constant s555 : state_type := "01010100"; + constant s558 : state_type := "01011100"; + constant s560 : state_type := "01011101"; + constant s561 : state_type := "01011111"; + constant s563 : state_type := "01011110"; + constant s564 : state_type := "01011010"; + constant s565 : state_type := "01011011"; + constant s566 : state_type := "01011001"; + constant s266 : state_type := "01011000"; + constant s301 : state_type := "01001000"; + constant s302 : state_type := "01001001"; + constant RES : state_type := "01001011"; + constant s511 : state_type := "01001010"; + constant s559 : state_type := "01001110"; + constant s562 : state_type := "01001111"; + constant s567 : state_type := "01001101"; + constant s568 : state_type := "01001100"; + constant s569 : state_type := "01000100"; + constant s570 : state_type := "01000101"; + constant s571 : state_type := "01000111"; + constant s572 : state_type := "01000110"; + constant s573 : state_type := "01000010"; + constant s574 : state_type := "01000011"; + constant s548 : state_type := "01000001"; + constant s551 : state_type := "01000000"; + constant s552 : state_type := "11000000"; + constant s575 : state_type := "11000001"; + constant s576 : state_type := "11000011"; + constant s577 : state_type := "11000010"; + constant s532 : state_type := "11000110"; + constant s533 : state_type := "11000111"; + constant s534 : state_type := "11000101"; + constant s535 : state_type := "11000100"; + constant s536 : state_type := "11001100"; + constant s537 : state_type := "11001101"; + + -- Declare current and next state signals + signal current_state : state_type; + signal next_state : state_type; + + -- Declare any pre-registered internal signals + signal d_o_cld : std_logic_vector ( 7 downto 0 ); + signal rd_o_cld : std_logic ; + signal sync_o_cld : std_logic ; + signal wr_n_o_cld : std_logic ; + signal wr_o_cld : std_logic ; + signal sel_alu_as_o_i_cld : std_logic ; + signal sel_alu_out_o_i_cld : std_logic_vector ( 2 downto 0 ); + signal sel_pc_as_o_i_cld : std_logic ; + signal sel_pc_in_o_i_cld : std_logic_vector ( 1 downto 0 ); + signal sel_pc_val_o_i_cld : std_logic_vector ( 1 downto 0 ); + signal sel_rb_in_o_i_cld : std_logic_vector ( 2 downto 0 ); + signal sel_rb_out_o_i_cld : std_logic_vector ( 2 downto 0 ); + signal sel_reg_o_i_cld : std_logic_vector ( 1 downto 0 ); + signal sel_sp_as_o_i_cld : std_logic ; + signal sel_sp_in_o_i_cld : std_logic_vector ( 1 downto 0 ); + signal sel_sp_val_o_i_cld : std_logic_vector ( 1 downto 0 ); + +begin + + ----------------------------------------------------------------- + clocked_proc : process ( + clk_clk_i, + rst_rst_n_i + ) + ----------------------------------------------------------------- + begin + if (rst_rst_n_i = '0') then + current_state <= RES; + -- Default Reset Values + d_o_cld <= X"00"; + rd_o_cld <= '0'; + sync_o_cld <= '0'; + wr_n_o_cld <= '1'; + wr_o_cld <= '0'; + sel_alu_as_o_i_cld <= '0'; + sel_alu_out_o_i_cld <= "000"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_val_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "000"; + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "00"; + sel_sp_val_o_i_cld <= "00"; + reg_F <= "00000100"; + reg_PC <= X"0000"; + reg_PC1 <= X"0000"; + sig_PC <= X"0000"; + zw_PC <= X"0000"; + zw_REG_ALU <= '0' & X"00"; + zw_REG_NMI <= '0'; + zw_REG_OP <= X"00"; + zw_REG_sig_PC <= X"0000"; + zw_b1 <= X"00"; + zw_b2 <= X"00"; + zw_b3 <= X"00"; + zw_b4 <= X"00"; + zw_w1 <= X"0000"; + zw_w2 <= X"0000"; + zw_w3 <= X"0000"; + elsif (clk_clk_i'event and clk_clk_i = '1') then + current_state <= next_state; + -- Default Assignment To Internals + reg_F <= reg_F or ('0' & (not so_n_i) & "000000"); + reg_PC <= reg_PC; + reg_PC1 <= reg_PC1; + sig_PC <= sig_PC; + zw_PC <= zw_PC; + zw_REG_ALU <= zw_REG_ALU; + zw_REG_NMI <= zw_REG_NMI or nmi_i; + zw_REG_OP <= zw_REG_OP; + zw_REG_sig_PC <= zw_REG_sig_PC; + zw_b1 <= zw_b1; + zw_b2 <= zw_b2; + zw_b3 <= zw_b3; + zw_b4 <= zw_b4; + zw_w1 <= zw_w1; + zw_w2 <= zw_w2; + zw_w3 <= zw_w3; + d_o_cld <= sig_D_OUT; + rd_o_cld <= sig_RD; + sync_o_cld <= sig_SYNC; + wr_n_o_cld <= sig_RWn; + wr_o_cld <= sig_WR; + sel_alu_as_o_i_cld <= sel_alu_as_o_i; + sel_alu_out_o_i_cld <= sel_alu_out_o_i; + sel_pc_as_o_i_cld <= sel_pc_as_o_i; + sel_pc_in_o_i_cld <= sel_pc_in_o_i; + sel_pc_val_o_i_cld <= sel_pc_val_o_i; + sel_rb_in_o_i_cld <= sel_rb_in_o_i; + sel_rb_out_o_i_cld <= sel_rb_out_o_i; + sel_reg_o_i_cld <= sel_reg_o_i; + sel_sp_as_o_i_cld <= sel_sp_as_o_i; + sel_sp_in_o_i_cld <= sel_sp_in_o_i; + sel_sp_val_o_i_cld <= sel_sp_val_o_i; + + -- Combined Actions + case current_state is + when FETCH => + zw_REG_OP <= d_i; + if ((zw_REG_NMI = '1') and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + zw_REG_NMI <= '0'; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + zw_b1(0) <= reg_F(7); + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + zw_b3 <= adr_nxt_pc_i (15 downto 8); + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"00") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"18") and (rdy_i = '1')) then + elsif ((d_i = X"D8") and (rdy_i = '1')) then + elsif ((d_i = X"58") and (rdy_i = '1')) then + elsif ((d_i = X"B8") and (rdy_i = '1')) then + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "010"; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + zw_b4 <= X"FF"; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_reg_o_i_cld <= "01"; + sel_rb_in_o_i_cld <= "011"; + zw_b4 <= X"FF"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"88") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "010"; + sel_reg_o_i_cld <= "10"; + sel_rb_in_o_i_cld <= "011"; + zw_b4 <= X"FF"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + zw_b4 <= X"01"; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_reg_o_i_cld <= "01"; + sel_rb_in_o_i_cld <= "011"; + zw_b4 <= X"01"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "010"; + sel_reg_o_i_cld <= "10"; + sel_rb_in_o_i_cld <= "011"; + zw_b4 <= X"01"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"20") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + sel_reg_o_i_cld <= "01"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + sel_reg_o_i_cld <= "10"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + elsif ((d_i = X"48") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"08") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"68") and (rdy_i = '1')) then + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + elsif ((d_i = X"28") and (rdy_i = '1')) then + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"40") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + elsif ((d_i = X"60") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + zw_b1(0) <= reg_F(7); + elsif ((d_i = X"38") and (rdy_i = '1')) then + elsif ((d_i = X"F8") and (rdy_i = '1')) then + elsif ((d_i = X"78") and (rdy_i = '1')) then + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"11") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "010"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "01"; + sel_rb_in_o_i_cld <= "000"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "000"; + sel_reg_o_i_cld <= "10"; + sel_rb_in_o_i_cld <= "000"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"98") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "010"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "001"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_reg_o_i_cld <= "01"; + sel_rb_in_o_i_cld <= "011"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_reg_o_i_cld <= "00"; + sel_rb_in_o_i_cld <= "010"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + sel_rb_out_o_i_cld <= "001"; + sel_reg_o_i_cld <= "11"; + sel_rb_in_o_i_cld <= "111"; + sel_alu_out_o_i_cld <= "110"; + sel_alu_as_o_i_cld <= '0'; + sel_sp_in_o_i_cld <= "01"; + sel_sp_as_o_i_cld <= '0'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s1 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s2 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '1'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s5 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '1'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s3 => + sig_PC <= adr_pc_i; + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '1'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s4 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s12 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= '0'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s16 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(3) <= '0'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s17 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(2) <= '0'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s24 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(6) <= '0'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s25 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s271 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "11"; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + zw_b1 <= d_i; + end if; + when s273 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + end if; + when s304 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "11"; + zw_b1 <= d_i; + end if; + when s307 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s177 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s180 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s181 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s182 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s183 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s184 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s185 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s186 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s187 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s188 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s189 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s190 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s191 => + sig_PC <= zw_b3 & zw_b1; + when s192 => + sig_PC <= d_i & zw_b1; + when s193 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s377 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s381 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s378 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s382 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s383 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s384 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s385 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s386 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F <= d_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s387 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s388 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s389 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + reg_F <= d_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "11"; + end if; + when s391 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end if; + when s392 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s390 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s393 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s394 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + end if; + when s395 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s396 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s397 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + zw_b1 <= d_i; + end if; + when s399 => + sig_PC <= adr_sp_i; + when s400 => + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "11"; + when s401 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1 (7 downto 0); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s526 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s527 => + sig_PC <= adr_sp_i; + when s528 => + sig_PC <= adr_sp_i; + when s529 => + sig_PC <= X"FFFE"; + when s530 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_F(4) <= '1'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s531 => + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + zw_b1 <= d_i; + end if; + when s544 => + sig_PC <= adr_sp_i; + when s545 => + sig_PC <= adr_sp_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + when s546 => + sig_PC <= adr_pc_i; + when s547 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + zw_w1 (7 downto 0) <= d_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "11"; + end if; + when s549 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_w1 (7 downto 0); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s550 => + sig_PC <= adr_sp_i; + sel_pc_in_o_i_cld <= "01"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + when s404 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s556 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s557 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(7); + reg_F(0) <= q_a_i(7); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s579 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(0) <= q_a_i(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s201 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + sig_PC <= X"00" & d_i; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + sig_PC <= adr_nxt_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + end if; + when s202 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s210 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s211 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s215 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s217 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s218 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s222 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s223 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s224 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s225 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + sig_PC <= adr_pc_i; + reg_F(7) <= zw_ALU(7); + reg_F(0) <= zw_ALU(8); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s226 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s243 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s244 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s247 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s344 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s343 => + if (rdy_i = '1') then + zw_b1 <= d_alu_i; + end if; + when s251 => + sig_PC <= adr_pc_i; + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s351 => + if (rdy_i = '1' and + zw_REG_OP = X"24") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end if; + when s361 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + reg_F(7) <= d_i(7); + reg_F(6) <= d_i(6); + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s360 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s403 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + end if; + when s406 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s407 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s409 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s412 => + if (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s416 => + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + zw_b1 <= d_i(6 downto 0) & '0'; + zw_b2(0) <= d_i(7); + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + zw_b1 <= '0' & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + zw_b1 <= d_i(6 downto 0) & reg_F(0); + zw_b2(0) <= d_i(7); + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + zw_b1 <= reg_F(0) & d_i(7 downto 1); + zw_b2(0) <= d_i(0); + end if; + when s418 => + sig_PC <= adr_pc_i; + reg_F(0) <= zw_b2(0); + reg_F(7) <= reg_7flag_i; + reg_F(1) <= reg_1flag_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s510 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s553 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s555 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s558 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s560 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s561 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s563 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s564 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s565 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU4(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s566 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s266 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "10"; + zw_b2 <= d_i; + end if; + when s301 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0); + end if; + when s302 => + if (rdy_i = '1') then + sig_PC <= adr_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when RES => + sel_pc_in_o_i_cld <= "00"; + sel_pc_val_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sig_PC <= adr_nxt_pc_i; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + when s511 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + sig_PC <= X"00" & d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + sig_PC <= adr_nxt_pc_i; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + sig_PC <= X"00" & d_i; + zw_b1 <= d_alu_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + sig_PC <= adr_nxt_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s559 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + end if; + when s562 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s567 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s568 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + zw_b1 <= d_alu_i; + zw_b2(0) <= reg_0flag_i; + end if; + when s569 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s570 => + if (rdy_i = '1') then + sig_PC <= X"00" & zw_b1; + end if; + when s571 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + zw_b3 <= d_alu_i; + end if; + when s572 => + if (rdy_i = '1') then + sig_PC <= X"00" & d_alu_i; + zw_b1 <= d_i; + end if; + when s573 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1') then + sig_PC <= zw_b3 & zw_b1; + end if; + when s574 => + if (rdy_i = '1' and + reg_F(3) = '0') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU(8); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + sig_PC <= adr_pc_i; + + reg_F(7) <= zw_ALU(7); + reg_F(6) <= zw_b1(0) XOR zw_ALU(7); + reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR + (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR + (zw_ALU(0))); + reg_F(0) <= zw_ALU2(4); + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s548 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s551 => + sig_PC <= adr_sp_i; + when s552 => + sig_PC <= adr_sp_i; + when s575 => + if (rdy_i = '1') then + sig_PC <= X"FFFF"; + zw_b1 <= d_i; + end if; + when s576 => + sig_PC <= X"FFFE"; + when s577 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + reg_F(2) <= '1'; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when s532 => + if (rdy_i = '1') then + sig_PC <= adr_sp_i; + end if; + when s533 => + sig_PC <= adr_sp_i; + when s534 => + sig_PC <= adr_sp_i; + when s535 => + if (rdy_i = '1') then + sig_PC <= X"FFFB"; + zw_b1 <= d_i; + end if; + when s536 => + sig_PC <= X"FFFA"; + when s537 => + if (rdy_i = '1') then + sig_PC <= d_i & zw_b1; + sel_pc_in_o_i_cld <= "00"; + sel_pc_as_o_i_cld <= '0'; + sel_pc_val_o_i_cld <= "00"; + sel_sp_in_o_i_cld <= "00"; + sel_sp_as_o_i_cld <= '1'; + sel_sp_val_o_i_cld <= "00"; + end if; + when others => + null; + end case; + end if; + end process clocked_proc; + + ----------------------------------------------------------------- + nextstate_proc : process ( + adr_nxt_pc_i, + current_state, + d_i, + irq_n_i, + rdy_i, + reg_F, + zw_REG_NMI, + zw_REG_OP, + zw_b2, + zw_b3 + ) + ----------------------------------------------------------------- + begin + case current_state is + when FETCH => + if ((zw_REG_NMI = '1') and (rdy_i = '1')) then + next_state <= s532; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + next_state <= s548; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + next_state <= s510; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + next_state <= s266; + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + next_state <= s351; + elsif ((d_i = X"00") and (rdy_i = '1')) then + next_state <= s526; + elsif ((d_i = X"18") and (rdy_i = '1')) then + next_state <= s12; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + next_state <= s16; + elsif ((d_i = X"58") and (rdy_i = '1')) then + next_state <= s17; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + next_state <= s24; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + next_state <= s226; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"88") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + next_state <= s226; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + next_state <= s25; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + next_state <= s271; + elsif ((d_i = X"20") and (rdy_i = '1')) then + next_state <= s397; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + next_state <= s201; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + next_state <= s1; + elsif ((d_i = X"48") and (rdy_i = '1')) then + next_state <= s377; + elsif ((d_i = X"08") and (rdy_i = '1')) then + next_state <= s378; + elsif ((d_i = X"68") and (rdy_i = '1')) then + next_state <= s379; + elsif ((d_i = X"28") and (rdy_i = '1')) then + next_state <= s380; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + next_state <= s403; + elsif ((d_i = X"40") and (rdy_i = '1')) then + next_state <= s387; + elsif ((d_i = X"60") and (rdy_i = '1')) then + next_state <= s390; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + next_state <= s511; + elsif ((d_i = X"38") and (rdy_i = '1')) then + next_state <= s2; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + next_state <= s5; + elsif ((d_i = X"78") and (rdy_i = '1')) then + next_state <= s3; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"11") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + next_state <= s177; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + next_state <= s404; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + next_state <= s556; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + next_state <= s557; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + next_state <= s579; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"98") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + next_state <= s4; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + next_state <= s4; + elsif (rdy_i = '1') then + next_state <= s1; + else + next_state <= FETCH; + end if; + when s1 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s1; + end if; + when s2 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s2; + end if; + when s5 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s5; + end if; + when s3 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s3; + end if; + when s4 => + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s4; + end if; + when s12 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s12; + end if; + when s16 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s16; + end if; + when s17 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s17; + end if; + when s24 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s24; + end if; + when s25 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s25; + end if; + when s271 => + if (rdy_i = '1' and + zw_REG_OP = X"4C") then + next_state <= s307; + elsif (rdy_i = '1' and + zw_REG_OP = X"6C") then + next_state <= s273; + else + next_state <= s271; + end if; + when s273 => + if (rdy_i = '1') then + next_state <= s304; + else + next_state <= s273; + end if; + when s304 => + if (rdy_i = '1') then + next_state <= s307; + else + next_state <= s304; + end if; + when s307 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s307; + end if; + when s177 => + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + next_state <= s184; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + next_state <= s185; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + next_state <= s183; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + next_state <= s182; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + next_state <= s180; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + next_state <= s181; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + next_state <= s186; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + next_state <= s185; + else + next_state <= s177; + end if; + when s180 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s180; + end if; + when s181 => + if (rdy_i = '1') then + next_state <= s189; + else + next_state <= s181; + end if; + when s182 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s182; + end if; + when s183 => + if (rdy_i = '1') then + next_state <= s187; + else + next_state <= s183; + end if; + when s184 => + next_state <= FETCH; + when s185 => + if (rdy_i = '1') then + next_state <= s190; + else + next_state <= s185; + end if; + when s186 => + if (rdy_i = '1') then + next_state <= s188; + else + next_state <= s186; + end if; + when s187 => + next_state <= FETCH; + when s188 => + if (rdy_i = '1') then + next_state <= s192; + else + next_state <= s188; + end if; + when s189 => + if (rdy_i = '1') then + next_state <= s191; + else + next_state <= s189; + end if; + when s190 => + next_state <= FETCH; + when s191 => + next_state <= s193; + when s192 => + next_state <= s193; + when s193 => + next_state <= FETCH; + when s377 => + if (rdy_i = '1') then + next_state <= s381; + else + next_state <= s377; + end if; + when s381 => + next_state <= FETCH; + when s378 => + if (rdy_i = '1') then + next_state <= s382; + else + next_state <= s378; + end if; + when s382 => + next_state <= FETCH; + when s379 => + if (rdy_i = '1') then + next_state <= s383; + else + next_state <= s379; + end if; + when s383 => + if (rdy_i = '1') then + next_state <= s384; + else + next_state <= s383; + end if; + when s384 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s384; + end if; + when s380 => + if (rdy_i = '1') then + next_state <= s385; + else + next_state <= s380; + end if; + when s385 => + if (rdy_i = '1') then + next_state <= s386; + else + next_state <= s385; + end if; + when s386 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s386; + end if; + when s387 => + if (rdy_i = '1') then + next_state <= s388; + else + next_state <= s387; + end if; + when s388 => + if (rdy_i = '1') then + next_state <= s389; + else + next_state <= s388; + end if; + when s389 => + if (rdy_i = '1') then + next_state <= s391; + else + next_state <= s389; + end if; + when s391 => + if (rdy_i = '1') then + next_state <= s392; + else + next_state <= s391; + end if; + when s392 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s392; + end if; + when s390 => + if (rdy_i = '1') then + next_state <= s393; + else + next_state <= s390; + end if; + when s393 => + if (rdy_i = '1') then + next_state <= s394; + else + next_state <= s393; + end if; + when s394 => + if (rdy_i = '1') then + next_state <= s395; + else + next_state <= s394; + end if; + when s395 => + if (rdy_i = '1') then + next_state <= s396; + else + next_state <= s395; + end if; + when s396 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s396; + end if; + when s397 => + if (rdy_i = '1') then + next_state <= s398; + else + next_state <= s397; + end if; + when s398 => + if (rdy_i = '1') then + next_state <= s399; + else + next_state <= s398; + end if; + when s399 => + next_state <= s400; + when s400 => + next_state <= s401; + when s401 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s401; + end if; + when s526 => + if (rdy_i = '1') then + next_state <= s527; + else + next_state <= s526; + end if; + when s527 => + next_state <= s528; + when s528 => + next_state <= s529; + when s529 => + next_state <= s531; + when s530 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s530; + end if; + when s531 => + if (rdy_i = '1') then + next_state <= s530; + else + next_state <= s531; + end if; + when s544 => + next_state <= s550; + when s545 => + next_state <= s546; + when s546 => + next_state <= s547; + when s547 => + if (rdy_i = '1') then + next_state <= s549; + else + next_state <= s547; + end if; + when s549 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s549; + end if; + when s550 => + next_state <= s545; + when s404 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s404; + end if; + when s556 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s556; + end if; + when s557 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s557; + end if; + when s579 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s579; + end if; + when s201 => + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + next_state <= s224; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + next_state <= FETCH; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + next_state <= s217; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + next_state <= s202; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + next_state <= s210; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + next_state <= s211; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + next_state <= s215; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + next_state <= s218; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + next_state <= s217; + else + next_state <= s201; + end if; + when s202 => + if (rdy_i = '1') then + next_state <= s224; + else + next_state <= s202; + end if; + when s210 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s210; + end if; + when s211 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s211; + end if; + when s215 => + if (rdy_i = '1') then + next_state <= s223; + else + next_state <= s215; + end if; + when s217 => + if (rdy_i = '1') then + next_state <= s224; + else + next_state <= s217; + end if; + when s218 => + if (rdy_i = '1') then + next_state <= s222; + else + next_state <= s218; + end if; + when s222 => + if (rdy_i = '1') then + next_state <= s202; + else + next_state <= s222; + end if; + when s223 => + if (rdy_i = '1') then + next_state <= s225; + else + next_state <= s223; + end if; + when s224 => + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s224; + end if; + when s225 => + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + next_state <= FETCH; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s224; + else + next_state <= s225; + end if; + when s226 => + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + next_state <= s343; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + next_state <= s247; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + next_state <= s243; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + next_state <= s244; + else + next_state <= s226; + end if; + when s243 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s243; + end if; + when s244 => + if (rdy_i = '1') then + next_state <= s344; + else + next_state <= s244; + end if; + when s247 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s247; + end if; + when s344 => + if (rdy_i = '1') then + next_state <= s343; + else + next_state <= s344; + end if; + when s343 => + if (rdy_i = '1') then + next_state <= s250; + else + next_state <= s343; + end if; + when s250 => + if (rdy_i = '1') then + next_state <= s251; + else + next_state <= s250; + end if; + when s251 => + next_state <= FETCH; + when s351 => + if (rdy_i = '1' and + zw_REG_OP = X"24") then + next_state <= s361; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + next_state <= s360; + else + next_state <= s351; + end if; + when s361 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s361; + end if; + when s360 => + if (rdy_i = '1') then + next_state <= s361; + else + next_state <= s360; + end if; + when s403 => + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + next_state <= s407; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + next_state <= s413; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + next_state <= s409; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + next_state <= s406; + else + next_state <= s403; + end if; + when s406 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s406; + end if; + when s407 => + if (rdy_i = '1') then + next_state <= s412; + else + next_state <= s407; + end if; + when s409 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s409; + end if; + when s412 => + if (rdy_i = '1') then + next_state <= s413; + else + next_state <= s412; + end if; + when s413 => + if (rdy_i = '1') then + next_state <= s416; + else + next_state <= s413; + end if; + when s416 => + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + next_state <= s418; + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + next_state <= s418; + else + next_state <= s416; + end if; + when s418 => + next_state <= FETCH; + when s510 => + if (rdy_i = '1' and + zw_REG_OP = X"65") then + next_state <= s565; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + next_state <= s560; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + next_state <= s553; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + next_state <= s555; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + next_state <= s555; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + next_state <= s558; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + next_state <= s561; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s510; + end if; + when s553 => + if (rdy_i = '1') then + next_state <= s565; + else + next_state <= s553; + end if; + when s555 => + if (rdy_i = '1') then + next_state <= s564; + else + next_state <= s555; + end if; + when s558 => + if (rdy_i = '1') then + next_state <= s566; + else + next_state <= s558; + end if; + when s560 => + if (rdy_i = '1') then + next_state <= s565; + else + next_state <= s560; + end if; + when s561 => + if (rdy_i = '1') then + next_state <= s563; + else + next_state <= s561; + end if; + when s563 => + if (rdy_i = '1') then + next_state <= s553; + else + next_state <= s563; + end if; + when s564 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s565; + else + next_state <= s564; + end if; + when s565 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s565; + end if; + when s566 => + if (rdy_i = '1') then + next_state <= s564; + else + next_state <= s566; + end if; + when s266 => + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s301; + else + next_state <= s266; + end if; + when s301 => + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s302; + else + next_state <= s301; + end if; + when s302 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s302; + end if; + when RES => + next_state <= s544; + when s511 => + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + next_state <= s574; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + next_state <= s569; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + next_state <= s559; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + next_state <= s562; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + next_state <= s567; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + next_state <= s568; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + next_state <= s570; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s511; + end if; + when s559 => + if (rdy_i = '1') then + next_state <= s574; + else + next_state <= s559; + end if; + when s562 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s562; + end if; + when s567 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s567; + end if; + when s568 => + if (rdy_i = '1') then + next_state <= s571; + else + next_state <= s568; + end if; + when s569 => + if (rdy_i = '1') then + next_state <= s574; + else + next_state <= s569; + end if; + when s570 => + if (rdy_i = '1') then + next_state <= s572; + else + next_state <= s570; + end if; + when s571 => + if (rdy_i = '1') then + next_state <= s573; + else + next_state <= s571; + end if; + when s572 => + if (rdy_i = '1') then + next_state <= s559; + else + next_state <= s572; + end if; + when s573 => + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + next_state <= FETCH; + elsif (rdy_i = '1') then + next_state <= s574; + else + next_state <= s573; + end if; + when s574 => + if (rdy_i = '1' and + reg_F(3) = '0') then + next_state <= FETCH; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + next_state <= FETCH; + else + next_state <= s574; + end if; + when s548 => + if (rdy_i = '1') then + next_state <= s551; + else + next_state <= s548; + end if; + when s551 => + next_state <= s552; + when s552 => + next_state <= s576; + when s575 => + if (rdy_i = '1') then + next_state <= s577; + else + next_state <= s575; + end if; + when s576 => + next_state <= s575; + when s577 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s577; + end if; + when s532 => + if (rdy_i = '1') then + next_state <= s533; + else + next_state <= s532; + end if; + when s533 => + next_state <= s534; + when s534 => + next_state <= s536; + when s535 => + if (rdy_i = '1') then + next_state <= s537; + else + next_state <= s535; + end if; + when s536 => + next_state <= s535; + when s537 => + if (rdy_i = '1') then + next_state <= FETCH; + else + next_state <= s537; + end if; + when others => + next_state <= RES; + end case; + end process nextstate_proc; + + ----------------------------------------------------------------- + output_proc : process ( + adr_nxt_pc_i, + adr_pc_i, + adr_sp_i, + current_state, + d_alu_i, + d_i, + d_regs_out_i, + irq_n_i, + q_a_i, + q_x_i, + q_y_i, + rdy_i, + reg_F, + sig_PC, + zw_ALU, + zw_ALU1, + zw_ALU2, + zw_ALU3, + zw_ALU4, + zw_ALU5, + zw_ALU6, + zw_REG_NMI, + zw_REG_OP, + zw_b1, + zw_b2, + zw_b3, + zw_b4, + zw_w1 + ) + ----------------------------------------------------------------- + begin + -- Default Assignment + a_o <= sig_PC; + adr_o <= X"0000"; + ch_a_o <= X"00"; + ch_b_o <= X"00"; + d_regs_in_o <= X"00"; + ld_o <= "00"; + ld_pc_o <= '0'; + ld_sp_o <= '0'; + load_regs_o <= '0'; + offset_o <= X"0000"; + reg_0flag_o <= reg_F(0); + reg_1flag_o <= reg_F(1); + reg_3flag_o <= reg_F(3); + reg_7flag_o <= reg_F(7); + -- Default Assignment To Internals + sig_D_OUT <= X"00"; + sig_RD <= '0'; + sig_RWn <= '1'; + sig_SYNC <= '0'; + sig_WR <= '0'; + zw_ALU <= '0' & X"00"; + zw_ALU1 <= '0' & X"00"; + zw_ALU2 <= '0' & X"00"; + zw_ALU3 <= '0' & X"00"; + zw_ALU4 <= '0' & X"00"; + zw_ALU5 <= '0' & X"00"; + zw_ALU6 <= '0' & X"00"; + + -- Combined Actions + case current_state is + when FETCH => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= NOT (rdy_i); + if ((zw_REG_NMI = '1') and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((irq_n_i = '0' and + reg_F(2) = '0') and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"69" or + d_i = X"65" or + d_i = X"75" or + d_i = X"6D" or + d_i = X"7D" or + d_i = X"79" or + d_i = X"61" or + d_i = X"71") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"06" or + d_i = X"16" or + d_i = X"0E" or + d_i = X"1E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"90" or + d_i = X"B0" or + d_i = X"F0" or + d_i = X"30" or + d_i = X"D0" or + d_i = X"10" or + d_i = X"50" or + d_i = X"70") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"24" or + d_i = X"2C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"00") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"18") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"D8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"58") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"B8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E0" or + d_i = X"E4" or + d_i = X"EC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C0" or + d_i = X"C4" or + d_i = X"CC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C6" or + d_i = X"D6" or + d_i = X"CE" or + d_i = X"DE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"CA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"88") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"49" or + d_i = X"45" or + d_i = X"55" or + d_i = X"4D" or + d_i = X"5D" or + d_i = X"59" or + d_i = X"41" or + d_i = X"51" or + d_i = X"09" or + d_i = X"05" or + d_i = X"15" or + d_i = X"0D" or + d_i = X"1D" or + d_i = X"19" or + d_i = X"01" or + d_i = X"11" or + d_i = X"29" or + d_i = X"25" or + d_i = X"35" or + d_i = X"2D" or + d_i = X"3D" or + d_i = X"39" or + d_i = X"21" or + d_i = X"31" or + d_i = X"C9" or + d_i = X"C5" or + d_i = X"D5" or + d_i = X"CD" or + d_i = X"DD" or + d_i = X"D9" or + d_i = X"C1" or + d_i = X"D1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E6" or + d_i = X"F6" or + d_i = X"EE" or + d_i = X"FE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"C8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4C" or + d_i = X"6C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"20") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A9" or + d_i = X"A5" or + d_i = X"B5" or + d_i = X"AD" or + d_i = X"BD" or + d_i = X"B9" or + d_i = X"A1" or + d_i = X"B1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A2" or + d_i = X"A6" or + d_i = X"B6" or + d_i = X"AE" or + d_i = X"BE") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A0" or + d_i = X"A4" or + d_i = X"B4" or + d_i = X"AC" or + d_i = X"BC") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"46" or + d_i = X"56" or + d_i = X"4E" or + d_i = X"5E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"EA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"48") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"08") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"68") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"28") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"26" or + d_i = X"36" or + d_i = X"2E" or + d_i = X"3E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"66" or + d_i = X"76" or + d_i = X"6E" or + d_i = X"7E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"40") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"60") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"E9" or + d_i = X"E5" or + d_i = X"F5" or + d_i = X"ED" or + d_i = X"FD" or + d_i = X"F9" or + d_i = X"E1" or + d_i = X"F1") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"38") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"F8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"78") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"85" or + d_i = X"95" or + d_i = X"8D" or + d_i = X"9D" or + d_i = X"99" or + d_i = X"81" or + d_i = X"91" or + d_i = X"11") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"86" or + d_i = X"96" or + d_i = X"8E") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"84" or + d_i = X"94" or + d_i = X"8C") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"AA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"0A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"4A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"2A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"6A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"A8") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"98") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"BA") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"8A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((d_i = X"9A") and (rdy_i = '1')) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s1 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s2 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s5 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s3 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s4 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"9A") then + adr_o <= X"01" & d_regs_out_i; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"BA") then + d_regs_in_o <= adr_sp_i (7 downto 0); + ch_a_o <= adr_sp_i (7 downto 0); + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ch_a_o <= d_regs_out_i; + ch_b_o <= X"00"; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s12 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s16 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s17 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s24 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s25 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + d_regs_in_o <= d_alu_i; + ch_a_o <= d_regs_out_i; + ch_b_o <= zw_b4; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s271 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s273 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s304 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s307 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s177 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"85" OR + zw_REG_OP = X"86" OR + zw_REG_OP = X"84")) then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"95" OR + zw_REG_OP = X"94")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"8D" OR + zw_REG_OP = X"8E" OR + zw_REG_OP = X"8C")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"9D") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"99") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"91") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"81") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"96") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s180 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s181 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s182 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s183 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s184 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s185 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s186 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s187 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s188 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s189 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s190 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s191 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + when s192 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= d_regs_out_i; + ld_o <= "11"; + ld_pc_o <= '1'; + when s193 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s377 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= q_a_i; + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s381 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s378 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s382 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_SYNC <= '1'; + when s379 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s383 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s384 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s380 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s385 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s386 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s387 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s388 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s389 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s391 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s392 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s390 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s393 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + end if; + when s394 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s395 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s396 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s397 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + end if; + when s398 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + end if; + when s399 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s400 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s401 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_b1; + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s526 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + end if; + when s527 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + when s528 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s529 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + when s530 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s531 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s544 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + when s545 => + sig_RWn <= '1'; + sig_RD <= '1'; + adr_o <= X"FFFB"; + ld_o <= "11"; + ld_pc_o <= '1'; + when s546 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_pc_o <= '1'; + when s547 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s549 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + adr_o <= d_i & zw_w1 (7 downto 0); + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + end if; + when s550 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + when s404 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & '0'; + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & '0'; + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s556 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= '0' & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= '0' & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s557 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= q_a_i (6 downto 0) & reg_F(0); + ch_b_o <= X"00"; + d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s579 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= reg_F(0) & q_a_i (7 downto 1); + ch_b_o <= X"00"; + d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1); + load_regs_o <= '1'; + sig_SYNC <= '1'; + end if; + when s201 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR + zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR + zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR + zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + ld_o <= "11"; + ld_pc_o <= '1'; + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR + zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B5" OR + zw_REG_OP = X"B4" OR + zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR + zw_REG_OP = X"35" OR + zw_REG_OP = X"D5")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"AD" OR + zw_REG_OP = X"AE" OR + zw_REG_OP = X"AC" OR + zw_REG_OP = X"4D" OR + zw_REG_OP = X"0D" OR + zw_REG_OP = X"2D" OR + zw_REG_OP = X"CD" OR + zw_REG_OP = X"EC" OR + zw_REG_OP = X"CC")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"BD" OR + zw_REG_OP = X"BC" OR + zw_REG_OP = X"5D" OR + zw_REG_OP = X"1D" OR + zw_REG_OP = X"3D" OR + zw_REG_OP = X"DD")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B9" OR + zw_REG_OP = X"BE" OR + zw_REG_OP = X"59" OR + zw_REG_OP = X"19" OR + zw_REG_OP = X"39" OR + zw_REG_OP = X"D9")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"B1" OR + zw_REG_OP = X"51" OR + zw_REG_OP = X"11" OR + zw_REG_OP = X"31" OR + zw_REG_OP = X"D1")) then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + (zw_REG_OP = X"A1" OR + zw_REG_OP = X"41" OR + zw_REG_OP = X"01" OR + zw_REG_OP = X"21" OR + zw_REG_OP = X"C1")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"B6") then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s202 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s210 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s211 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s215 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s217 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s218 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s222 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s223 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s224 => + sig_RWn <= '1'; + sig_RD <= '1'; + if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s225 => + sig_RWn <= '1'; + sig_RD <= '1'; + if ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or + zw_REG_OP = X"15" or zw_REG_OP = X"0D" or + zw_REG_OP = X"1D" or zw_REG_OP = X"19" or + zw_REG_OP = X"01" or zw_REG_OP = X"11")) then + d_regs_in_o <= d_i OR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i OR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or + zw_REG_OP = X"55" or zw_REG_OP = X"4D" or + zw_REG_OP = X"5D" or zw_REG_OP = X"59" or + zw_REG_OP = X"41" or zw_REG_OP = X"51")) then + d_regs_in_o <= d_i XOR q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i XOR q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or + zw_REG_OP = X"35" or zw_REG_OP = X"2D" or + zw_REG_OP = X"3D" or zw_REG_OP = X"39" or + zw_REG_OP = X"21" or zw_REG_OP = X"31")) then + d_regs_in_o <= d_i AND q_a_i; + load_regs_o <= '1'; + ch_a_o <= d_i AND q_a_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + elsif ((rdy_i = '1' AND + zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or + zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or + zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or + zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or + zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or + zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or + zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then + zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1; + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0') then + d_regs_in_o <= d_i; + load_regs_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s226 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"C6" OR + zw_REG_OP = X"E6")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"D6" OR + zw_REG_OP = X"F6")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"CE" OR + zw_REG_OP = X"EE")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"DE" OR + zw_REG_OP = X"FE")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + end if; + when s243 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s244 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s247 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s344 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s343 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= zw_b4; + end if; + when s250 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= zw_b1; + end if; + when s251 => + sig_RWn <= '1'; + sig_RD <= '1'; + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + when s351 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"24") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"2C") then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s361 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= q_a_i AND d_i; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + end if; + when s360 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s403 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"1E" or + zw_REG_OP = X"7E" or + zw_REG_OP = X"3E" or + zw_REG_OP = X"5E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"66" or + zw_REG_OP = X"26" or + zw_REG_OP = X"46")) then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"16" or + zw_REG_OP = X"76" or + zw_REG_OP = X"36" or + zw_REG_OP = X"56")) then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + (zw_REG_OP = X"0E" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"4E")) then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s406 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s407 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= "0000000" & zw_b2(0); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s409 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s412 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s413 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s416 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + (zw_REG_OP = X"06" or + zw_REG_OP = X"16" or + zw_REG_OP = X"0E" or + zw_REG_OP = X"1E")) then + sig_D_OUT <= d_i(6 downto 0) & '0'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"46" or + zw_REG_OP = X"56" or + zw_REG_OP = X"4E" or + zw_REG_OP = X"5E")) then + sig_D_OUT <= '0' & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"26" or + zw_REG_OP = X"36" or + zw_REG_OP = X"2E" or + zw_REG_OP = X"3E")) then + sig_D_OUT <= d_i(6 downto 0) & reg_F(0); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + elsif (rdy_i = '1' and + (zw_REG_OP = X"66" or + zw_REG_OP = X"76" or + zw_REG_OP = X"6E" or + zw_REG_OP = X"7E")) then + sig_D_OUT <= reg_F(0) & d_i(7 downto 1); + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + end if; + when s418 => + sig_RWn <= '1'; + sig_RD <= '1'; + ch_a_o <= zw_b1; + ch_b_o <= X"00"; + sig_SYNC <= '1'; + when s510 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"65") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '0') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"75") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"6D") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"7D") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"79") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"71") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"61") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"69" and + reg_F(3) = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s553 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s555 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s558 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s560 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s561 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s563 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s564 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s565 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5)); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5)); + + zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0'; + zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0'; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4)); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & d_i(3 downto 0)) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s566 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s266 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and ( + (reg_F(0) = '1' and zw_REG_OP = X"90") or + (reg_F(0) = '0' and zw_REG_OP = X"B0") or + (reg_F(1) = '0' and zw_REG_OP = X"F0") or + (reg_F(7) = '0' and zw_REG_OP = X"30") or + (reg_F(1) = '1' and zw_REG_OP = X"D0") or + (reg_F(7) = '1' and zw_REG_OP = X"10") or + (reg_F(6) = '1' and zw_REG_OP = X"50") or + (reg_F(6) = '0' and zw_REG_OP = X"70"))) then + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s301 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + zw_b3 = adr_nxt_pc_i (15 downto 8)) then + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + ld_o <= "11"; + ld_pc_o <= '1'; + sig_SYNC <= '1'; + elsif (rdy_i = '1') then + offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & + zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s302 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when RES => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_pc_o <= '1'; + ld_sp_o <= '1'; + sig_RWn <= '1'; + sig_RD <= '1'; + when s511 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + zw_REG_OP = X"E5") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '0') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"F5") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"ED") then + ld_o <= "11"; + ld_pc_o <= '1'; + elsif (rdy_i = '1' and + zw_REG_OP = X"FD") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F9") then + ld_o <= "11"; + ld_pc_o <= '1'; + ch_a_o <= d_i; + ch_b_o <= q_y_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"F1") then + ch_a_o <= d_i; + ch_b_o <= X"01"; + elsif (rdy_i = '1' and + zw_REG_OP = X"E1") then + ch_a_o <= d_i; + ch_b_o <= q_x_i; + elsif (rdy_i = '1' and + zw_REG_OP = X"E9" and + reg_F(3) = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s559 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s562 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s567 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s568 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= q_y_i; + end if; + when s569 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s570 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s571 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= d_i; + ch_b_o <= X"01"; + ld_o <= "11"; + ld_pc_o <= '1'; + end if; + when s572 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ch_a_o <= zw_b1; + ch_b_o <= X"01"; + end if; + when s573 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' AND + zw_b2(0) = '0' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s574 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1' and + reg_F(3) = '0') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0); + sig_SYNC <= '1'; + elsif (rdy_i = '1' and + reg_F(3) = '1') then + d_regs_in_o <= zw_ALU(7 downto 0); + load_regs_o <= '1'; + zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + + unsigned ((zw_ALU6(8 downto 5))); + zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + + unsigned ((zw_ALU5(8 downto 5))); + + zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & + (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0'; + zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & + (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ; + + zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6; + zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned + ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4); + + zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6; + zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned + ('0' & NOT (d_i(3 downto 0))) + reg_F(0); + sig_SYNC <= '1'; + end if; + when s548 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + end if; + when s551 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + when s552 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s575 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s576 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + when s577 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when s532 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + ld_o <= "11"; + ld_sp_o <= '1'; + ld_pc_o <= '1'; + end if; + when s533 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (15 downto 8); + when s534 => + sig_RWn <= '1'; + sig_RD <= '1'; + ld_o <= "11"; + ld_sp_o <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= adr_pc_i (7 downto 0); + when s535 => + sig_RWn <= '1'; + sig_RD <= '1'; + when s536 => + sig_RWn <= '1'; + sig_RD <= '1'; + sig_RWn <= '0'; + sig_RD <= '0'; + sig_WR <= '1'; + sig_D_OUT <= reg_F; + when s537 => + sig_RWn <= '1'; + sig_RD <= '1'; + if (rdy_i = '1') then + sig_SYNC <= '1'; + end if; + when others => + null; + end case; + end process output_proc; + + -- Concurrent Statements + -- Clocked output assignments + d_o <= d_o_cld; + rd_o <= rd_o_cld; + sync_o <= sync_o_cld; + wr_n_o <= wr_n_o_cld; + wr_o <= wr_o_cld; + sel_alu_as_o_i <= sel_alu_as_o_i_cld; + sel_alu_out_o_i <= sel_alu_out_o_i_cld; + sel_pc_as_o_i <= sel_pc_as_o_i_cld; + sel_pc_in_o_i <= sel_pc_in_o_i_cld; + sel_pc_val_o_i <= sel_pc_val_o_i_cld; + sel_rb_in_o_i <= sel_rb_in_o_i_cld; + sel_rb_out_o_i <= sel_rb_out_o_i_cld; + sel_reg_o_i <= sel_reg_o_i_cld; + sel_sp_as_o_i <= sel_sp_as_o_i_cld; + sel_sp_in_o_i <= sel_sp_in_o_i_cld; + sel_sp_val_o_i <= sel_sp_val_o_i_cld; +end fsm;
vhdl/fsm_core_v2_0.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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