Subversion Repositories cpu6502_true_cycle

Generation Settings

Declarations

Ports:

    -clk_clk_i   : std_logic








    -d_i         : std_logic_vector(7 DOWNTO 0)








    -so_n_i      : std_logic








    -rdy_i       : std_logic








    -irq_n_i     : std_logic








    -nmi_n_i     : std_logic








    -rst_rst_n_i : std_logic








    -a_o         : std_logic_vector(15 DOWNTO 0)








    -d_o         : std_logic_vector(7 DOWNTO 0)








    -rd_o        : std_logic








    -wr_o        : std_logic








    -wr_n_o      : std_logic








    -sync_o      : std_logic

Diagram Signals:

    -

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;

Bundles

Declarations

Ports:

    -clk_clk_i   : in     std_logic  ;








    -d_i         : in     std_logic_vector (7 DOWNTO 0) ;








    -irq_n_i     : in     std_logic  ;








    -nmi_n_i     : in     std_logic  ;








    -rdy_i       : in     std_logic  ;








    -rst_rst_n_i : in     std_logic  ;








    -so_n_i      : in     std_logic  ;








    -a_o         : out    std_logic_vector (15 DOWNTO 0) ;








    -d_o         : out    std_logic_vector (7 DOWNTO 0) ;








    -rd_o        : out    std_logic  ;








    -sync_o      : out    std_logic  ;








    -wr_n_o      : out    std_logic  ;








    -wr_o        : out    std_logic

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Generation Settings

Declarations

Ports:

    -clk_clk_i          : std_logic








    -d_i                : std_logic_vector(7 DOWNTO 0)








    -rdy_i              : std_logic








    -irq_n_i            : std_logic








    -so_n_i             : std_logic








    -a_o                : std_logic_vector(15 DOWNTO 0)








    -d_o                : std_logic_vector(7 DOWNTO 0)








    -rd_o               : std_logic








    -wr_o               : std_logic








    -wr_n_o             : std_logic








    -sync_o             : std_logic








    -rst_rst_n_i        : std_logic








    -nmi_n_i            : std_logic

Diagram Signals:

    -signal adr_o_i            : std_logic_vector(15 DOWNTO 0)








    -signal offset_o_i         : std_logic_vector(15 DOWNTO 0)








    -signal ch_a_o_i           : std_logic_vector(7 DOWNTO 0)








    -signal ch_b_o_i           : std_logic_vector(7 DOWNTO 0)








    -signal reg_0flag_core_o_i : std_logic








    -signal reg_3flag_core_o_i : std_logic








    -signal reg_7flag_core_o_i : std_logic








    -signal adr_sp_o_i         : std_logic_vector(15 DOWNTO 0)








    -signal adr_pc_o_i         : std_logic_vector(15 DOWNTO 0)








    -signal load_regs_o_i      : std_logic








    -signal ld_o_i             : std_logic_vector(1 DOWNTO 0)








    -signal reg_0flag_o_i      : std_logic








    -signal reg_1flag_o_i      : std_logic








    -signal reg_6flag_o_i      : std_logic








    -signal reg_7flag_o_i      : std_logic








    -signal d_regs_out_o_i     : std_logic_vector(7 DOWNTO 0)








    -signal d_alu_o_i          : std_logic_vector(7 DOWNTO 0)








    -signal cout_pc_o_i        : std_logic








    -signal sel_reg_o_i        : std_logic_vector(1 DOWNTO 0)








    -signal ld_pc_o_i          : std_logic








    -signal sel_alu_out_o_i    : std_logic_vector(2 DOWNTO 0)








    -signal sel_rb_out_o_i     : std_logic_vector(2 DOWNTO 0)








    -signal sel_rb_in_o_i      : std_logic_vector(2 DOWNTO 0)








    -signal sel_pc_in_o_i      : std_logic_vector(1 DOWNTO 0)








    -signal ld_sp_o_i          : std_logic








    -signal sel_sp_in_o_i      : std_logic_vector(1 DOWNTO 0)








    -signal sel_sp_val_o_i     : std_logic_vector(1 DOWNTO 0)








    -signal sel_pc_val_o_i     : std_logic_vector(1 DOWNTO 0)








    -signal sel_sp_as_o_i      : std_logic








    -signal sel_pc_as_o_i      : std_logic








    -signal sel_alu_as_o_i     : std_logic








    -signal adr_nxt_pc_o_i     : std_logic_vector(15 DOWNTO 0)








    -signal adr_nxt_sp_o_i     : std_logic_vector(15 DOWNTO 0)








    -signal q_a_o_i            : std_logic_vector(7 DOWNTO 0)








    -signal q_x_o_i            : std_logic_vector(7 DOWNTO 0)








    -signal q_y_o_i            : std_logic_vector(7 DOWNTO 0)








    -signal rst_rst_int_o_i    : std_logic








    -signal d_regs_in_o_i      : std_logic_vector(7 DOWNTO 0)








    -signal nmi_o_i            : std_logic








    -signal fetch_o_i          : std_logic

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

Declarations

Ports:

    -clk_clk_i   : in     std_logic  ;








    -d_i         : in     std_logic_vector (7 DOWNTO 0) ;








    -irq_n_i     : in     std_logic  ;








    -nmi_i       : in     std_logic  ;








    -rdy_i       : in     std_logic  ;








    -rst_rst_n_i : in     std_logic  ;








    -so_n_i      : in     std_logic  ;








    -a_o         : out    std_logic_vector (15 DOWNTO 0) ;








    -d_o         : out    std_logic_vector (7 DOWNTO 0) ;








    -rd_o        : out    std_logic  ;








    -sync_o      : out    std_logic  ;








    -wr_n_o      : out    std_logic  ;








    -wr_o        : out    std_logic

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Generation Settings

Declarations

Ports:

    -clk_clk_i    : std_logic








    -rst_rst_i    : std_logic








    -d_regs_in_i  : std_logic_vector(7 DOWNTO 0)








    -sel_rb_in_i  : std_logic_vector(2 DOWNTO 0)








    -sel_rb_out_i : std_logic_vector(1 DOWNTO 0)








    -load_regs_i  : std_logic








    -q_a_o        : std_logic_vector(7 DOWNTO 0)








    -q_x_o        : std_logic_vector(7 DOWNTO 0)








    -q_y_o        : std_logic_vector(7 DOWNTO 0)








    -d_regs_out_o : std_logic_vector(7 DOWNTO 0)








    -sel_reg_i    : std_logic_vector(1 DOWNTO 0)

Diagram Signals:

    -signal dout         : std_logic_vector(7 DOWNTO 0)








    -signal ld           : std_logic_vector(3 DOWNTO 0)








    -signal load         : std_logic








    -signal load1        : std_logic








    -signal load2        : std_logic








    -signal load3        : std_logic








    -signal q_zw         : std_logic_vector(7 DOWNTO 0)








    -signal val_zero     : std_logic_vector(7 DOWNTO 0)








    -signal dout1        : std_logic_vector(7 downto 0)

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

Declarations

Ports:

    -clk_clk_i    : in     std_logic  ;








    -d_regs_in_i  : in     std_logic_vector (7 DOWNTO 0) ;








    -load_regs_i  : in     std_logic  ;








    -rst_rst_i    : in     std_logic  ;








    -sel_rb_in_i  : in     std_logic_vector (2 DOWNTO 0) ;








    -sel_rb_out_i : in     std_logic_vector (1 DOWNTO 0) ;








    -sel_reg_i    : in     std_logic_vector (1 DOWNTO 0) ;








    -d_regs_out_o : out    std_logic_vector (7 DOWNTO 0) ;








    -q_a_o        : out    std_logic_vector (7 DOWNTO 0) ;








    -q_x_o        : out    std_logic_vector (7 DOWNTO 0) ;








    -q_y_o        : out    std_logic_vector (7 DOWNTO 0)

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

    --- eb1 1








    -val_zero (7 downto 0) <= X"00";

Generation Settings

Declarations

Ports:

    -A        : std_logic_vector(15 DOWNTO 0)








    -NMIn     : std_logic








    -clk      : std_logic








    -RSTn     : std_logic








    -RDY      : std_logic








    -IRQn     : std_logic








    -so_n_i   : std_logic








    -RAM_DOUT : std_logic_vector(7 DOWNTO 0)








    -CPU_DOUT : std_logic_vector( 7 DOWNTO 0 )








    -WR       : std_logic








    -RD       : std_logic








    -SYNC     : std_logic








    -clk1     : std_logic

Diagram Signals:

    -signal dout     : std_logic_vector(7 DOWNTO 0)








    -signal dout1    : std_logic_vector(7 DOWNTO 0)

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

Declarations

Ports:

    -IRQn     : in     std_logic  ;








    -NMIn     : in     std_logic  ;








    -RDY      : in     std_logic  ;








    -RSTn     : in     std_logic  ;








    -clk      : in     std_logic  ;








    -clk1     : in     std_logic  ;








    -so_n_i   : in     std_logic  ;








    -A        : out    std_logic_vector (15 DOWNTO 0) ;








    -CPU_DOUT : out    std_logic_vector ( 7 DOWNTO 0 ) ;








    -RAM_DOUT : out    std_logic_vector (7 DOWNTO 0) ;








    -RD       : out    std_logic  ;








    -SYNC     : out    std_logic  ;








    -WR       : out    std_logic

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Generation Settings

Declarations

Ports:

    -clk_clk_i    : std_logic








    -rst_rst_i    : std_logic








    -sel_sp_in_i  : std_logic








    -ld_i         : std_logic_vector(1 DOWNTO 0)








    -adr_i        : std_logic_vector(15 DOWNTO 0)








    -adr_sp_o     : std_logic_vector(15 DOWNTO 0)








    -sel_sp_val_i : std_logic








    -sel_sp_as_i  : std_logic








    -ld_sp_i      : std_logic








    -adr_nxt_sp_o : std_logic_vector(15 DOWNTO 0)

Diagram Signals:

    -signal load         : std_logic








    -signal val_zero     : std_logic_vector(7 DOWNTO 0)








    -signal val_one      : std_logic_vector(7 DOWNTO 0)








    -signal val_two      : std_logic_vector(7 DOWNTO 0)








    -signal dout1        : std_logic_vector(7 downto 0)








    -signal dout2        : std_logic_vector(7 DOWNTO 0)








    -signal dout3        : std_logic








    -signal load3        : std_logic








    -signal d            : std_logic_vector(7 downto 0)

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

Declarations

Ports:

    -adr_i        : in     std_logic_vector (15 DOWNTO 0) ;








    -clk_clk_i    : in     std_logic  ;








    -ld_i         : in     std_logic_vector (1 DOWNTO 0) ;








    -ld_sp_i      : in     std_logic  ;








    -rst_rst_i    : in     std_logic  ;








    -sel_sp_as_i  : in     std_logic  ;








    -sel_sp_in_i  : in     std_logic  ;








    -sel_sp_val_i : in     std_logic  ;








    -adr_nxt_sp_o : out    std_logic_vector (15 DOWNTO 0) ;








    -adr_sp_o     : out    std_logic_vector (15 DOWNTO 0)

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

    --- eb1 1








    -val_zero (7 downto 0) <= X"00";








    -val_one (7 downto 0) <= X"01";








    -val_two (7 downto 0) <= X"02";








    -adr_nxt_sp_o (15 downto 8) <= X"01";

    --- eb1 1








    -adr_nxt_sp_o (7 DOWNTO 0) <= d;

Declarations

Ports:

    -adr_i        : in     std_logic_vector (15 DOWNTO 0) ;








    -clk_clk_i    : in     std_logic  ;








    -ld_i         : in     std_logic_vector (1 DOWNTO 0) ;








    -ld_pc_i      : in     std_logic  ;








    -offset_i     : in     std_logic_vector (15 DOWNTO 0) ;








    -rst_rst_i    : in     std_logic  ;








    -sel_pc_as_i  : in     std_logic  ;








    -sel_pc_in_i  : in     std_logic  ;








    -sel_pc_val_i : in     std_logic_vector (1 DOWNTO 0) ;








    -adr_nxt_pc_o : out    std_logic_vector (15 DOWNTO 0) ;








    -adr_pc_o     : out    std_logic_vector (15 DOWNTO 0) ;








    -cout_pc_o    : out    std_logic

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

    --- eb1 1








    -val_zero (7 downto 0) <= X"00";








    -val_one (7 downto 0) <= X"01";








    -val_two (7 downto 0) <= X"02";

Generation Settings

Declarations

Ports:

    -clk_clk_i    : std_logic








    -rst_rst_i    : std_logic








    -sel_pc_in_i  : std_logic








    -ld_i         : std_logic_vector(1 DOWNTO 0)








    -adr_i        : std_logic_vector(15 DOWNTO 0)








    -adr_pc_o     : std_logic_vector(15 DOWNTO 0)








    -sel_pc_val_i : std_logic_vector(1 DOWNTO 0)








    -sel_pc_as_i  : std_logic








    -cout_pc_o    : std_logic








    -offset_i     : std_logic_vector(15 DOWNTO 0)








    -ld_pc_i      : std_logic








    -adr_nxt_pc_o : std_logic_vector(15 DOWNTO 0)

Diagram Signals:

    -signal load         : std_logic








    -signal val_zero     : std_logic_vector(7 DOWNTO 0)








    -signal val_one      : std_logic_vector(7 DOWNTO 0)








    -signal val_two      : std_logic_vector(7 DOWNTO 0)








    -signal dout1        : std_logic_vector(7 downto 0)








    -signal dout3        : std_logic








    -signal load3        : std_logic








    -signal d            : std_logic_vector(7 downto 0)








    -signal d1           : std_logic_vector(7 downto 0)








    -signal dout         : std_logic








    -signal dout5        : std_logic_vector(7 downto 0)








    -signal dout6        : std_logic_vector(7 downto 0)

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

    --- eb1 1








    -adr_nxt_pc_o(7 DOWNTO 0) <= d;

    --- eb1 1








    -adr_nxt_pc_o(15 DOWNTO 8) <= d1;

    --- eb1 1








    -val_zero (7 downto 0) <= X"00";








    -val_one (7 downto 0) <= X"01";








    -val_two (7 downto 0) <= X"02";








    -sel(0) <= reg_3flag_core_i AND sel_alu_out_i(0);








    -sel(1) <= sel_alu_as_i;

Generation Settings

Declarations

Ports:

    -ch_a_i           : std_logic_vector(7 DOWNTO 0)








    -ch_b_i           : std_logic_vector(7 DOWNTO 0)








    -d_alu_o          : std_logic_vector(7 DOWNTO 0)








    -reg_1flag_o      : std_logic








    -reg_0flag_o      : std_logic








    -reg_6flag_o      : std_logic








    -reg_7flag_o      : std_logic








    -reg_0flag_core_i : std_logic








    -reg_3flag_core_i : std_logic








    -sel_alu_as_i     : std_logic








    -reg_7flag_core_i : std_logic








    -sel_alu_out_i    : std_logic_vector(2 DOWNTO 0)

Diagram Signals:

    -signal q_and            : std_logic_vector(7 DOWNTO 0)








    -signal q_or             : std_logic_vector(7 DOWNTO 0)








    -signal q_xor            : std_logic_vector(7 DOWNTO 0)








    -signal q_aneg           : std_logic_vector(7 DOWNTO 0)








    -signal q_bneg           : std_logic_vector(7 DOWNTO 0)








    -signal val_zero         : std_logic_vector(7 DOWNTO 0)








    -signal val_one          : std_logic_vector(7 DOWNTO 0)








    -signal val_two          : std_logic_vector(7 DOWNTO 0)








    -signal q_a              : std_logic_vector(7 DOWNTO 0)








    -signal din              : std_logic








    -signal din1             : std_logic








    -signal sel              : std_logic_vector(1 DOWNTO 0)








    -signal din0             : std_logic








    -signal din2             : std_logic








    -signal din3             : std_logic








    -signal dout             : std_logic

Pre User:

    -

Post User:

    -

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;

Bundles

Declarations

Ports:

    -ch_a_i           : in     std_logic_vector (7 DOWNTO 0) ;








    -ch_b_i           : in     std_logic_vector (7 DOWNTO 0) ;








    -reg_0flag_core_i : in     std_logic  ;








    -reg_3flag_core_i : in     std_logic  ;








    -reg_7flag_core_i : in     std_logic  ;








    -sel_alu_as_i     : in     std_logic  ;








    -sel_alu_out_i    : in     std_logic_vector (2 DOWNTO 0) ;








    -d_alu_o          : out    std_logic_vector (7 DOWNTO 0) ;








    -reg_0flag_o      : out    std_logic  ;








    -reg_1flag_o      : out    std_logic  ;








    -reg_6flag_o      : out    std_logic  ;








    -reg_7flag_o      : out    std_logic

User:

    -

Generic Declarations

Package List

    -LIBRARY ieee;








    -USE ieee.std_logic_1164.all;








    -USE ieee.std_logic_arith.all;