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/errata.txt
0,0 → 1,15
v1.11 BETA 2013/07/24
FUNCTIONALITY:
- ADC and SBC in decimal mode (all op codes -
seems to use a formula different from a real R6502.
 
TIMING:
- All Branch Instructions
(BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
4 cycles if branch forward occur and the branch
instruction lies on a xxFEh location.
Must be 3 cycles.
 
SIGNALING:
- Hardware Interrupts NMI & IRQ - NO "SYNC"
- RESET generates NO SYNC

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