OpenCores

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/doc/R65C02 IP Core Specification.pdf

doc/R65C02 IP Core Specification.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/errata.txt =================================================================== --- doc/errata.txt (revision 23) +++ doc/errata.txt (nonexistent) @@ -1,21 +0,0 @@ -v2.00RC 2018/10/14 -FUNCTIONALITY: - no errata reported/opened - -TIMING: - no errata reported/opened - -SIGNALING: - no errata reported/opened - - -v1.52 2018/09/10 -FUNCTIONALITY: - no errata reported/opened - -TIMING: - no errata reported/opened - -SIGNALING: - no errata reported/opened - Index: doc/HTML_r65c02_tc.7z =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/HTML_r65c02_tc.7z =================================================================== --- doc/HTML_r65c02_tc.7z (revision 23) +++ doc/HTML_r65c02_tc.7z (nonexistent)

doc/HTML_r65c02_tc.7z Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/65C02_OP code_table_A02.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/65C02_OP code_table_A02.pdf =================================================================== --- doc/65C02_OP code_table_A02.pdf (revision 23) +++ doc/65C02_OP code_table_A02.pdf (nonexistent)

doc/65C02_OP code_table_A02.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: rtl/vhdl/fsm_execution_unit.vhd =================================================================== --- rtl/vhdl/fsm_execution_unit.vhd (revision 23) +++ rtl/vhdl/fsm_execution_unit.vhd (nonexistent) @@ -1,4974 +0,0 @@ --- VHDL Entity r65c02_tc.fsm_execution_unit.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 15:56:20 27.08.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity fsm_execution_unit is - port( - adr_nxt_pc_i : in std_logic_vector (15 downto 0); - adr_pc_i : in std_logic_vector (15 downto 0); - adr_sp_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic; - d_alu_i : in std_logic_vector ( 7 downto 0 ); - d_alu_prio_i : in std_logic_vector (7 downto 0); - d_i : in std_logic_vector ( 7 downto 0 ); - d_regs_out_i : in std_logic_vector ( 7 downto 0 ); - irq_n_i : in std_logic; - nmi_i : in std_logic; - q_a_i : in std_logic_vector ( 7 downto 0 ); - q_x_i : in std_logic_vector ( 7 downto 0 ); - q_y_i : in std_logic_vector ( 7 downto 0 ); - rdy_i : in std_logic; - reg_0flag_i : in std_logic; - reg_1flag_i : in std_logic; - reg_7flag_i : in std_logic; - rst_rst_n_i : in std_logic; - so_n_i : in std_logic; - a_o : out std_logic_vector (15 downto 0); - adr_o : out std_logic_vector (15 downto 0); - ch_a_o : out std_logic_vector ( 7 downto 0 ); - ch_b_o : out std_logic_vector ( 7 downto 0 ); - d_o : out std_logic_vector ( 7 downto 0 ); - d_regs_in_o : out std_logic_vector ( 7 downto 0 ); - ld_o : out std_logic_vector ( 1 downto 0 ); - ld_pc_o : out std_logic; - ld_sp_o : out std_logic; - load_regs_o : out std_logic; - offset_o : out std_logic_vector ( 15 downto 0 ); - rd_o : out std_logic; - rst_nmi_o : out std_logic; - sel_pc_in_o : out std_logic; - sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); - sel_reg_o : out std_logic_vector ( 1 downto 0 ); - sel_sp_as_o : out std_logic; - sel_sp_in_o : out std_logic; - sync_o : out std_logic; - wr_n_o : out std_logic; - wr_o : out std_logic - ); - --- Declarations - -end fsm_execution_unit ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.13 2018/10/14 11:50:00 jens --- - Performance improvements --- Revision 1.1202 2018/09/10 12:14:00 jens --- - RESET generates SYNC now, 1 dead cycle delayed --- Revision 1.1202 RC 2018/09/09 03:00:00 jens --- - ADC / SBC flags and A like R65C02 now --- Revision 1.1202 BETA 2018/09/05 19:35:00 jens --- - BBRx/BBSx internal cycles like real 65C02 now --- - Bug Fix ADC and SBC in decimal mode (all op codes - --- 1 cycle is missing --- - Bug Fix ADC and SBC in decimal mode (all op codes - --- "Overflow" flag was computed wrong) --- Revision 1.1202 BETA 2018/09/02 18:49:00 jens --- - Interrupt NMI and IRQ processing via FETCH stage now --- Revision 1.1202 BETA 2018/08/30 15:39:00 jens --- - Interrupt priority order is now: BRQ - NMI - IRQ --- - Performance improvements on-going (Mealy -> Moore) --- Revision 1.1202 BETA 2018/08/23 20:27:00 jens --- - Bug Fixes All Branch Instructions --- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) --- 3 cycles now if branch forward occur and the branch --- instruction lies on a xxFEh location. --- (BBR, BBS) 6 cycles now if branch forward occur and the --- branch instruction lies on a xxFDh location. --- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now --- - Bug Fix Now all cycles are delayable (WR and internal) --- --- Revision 1.1201 BETA 2014/04/19 14:44:00 jens --- (never submitted to opencores) --- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. --- When the ABS address data bytes cross the page --- boundary (e.g. $02FE JMP hhll reads hh from --- $02FF and ll from $0200, instead $02FF and $0300) --- --- Revision 1.12 RC 2013/07/31 11:53:00 jens --- - Bug Fix CMP (IND) - wrongly decoded as function AND --- - Bug Fix BRK should clear decimal flag P Reg --- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address --- - Bug Fix Unknown Ops - Used allways 1b2c NOP ($EA) - new NOPs created --- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) --- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed --- - Bug Fix RTI - should increment stack pointer (decremented) --- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. --- - Bug Fix ADC and SBC (all op codes - "Overflow" flag was computed wrong) --- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. --- --- Revision 1.11 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) --- --- Revision 1.10 2010/02/08 17:34:20 eda --- BUGFIX for IRQn, NMIn and RTI --- After detection of NMI or IRQ the address of the next instruction stacked wrong. --- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the --- vector address is not loaded yet. --- --- --- Revision 1.9 2010/02/08 17:32:19 eda --- BUGFIX for IRQn, NMIn and RTI --- After detection of NMI or IRQ the address of the next instruction stacked wrong. --- NMI now overwrites the vector address of IRQ if NMI asserted after IRQ and the --- vector address is not loaded yet. --- --- --- Revision 1.8 2009/01/04 20:23:42 eda --- *** EMERGENCY BUGFIX *** --- - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. --- - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist --- when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from --- $02FF and $0200, instead of $02FF and $0300) --- --- Revision 1.7 2009/01/04 16:54:59 eda --- - Removed unused bits in ALU (zw_ALUx) --- --- Revision 1.6 2009/01/04 10:27:49 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 10:25:04 eda --- Changes for cosmetic issues only --- --- Revision 1.4 2009/01/03 16:53:01 eda --- - Unused nets and blocks deleted --- - Re-arragend symbols in block FSM_Execution_Unit --- - Renamed blocks --- - Input SO implemented --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Re-arragend symbols in block FSM_Execution_Unit --- - Renamed blocks --- - Input SO implemented --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.01 2018/10/14 11:57:00 jens --- Production Release --- --- --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.01 2018/09/26 11:11:00 jens --- Production Release --- --- --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.01 2018/09/26 11:11:00 jens --- Production Release --- --- --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.01 2018/09/26 11:11:00 jens --- Production Release --- --- --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.01 2018/10/02 10:36:00 jens --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.fsm_execution_unit.fsm --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:03:14 14.10.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -architecture fsm of fsm_execution_unit is - - -- Architecture Declarations - signal adc_sbc_finished : std_logic; - signal addr_correction : std_logic_vector(7 DOWNTO 0); - signal c_detect_out : std_logic; - signal cnz_detect_in : std_logic_vector(8 DOWNTO 0); - signal irq_finished : std_logic; - signal n_detect_out : std_logic; - signal op_fetch : std_logic; - signal op_finished : std_logic; - signal reg_F : std_logic_vector( 7 DOWNTO 0 ); - signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 ); - signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 ); - signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 ); - signal rmb_started : std_logic; - signal rst_finished : std_logic; - signal sel_pc_in : std_logic; - signal sel_pc_val : std_logic_vector( 1 DOWNTO 0 ); - signal sel_sp_as : std_logic; - signal sel_sp_in : std_logic; - signal shift_rot_asl_out : std_logic_vector( 7 DOWNTO 0 ); - signal shift_rot_in : std_logic_vector( 7 DOWNTO 0 ); - signal shift_rot_l_c_out : std_logic; - signal shift_rot_lsr_out : std_logic_vector( 7 DOWNTO 0 ); - signal shift_rot_r_c_out : std_logic; - signal shift_rot_rol_out : std_logic_vector( 7 DOWNTO 0 ); - signal shift_rot_ror_out : std_logic_vector( 7 DOWNTO 0 ); - signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 ); - signal sig_PC : std_logic_vector(15 DOWNTO 0); - signal sig_RD : std_logic; - signal sig_RWn : std_logic; - signal sig_SYNC : std_logic; - signal sig_WR : std_logic; - signal z_detect_out : std_logic; - signal zw_ALU : std_logic_vector(9 DOWNTO 0); - signal zw_ALU1 : std_logic_vector(9 DOWNTO 0); - signal zw_ALU2 : std_logic_vector(9 DOWNTO 0); - signal zw_ALU3 : std_logic_vector(9 DOWNTO 0); - signal zw_ALU4 : std_logic_vector(9 DOWNTO 0); - signal zw_ALU5 : std_logic_vector(9 DOWNTO 0); - signal zw_ALU6 : std_logic_vector(9 DOWNTO 0); - signal zw_PC : std_logic_vector( 15 DOWNTO 0 ); - signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 ); - signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 ); - signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0); - signal zw_b1 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b10 : std_logic_vector(9 DOWNTO 0); - signal zw_b11 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b12 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b13 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b14 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b2 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b3 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b4 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b5 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b6 : std_logic_vector( 7 DOWNTO 0 ); - signal zw_b7 : std_logic_vector(9 DOWNTO 0); - signal zw_b8 : std_logic_vector(9 DOWNTO 0); - signal zw_b9 : std_logic_vector(9 DOWNTO 0); - signal zw_din : std_logic_vector(7 DOWNTO 0); - signal zw_reg_0flag : std_logic; - signal zw_so : std_logic; - signal zw_w1 : std_logic_vector( 15 DOWNTO 0 ); - signal zw_w2 : std_logic_vector( 15 DOWNTO 0 ); - signal zw_w3 : std_logic_vector( 15 DOWNTO 0 ); - - type csm_state_type is ( - res2, - res4, - res5, - res6, - res7, - res3, - RES, - FETCH, - s6, - s10, - s268, - s305, - s306, - jmp1, - jmp2_1, - jmp4_12, - jmp_ex, - jmp2_2, - jmp3_1, - jsr1, - jsr2, - jsr3, - jsr4, - jsr5, - brk1, - brk2, - brk3, - brk4, - brk6, - brk5, - rti1, - rti2, - rti3, - rti4, - rti5, - rts1, - rts2, - rts3, - rts4, - rts5, - pha1, - pha2, - php1, - php2, - pla1, - pla2, - pla3, - plp1, - plp2, - plp3, - irq1, - irq2, - irq3, - irq5b, - irq5a, - irq4, - irq6a, - s11, - s12, - s20, - s14, - s21, - s23, - s15, - s25, - s28, - s16, - s30, - s31, - s32, - s33, - s34, - s36, - jmp3_2, - s270, - s307, - s308, - s271, - s272, - s309, - RES0, - zp1, - zp2, - zpx1, - zpx2, - zpx3, - ab1, - ab2, - ab3, - absx1, - absx2, - absx4, - absx3, - ind1, - ind3, - ind4, - ind2, - indy1, - indy2, - indy3, - indy5, - indy4, - indx1, - indx4, - indx2, - indx3, - indx5, - zpy1, - zpy2, - zpy3, - absy2, - absy1, - absy4, - absy3, - imm1, - imp1, - irq6b, - absx5, - absy5, - indy6, - s237, - s348, - s254, - s255, - s238, - s257, - s350, - s258, - s259, - s239, - s260, - s352, - s263, - s264, - s240, - s266, - s353, - s354, - s269, - s273, - zp2w, - zpx3w, - zpy3w, - ab3w, - absx4w, - absx3w, - absy4w, - absy3w, - ind4w, - indx5w, - indy5w, - indy4w, - s256, - s261, - s265, - s274, - s355, - zp3, - zpx4, - ab4, - ind5, - indx6, - imm2 - ); - type csm_functions_state_type is ( - f_idle, - f_and, - f_lda, - f_rst, - f_eor, - f_cmp, - f_ora, - f_clc, - f_sec, - f_cld, - f_sed, - f_clv, - f_cli, - f_sei, - f_rti, - f_irq, - f_res, - f_bit1, - f_bit2, - f_de_in_a, - f_adc_bin, - f_sbc_bin, - f_adc_dec, - f_adc_dec1, - f_sbc_dec, - f_sbc_dec1, - f_asla, - f_lsra, - f_rola, - f_rora, - f_tax, - f_tsx, - f_decr, - f_asl, - f_lsr, - f_rol, - f_ror, - f_rmb, - f_smb, - f_trb, - f_tsb - ); - type csm_rb_out_state_type is ( - rb_out_idle, - rb_out_01, - rb_out_10, - rb_out_11 - ); - type csm_reg_state_type is ( - reg_idle, - reg_10, - reg_11, - reg_01 - ); - type csm_rb_in_state_type is ( - rb_in_idle, - rb_in_01, - rb_in_10, - rb_in_00 - ); - type csm_add_value_state_type is ( - add_val_idle, - add_val - ); - - -- Declare current and next state signals - signal csm_current_state : csm_state_type; - signal csm_next_state : csm_state_type; - signal csm_functions_current_state : csm_functions_state_type; - signal csm_functions_next_state : csm_functions_state_type; - signal csm_rb_out_current_state : csm_rb_out_state_type; - signal csm_rb_out_next_state : csm_rb_out_state_type; - signal csm_reg_current_state : csm_reg_state_type; - signal csm_reg_next_state : csm_reg_state_type; - signal csm_rb_in_current_state : csm_rb_in_state_type; - signal csm_rb_in_next_state : csm_rb_in_state_type; - signal csm_add_value_current_state : csm_add_value_state_type; - signal csm_add_value_next_state : csm_add_value_state_type; - - -- Declare any pre-registered internal signals - signal sync_o_cld : std_logic ; - -begin - - ----------------------------------------------------------------- - csm_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_current_state <= RES; - -- Default Reset Values - sync_o_cld <= '0'; - reg_sel_rb_in <= "00"; - reg_sel_rb_out <= "00"; - reg_sel_reg <= "00"; - zw_PC <= X"0000"; - zw_REG_ALU <= '0' & X"00"; - zw_REG_OP <= X"00"; - zw_REG_sig_PC <= X"0000"; - zw_b1 <= X"00"; - zw_b11 <= X"00"; - zw_b12 <= X"00"; - zw_b2 <= X"00"; - zw_b3 <= X"00"; - zw_b5 <= X"00"; - zw_b6 <= X"00"; - zw_reg_0flag <= '0'; - zw_so <= '0'; - zw_w1 <= X"0000"; - zw_w2 <= X"0000"; - zw_w3 <= X"0000"; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_current_state <= csm_next_state; - -- Default Assignment To Internals - reg_sel_rb_in <= reg_sel_rb_in; - reg_sel_rb_out <= reg_sel_rb_out; - reg_sel_reg <= reg_sel_reg; - zw_PC <= zw_PC; - zw_REG_ALU <= zw_REG_ALU; - zw_REG_OP <= zw_REG_OP; - zw_REG_sig_PC <= zw_REG_sig_PC; - zw_b1 <= zw_b1; - zw_b11 <= zw_b11; - zw_b12 <= zw_b12; - zw_b2 <= zw_b2; - zw_b3 <= zw_b3; - zw_b5 <= zw_b5; - zw_b6 <= zw_b6; - zw_reg_0flag <= zw_reg_0flag; - zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6))); - zw_w1 <= zw_w1; - zw_w2 <= zw_w2; - zw_w3 <= zw_w3; - sync_o_cld <= sig_SYNC; - - -- Combined Actions - case csm_current_state is - when res6 => - zw_b5 <= d_i; - when FETCH => - zw_REG_OP <= d_i; - if ((d_i = X"00") and (rdy_i = '1')) then - elsif ((nmi_i = '1') and (rdy_i = '1')) then - zw_w3 <= adr_pc_i; - elsif ((irq_n_i = '0' and - reg_F(2) = '0') and (rdy_i = '1')) then - zw_w3 <= adr_pc_i; - end if; - when s268 => - zw_b3 <= adr_nxt_pc_i (15 downto 8); - zw_b2 <= d_i; - when jmp1 => - zw_b5 <= d_i; - when jmp2_1 => - zw_b6 <= d_i; - when jmp4_12 => - zw_b5 <= d_i; - when jmp2_2 => - zw_b6 <= d_i; - when jsr1 => - zw_b1 <= d_i; - when jsr2 => - zw_b11 <= adr_pc_i (15 downto 8); - zw_b12 <= adr_pc_i (7 downto 0); - when brk1 => - zw_b11 <= adr_nxt_pc_i (15 downto 8); - zw_b12 <= adr_nxt_pc_i (7 downto 0); - when brk3 => - zw_b11 <= reg_F OR X"30"; - when brk5 => - zw_b5 <= d_i; - when rti4 => - zw_b5 <= d_i; - when rts3 => - zw_b5 <= d_i; - when rts4 => - zw_b6 <= d_i; - when irq1 => - zw_b11 <= zw_w3 (15 downto 8); - zw_b12 <= zw_w3 (7 downto 0); - when irq3 => - zw_b11 <= reg_F AND X"EF"; - when irq5b => - zw_b5 <= d_i; - when irq5a => - zw_b5 <= d_i; - when s270 => - zw_b2 <= d_i; - when s308 => - zw_w3 <= adr_pc_i; - zw_b2 <= d_i; - zw_b3 <= adr_nxt_pc_i (15 downto 8); - when s272 => - zw_b1 <= d_i; - when zp1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when zpx1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when zpx2 => - zw_b1 <= d_alu_i; - when ab1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when ab2 => - zw_b6 <= d_i; - when absx1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when absx2 => - zw_b6 <= d_i; - zw_b1 <= d_alu_i; - zw_reg_0flag <= reg_0flag_i; - when absx3 => - zw_b3 <= d_alu_i; - when ind1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when ind3 => - zw_b5 <= d_i; - when ind2 => - zw_b1 <= d_alu_i; - zw_b6 <= d_i; - when indy1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when indy2 => - zw_b2 <= d_i; - zw_b1 <= d_alu_i; - when indy3 => - zw_b5 <= d_i; - zw_b6 <= d_alu_i; - zw_reg_0flag <= reg_0flag_i; - when indy4 => - zw_b3 <= d_alu_i; - when indx1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when indx4 => - zw_b2 <= d_i; - when indx2 => - zw_b1 <= d_alu_i; - when indx3 => - zw_b5 <= d_i; - zw_b6 <= d_alu_i; - when zpy1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when zpy2 => - zw_b1 <= d_alu_i; - when absy2 => - zw_b6 <= d_i; - zw_b1 <= d_alu_i; - zw_reg_0flag <= reg_0flag_i; - when absy1 => - zw_b5 <= d_i; - zw_b11 <= d_regs_out_i; - when absy3 => - zw_b3 <= d_alu_i; - when s237 => - zw_b5 <= d_i; - when s348 => - zw_b2 <= d_i; - when s254 => - zw_b11 <= d_alu_i; - when s238 => - zw_b5 <= d_i; - when s257 => - zw_b1 <= d_alu_i; - when s350 => - zw_b2 <= d_i; - when s258 => - zw_b11 <= d_alu_i; - when s239 => - zw_b5 <= d_i; - when s260 => - zw_b6 <= d_i; - when s352 => - zw_b2 <= d_i; - when s263 => - zw_b11 <= d_alu_i; - when s240 => - zw_b5 <= d_i; - when s266 => - zw_b6 <= d_i; - zw_b1 <= d_alu_i; - zw_reg_0flag <= reg_0flag_i; - when s353 => - zw_b2 <= d_i; - zw_b3 <= d_alu_i; - when s354 => - zw_b2 <= d_i; - when s269 => - zw_b11 <= d_alu_i; - when absx3w => - zw_b3 <= d_alu_i; - when absy3w => - zw_b3 <= d_alu_i; - when indy4w => - zw_b3 <= d_alu_i; - when s256 => - zw_b11 <= zw_b13; - when s261 => - zw_b11 <= zw_b13; - when s265 => - zw_b11 <= zw_b13; - when s274 => - zw_b11 <= zw_b13; - when others => - null; - end case; - end if; - end process csm_clocked_proc; - - ----------------------------------------------------------------- - csm_nextstate_proc : process ( - addr_correction, - csm_current_state, - d_i, - irq_n_i, - nmi_i, - rdy_i, - reg_F, - zw_REG_OP, - zw_b1, - zw_reg_0flag - ) - ----------------------------------------------------------------- - begin - case csm_current_state is - when res2 => - if (rdy_i = '1') then - csm_next_state <= res3; - else - csm_next_state <= res2; - end if; - when res4 => - if (rdy_i = '1') then - csm_next_state <= res5; - else - csm_next_state <= res4; - end if; - when res5 => - if (rdy_i = '1') then - csm_next_state <= res6; - else - csm_next_state <= res5; - end if; - when res6 => - if (rdy_i = '1') then - csm_next_state <= res7; - else - csm_next_state <= res6; - end if; - when res7 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= res7; - end if; - when res3 => - if (rdy_i = '1') then - csm_next_state <= res4; - else - csm_next_state <= res3; - end if; - when RES => - csm_next_state <= RES0; - when FETCH => - if ((d_i = X"00") and (rdy_i = '1')) then - csm_next_state <= brk1; - elsif ((nmi_i = '1') and (rdy_i = '1')) then - csm_next_state <= irq1; - elsif ((irq_n_i = '0' and - reg_F(2) = '0') and (rdy_i = '1')) then - csm_next_state <= irq1; - elsif ((d_i = X"8F" or - d_i = X"9F" or - d_i = X"AF" or - d_i = X"BF" or - d_i = X"CF" or - d_i = X"DF" or - d_i = X"EF" or - d_i = X"FF" or - d_i = X"0F" or - d_i = X"1F" or - d_i = X"2F" or - d_i = X"3F" or - d_i = X"4F" or - d_i = X"5F" or - d_i = X"6F" or - d_i = X"7F") and (rdy_i = '1')) then - csm_next_state <= s270; - elsif ((d_i = X"90" or - d_i = X"B0" or - d_i = X"F0" or - d_i = X"30" or - d_i = X"D0" or - d_i = X"10" or - d_i = X"50" or - d_i = X"70" or - d_i = X"80") and (rdy_i = '1')) then - csm_next_state <= s268; - elsif ((d_i = X"4C" or - d_i = X"6C" or - d_i = X"7C") and (rdy_i = '1')) then - csm_next_state <= jmp1; - elsif ((d_i = X"20") and (rdy_i = '1')) then - csm_next_state <= jsr1; - elsif ((d_i = X"68") and (rdy_i = '1')) then - csm_next_state <= pla1; - elsif ((d_i = X"FA") and (rdy_i = '1')) then - csm_next_state <= pla1; - elsif ((d_i = X"C6" or - d_i = X"E6" or - d_i = X"66" or - d_i = X"06" or - d_i = X"46" or - d_i = X"26" or - d_i (3 downto 0) = X"7" or - d_i = X"14" or - d_i = X"04") and (rdy_i = '1')) then - csm_next_state <= s237; - elsif ((d_i = X"D6" or - d_i = X"F6" or - d_i = X"76" or - d_i = X"16" or - d_i = X"56" or - d_i = X"36") and (rdy_i = '1')) then - csm_next_state <= s238; - elsif ((d_i = X"CE" or - d_i = X"EE" or - d_i = X"6E" or - d_i = X"0E" or - d_i = X"4E" or - d_i = X"2E" or - d_i = X"1C" or - d_i = X"0C") and (rdy_i = '1')) then - csm_next_state <= s239; - elsif ((d_i = X"DE" or - d_i = X"FE" or - d_i = X"7E" or - d_i = X"1E" or - d_i = X"5E" or - d_i = X"3E") and (rdy_i = '1')) then - csm_next_state <= s240; - elsif ((d_i = X"09" or - d_i = X"29" or - d_i = X"49" or - d_i = X"69" or - d_i = X"89" or - d_i = X"A0" or - d_i = X"A2" or - d_i = X"A9" or - d_i = X"C9" or - d_i = X"E0" or - d_i = X"C0" or - d_i = X"E9") and (rdy_i = '1')) then - csm_next_state <= imm1; - elsif ((d_i = X"05" or - d_i = X"25" or - d_i = X"45" or - d_i = X"65" or - d_i = X"A5" or - d_i = X"24" or - d_i = X"C5" or - d_i = X"E4" or - d_i = X"C4" or - d_i = X"A6" or - d_i = X"A4" or - d_i = X"E5" or - d_i = X"85" or - d_i = X"86" or - d_i = X"84" or - d_i = X"64") and (rdy_i = '1')) then - csm_next_state <= zp1; - elsif ((d_i = X"15" or - d_i = X"35" or - d_i = X"55" or - d_i = X"75" or - d_i = X"B5" or - d_i = X"34" or - d_i = X"D5" or - d_i = X"B4" or - d_i = X"F5" or - d_i = X"95" or - d_i = X"94" or - d_i = X"74") and (rdy_i = '1')) then - csm_next_state <= zpx1; - elsif ((d_i = X"B6" or - d_i = X"96") and (rdy_i = '1')) then - csm_next_state <= zpy1; - elsif ((d_i = X"6D" or - d_i = X"2D" or - d_i = X"2C" or - d_i = X"CD" or - d_i = X"CC" or - d_i = X"EC" or - d_i = X"4D" or - d_i = X"AD" or - d_i = X"AE" or - d_i = X"AC" or - d_i = X"0D" or - d_i = X"ED" or - d_i = X"8D" or - d_i = X"8E" or - d_i = X"8C" or - d_i = X"9C") and (rdy_i = '1')) then - csm_next_state <= ab1; - elsif ((d_i = X"7D" or - d_i = X"3D" or - d_i = X"3C" or - d_i = X"DD" or - d_i = X"5D" or - d_i = X"BD" or - d_i = X"BC" or - d_i = X"1D" or - d_i = X"FD" or - d_i = X"9D" or - d_i = X"9E") and (rdy_i = '1')) then - csm_next_state <= absx1; - elsif ((d_i = X"79" or - d_i = X"39" or - d_i = X"D9" or - d_i = X"5D" or - d_i = X"59" or - d_i = X"B9" or - d_i = X"BE" or - d_i = X"19" or - d_i = X"F9" or - d_i = X"99") and (rdy_i = '1')) then - csm_next_state <= absy1; - elsif ((d_i = X"72" or - d_i = X"32" or - d_i = X"D2" or - d_i = X"59" or - d_i = X"52" or - d_i = X"B2" or - d_i = X"12" or - d_i = X"F2" or - d_i = X"92") and (rdy_i = '1')) then - csm_next_state <= ind1; - elsif ((d_i = X"71" or - d_i = X"31" or - d_i = X"D1" or - d_i = X"51" or - d_i = X"B1" or - d_i = X"11" or - d_i = X"F1" or - d_i = X"91") and (rdy_i = '1')) then - csm_next_state <= indy1; - elsif ((d_i = X"61" or - d_i = X"21" or - d_i = X"C1" or - d_i = X"41" or - d_i = X"A1" or - d_i = X"01" or - d_i = X"E1" or - d_i = X"81") and (rdy_i = '1')) then - csm_next_state <= indx1; - elsif ((d_i = X"B8" or - d_i = X"38" or - d_i = X"18" or - d_i = X"F8" or - d_i = X"D8" or - d_i = X"78" or - d_i = X"58" or - d_i = X"0A" or - d_i = X"4A" or - d_i = X"2A" or - d_i = X"6A" or - d_i = X"A8" or - d_i = X"98" or - d_i = X"BA" or - d_i = X"8A" or - d_i = X"AA" or - d_i = X"C8" or - d_i = X"E8" or - d_i = X"1A" or - d_i = X"88" or - d_i = X"CA" or - d_i = X"3A") and (rdy_i = '1')) then - csm_next_state <= imp1; - elsif ((d_i = X"7A") and (rdy_i = '1')) then - csm_next_state <= pla1; - elsif ((d_i = X"28") and (rdy_i = '1')) then - csm_next_state <= plp1; - elsif ((d_i = X"9A") and (rdy_i = '1')) then - csm_next_state <= s10; - elsif ((d_i = X"60") and (rdy_i = '1')) then - csm_next_state <= rts1; - elsif ((d_i = X"40") and (rdy_i = '1')) then - csm_next_state <= rti1; - elsif ((d_i = X"08") and (rdy_i = '1')) then - csm_next_state <= php1; - elsif ((d_i = X"5A") and (rdy_i = '1')) then - csm_next_state <= pha1; - elsif ((d_i = X"DA") and (rdy_i = '1')) then - csm_next_state <= pha1; - elsif ((d_i = X"48") and (rdy_i = '1')) then - csm_next_state <= pha1; - elsif ((d_i = X"EA") and (rdy_i = '1')) then - csm_next_state <= s6; - elsif ((d_i(3 downto 0) = X"3" or - d_i(3 downto 0) = X"B") and (rdy_i = '1')) then - csm_next_state <= FETCH; - elsif ((d_i = X"02" or - d_i = X"22" or - d_i = X"42" or - d_i = X"62" or - d_i = X"82" or - d_i = X"C2" or - d_i = X"E2") and (rdy_i = '1')) then - csm_next_state <= s11; - elsif ((d_i = X"44") and (rdy_i = '1')) then - csm_next_state <= s12; - elsif ((d_i = X"54" or - d_i = X"D4" or - d_i = X"F4") and (rdy_i = '1')) then - csm_next_state <= s14; - elsif ((d_i = X"DC" or - d_i = X"FC") and (rdy_i = '1')) then - csm_next_state <= s15; - elsif ((d_i = X"5C") and (rdy_i = '1')) then - csm_next_state <= s16; - else - csm_next_state <= FETCH; - end if; - when s6 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s6; - end if; - when s10 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s10; - end if; - when s268 => - if (rdy_i = '1' and ( - (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or - (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or - (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or - (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= s305; - else - csm_next_state <= s268; - end if; - when s305 => - if (rdy_i = '1' and - addr_correction = X"00") then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= s306; - else - csm_next_state <= s305; - end if; - when s306 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s306; - end if; - when jmp1 => - if (rdy_i = '1' and - zw_REG_OP = X"4C") then - csm_next_state <= jmp_ex; - elsif (rdy_i = '1' and - zw_REG_OP = X"6C") then - csm_next_state <= jmp2_1; - elsif (rdy_i = '1' and - zw_REG_OP = X"7C") then - csm_next_state <= jmp2_2; - else - csm_next_state <= jmp1; - end if; - when jmp2_1 => - if (rdy_i = '1') then - csm_next_state <= jmp3_1; - else - csm_next_state <= jmp2_1; - end if; - when jmp4_12 => - if (rdy_i = '1') then - csm_next_state <= jmp_ex; - else - csm_next_state <= jmp4_12; - end if; - when jmp_ex => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= jmp_ex; - end if; - when jmp2_2 => - if (rdy_i = '1') then - csm_next_state <= jmp3_2; - else - csm_next_state <= jmp2_2; - end if; - when jmp3_1 => - if (rdy_i = '1') then - csm_next_state <= jmp4_12; - else - csm_next_state <= jmp3_1; - end if; - when jsr1 => - if (rdy_i = '1') then - csm_next_state <= jsr2; - else - csm_next_state <= jsr1; - end if; - when jsr2 => - if (rdy_i = '1') then - csm_next_state <= jsr3; - else - csm_next_state <= jsr2; - end if; - when jsr3 => - if (rdy_i = '1') then - csm_next_state <= jsr4; - else - csm_next_state <= jsr3; - end if; - when jsr4 => - if (rdy_i = '1') then - csm_next_state <= jsr5; - else - csm_next_state <= jsr4; - end if; - when jsr5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= jsr5; - end if; - when brk1 => - if (rdy_i = '1') then - csm_next_state <= brk2; - else - csm_next_state <= brk1; - end if; - when brk2 => - if (rdy_i = '1') then - csm_next_state <= brk3; - else - csm_next_state <= brk2; - end if; - when brk3 => - if (rdy_i = '1') then - csm_next_state <= brk4; - else - csm_next_state <= brk3; - end if; - when brk4 => - if (rdy_i = '1') then - csm_next_state <= brk5; - else - csm_next_state <= brk4; - end if; - when brk6 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= brk6; - end if; - when brk5 => - if (rdy_i = '1') then - csm_next_state <= brk6; - else - csm_next_state <= brk5; - end if; - when rti1 => - if (rdy_i = '1') then - csm_next_state <= rti2; - else - csm_next_state <= rti1; - end if; - when rti2 => - if (rdy_i = '1') then - csm_next_state <= rti3; - else - csm_next_state <= rti2; - end if; - when rti3 => - if (rdy_i = '1') then - csm_next_state <= rti4; - else - csm_next_state <= rti3; - end if; - when rti4 => - if (rdy_i = '1') then - csm_next_state <= rti5; - else - csm_next_state <= rti4; - end if; - when rti5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= rti5; - end if; - when rts1 => - if (rdy_i = '1') then - csm_next_state <= rts2; - else - csm_next_state <= rts1; - end if; - when rts2 => - if (rdy_i = '1') then - csm_next_state <= rts3; - else - csm_next_state <= rts2; - end if; - when rts3 => - if (rdy_i = '1') then - csm_next_state <= rts4; - else - csm_next_state <= rts3; - end if; - when rts4 => - if (rdy_i = '1') then - csm_next_state <= rts5; - else - csm_next_state <= rts4; - end if; - when rts5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= rts5; - end if; - when pha1 => - if (rdy_i = '1') then - csm_next_state <= pha2; - else - csm_next_state <= pha1; - end if; - when pha2 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= pha2; - end if; - when php1 => - if (rdy_i = '1') then - csm_next_state <= php2; - else - csm_next_state <= php1; - end if; - when php2 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= php2; - end if; - when pla1 => - if (rdy_i = '1') then - csm_next_state <= pla2; - else - csm_next_state <= pla1; - end if; - when pla2 => - if (rdy_i = '1') then - csm_next_state <= pla3; - else - csm_next_state <= pla2; - end if; - when pla3 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= pla3; - end if; - when plp1 => - if (rdy_i = '1') then - csm_next_state <= plp2; - else - csm_next_state <= plp1; - end if; - when plp2 => - if (rdy_i = '1') then - csm_next_state <= plp3; - else - csm_next_state <= plp2; - end if; - when plp3 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= plp3; - end if; - when irq1 => - if (rdy_i = '1') then - csm_next_state <= irq2; - else - csm_next_state <= irq1; - end if; - when irq2 => - if (rdy_i = '1') then - csm_next_state <= irq3; - else - csm_next_state <= irq2; - end if; - when irq3 => - if (rdy_i = '1') then - csm_next_state <= irq4; - else - csm_next_state <= irq3; - end if; - when irq5b => - if (rdy_i = '1') then - csm_next_state <= irq6b; - else - csm_next_state <= irq5b; - end if; - when irq5a => - if (rdy_i = '1') then - csm_next_state <= irq6a; - else - csm_next_state <= irq5a; - end if; - when irq4 => - if (rdy_i = '1' and - nmi_i = '1') then - csm_next_state <= irq5a; - elsif (rdy_i = '1') then - csm_next_state <= irq5b; - else - csm_next_state <= irq4; - end if; - when irq6a => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= irq6a; - end if; - when s11 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s11; - end if; - when s12 => - if (rdy_i = '1') then - csm_next_state <= s20; - else - csm_next_state <= s12; - end if; - when s20 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s20; - end if; - when s14 => - if (rdy_i = '1') then - csm_next_state <= s21; - else - csm_next_state <= s14; - end if; - when s21 => - if (rdy_i = '1') then - csm_next_state <= s23; - else - csm_next_state <= s21; - end if; - when s23 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s23; - end if; - when s15 => - if (rdy_i = '1') then - csm_next_state <= s25; - else - csm_next_state <= s15; - end if; - when s25 => - if (rdy_i = '1') then - csm_next_state <= s28; - else - csm_next_state <= s25; - end if; - when s28 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s28; - end if; - when s16 => - if (rdy_i = '1') then - csm_next_state <= s30; - else - csm_next_state <= s16; - end if; - when s30 => - if (rdy_i = '1') then - csm_next_state <= s31; - else - csm_next_state <= s30; - end if; - when s31 => - if (rdy_i = '1') then - csm_next_state <= s32; - else - csm_next_state <= s31; - end if; - when s32 => - if (rdy_i = '1') then - csm_next_state <= s34; - else - csm_next_state <= s32; - end if; - when s33 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s33; - end if; - when s34 => - if (rdy_i = '1') then - csm_next_state <= s36; - else - csm_next_state <= s34; - end if; - when s36 => - if (rdy_i = '1') then - csm_next_state <= s33; - else - csm_next_state <= s36; - end if; - when jmp3_2 => - if (rdy_i = '1') then - csm_next_state <= jmp4_12; - else - csm_next_state <= jmp3_2; - end if; - when s270 => - if (rdy_i = '1') then - csm_next_state <= s271; - else - csm_next_state <= s270; - end if; - when s307 => - if (rdy_i = '1' and - addr_correction = X"00") then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= s309; - else - csm_next_state <= s307; - end if; - when s308 => - if (rdy_i = '1' and ( - (zw_b1(0) = '0' and zw_REG_OP = X"8F") or - (zw_b1(1) = '0' and zw_REG_OP = X"9F") or - (zw_b1(2) = '0' and zw_REG_OP = X"AF") or - (zw_b1(3) = '0' and zw_REG_OP = X"BF") or - (zw_b1(4) = '0' and zw_REG_OP = X"CF") or - (zw_b1(5) = '0' and zw_REG_OP = X"DF") or - (zw_b1(6) = '0' and zw_REG_OP = X"EF") or - (zw_b1(7) = '0' and zw_REG_OP = X"FF") or - (zw_b1(0) = '1' and zw_REG_OP = X"0F") or - (zw_b1(1) = '1' and zw_REG_OP = X"1F") or - (zw_b1(2) = '1' and zw_REG_OP = X"2F") or - (zw_b1(3) = '1' and zw_REG_OP = X"3F") or - (zw_b1(4) = '1' and zw_REG_OP = X"4F") or - (zw_b1(5) = '1' and zw_REG_OP = X"5F") or - (zw_b1(6) = '1' and zw_REG_OP = X"6F") or - (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= s307; - else - csm_next_state <= s308; - end if; - when s271 => - if (rdy_i = '1') then - csm_next_state <= s272; - else - csm_next_state <= s271; - end if; - when s272 => - if (rdy_i = '1') then - csm_next_state <= s308; - else - csm_next_state <= s272; - end if; - when s309 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s309; - end if; - when RES0 => - csm_next_state <= res2; - when zp1 => - if (rdy_i = '1' and - (zw_REG_OP = X"85" OR - zw_REG_OP = X"86" OR - zw_REG_OP = X"64" OR - zw_REG_OP = X"84")) then - csm_next_state <= zp2w; - elsif (rdy_i = '1') then - csm_next_state <= zp2; - else - csm_next_state <= zp1; - end if; - when zp2 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"65" OR - zw_REG_OP = X"E5")) then - csm_next_state <= zp3; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zp2; - end if; - when zpx1 => - if (rdy_i = '1') then - csm_next_state <= zpx2; - else - csm_next_state <= zpx1; - end if; - when zpx2 => - if (rdy_i = '1' and - (zw_REG_OP = X"95" OR - zw_REG_OP = X"74" OR - zw_REG_OP = X"94")) then - csm_next_state <= zpx3w; - elsif (rdy_i = '1') then - csm_next_state <= zpx3; - else - csm_next_state <= zpx2; - end if; - when zpx3 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"75" OR - zw_REG_OP = X"F5")) then - csm_next_state <= zpx4; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zpx3; - end if; - when ab1 => - if (rdy_i = '1') then - csm_next_state <= ab2; - else - csm_next_state <= ab1; - end if; - when ab2 => - if (rdy_i = '1' and - (zw_REG_OP = X"8D" OR - zw_REG_OP = X"8E" OR - zw_REG_OP = X"9C" OR - zw_REG_OP = X"8C")) then - csm_next_state <= ab3w; - elsif (rdy_i = '1') then - csm_next_state <= ab3; - else - csm_next_state <= ab2; - end if; - when ab3 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"6D" OR - zw_REG_OP = X"ED")) then - csm_next_state <= ab4; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ab3; - end if; - when absx1 => - if (rdy_i = '1') then - csm_next_state <= absx2; - else - csm_next_state <= absx1; - end if; - when absx2 => - if (rdy_i = '1' and - (zw_REG_OP = X"9D" OR - zw_REG_OP = X"9E")) then - csm_next_state <= absx3w; - elsif (rdy_i = '1') then - csm_next_state <= absx3; - else - csm_next_state <= absx2; - end if; - when absx4 => - if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or - zw_REG_OP = X"FD") and - reg_F(3) = '1')) then - csm_next_state <= absx5; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absx4; - end if; - when absx3 => - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or - zw_REG_OP = X"FD") and - reg_F(3) = '1')) then - csm_next_state <= absx5; - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= absx4; - else - csm_next_state <= absx3; - end if; - when ind1 => - if (rdy_i = '1') then - csm_next_state <= ind2; - else - csm_next_state <= ind1; - end if; - when ind3 => - if (rdy_i = '1' and - zw_REG_OP = X"92") then - csm_next_state <= ind4w; - elsif (rdy_i = '1') then - csm_next_state <= ind4; - else - csm_next_state <= ind3; - end if; - when ind4 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"72" OR - zw_REG_OP = X"F2")) then - csm_next_state <= ind5; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ind4; - end if; - when ind2 => - if (rdy_i = '1') then - csm_next_state <= ind3; - else - csm_next_state <= ind2; - end if; - when indy1 => - if (rdy_i = '1') then - csm_next_state <= indy2; - else - csm_next_state <= indy1; - end if; - when indy2 => - if (rdy_i = '1') then - csm_next_state <= indy3; - else - csm_next_state <= indy2; - end if; - when indy3 => - if (rdy_i = '1' and - zw_REG_OP = X"91") then - csm_next_state <= indy4w; - elsif (rdy_i = '1') then - csm_next_state <= indy4; - else - csm_next_state <= indy3; - end if; - when indy5 => - if ((rdy_i = '1') and ((zw_REG_OP = X"71" or - zw_REG_OP = X"F1") and - reg_F(3) = '1')) then - csm_next_state <= indy6; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indy5; - end if; - when indy4 => - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or - zw_REG_OP = X"F1") and - reg_F(3) = '1')) then - csm_next_state <= indy6; - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= indy5; - else - csm_next_state <= indy4; - end if; - when indx1 => - if (rdy_i = '1') then - csm_next_state <= indx2; - else - csm_next_state <= indx1; - end if; - when indx4 => - if (rdy_i = '1' and - zw_REG_OP = X"81") then - csm_next_state <= indx5w; - elsif (rdy_i = '1') then - csm_next_state <= indx5; - else - csm_next_state <= indx4; - end if; - when indx2 => - if (rdy_i = '1') then - csm_next_state <= indx3; - else - csm_next_state <= indx2; - end if; - when indx3 => - if (rdy_i = '1') then - csm_next_state <= indx4; - else - csm_next_state <= indx3; - end if; - when indx5 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"61" OR - zw_REG_OP = X"E1")) then - csm_next_state <= indx6; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indx5; - end if; - when zpy1 => - if (rdy_i = '1') then - csm_next_state <= zpy2; - else - csm_next_state <= zpy1; - end if; - when zpy2 => - if (rdy_i = '1' and - zw_REG_OP = X"96") then - csm_next_state <= zpy3w; - elsif (rdy_i = '1') then - csm_next_state <= zpy3; - else - csm_next_state <= zpy2; - end if; - when zpy3 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zpy3; - end if; - when absy2 => - if (rdy_i = '1' and - zw_REG_OP = X"99") then - csm_next_state <= absy3w; - elsif (rdy_i = '1') then - csm_next_state <= absy3; - else - csm_next_state <= absy2; - end if; - when absy1 => - if (rdy_i = '1') then - csm_next_state <= absy2; - else - csm_next_state <= absy1; - end if; - when absy4 => - if ((rdy_i = '1') and ((zw_REG_OP = X"79" or - zw_REG_OP = X"F9") and - reg_F(3) = '1')) then - csm_next_state <= absy5; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absy4; - end if; - when absy3 => - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or - zw_REG_OP = X"F9") and - reg_F(3) = '1')) then - csm_next_state <= absy5; - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= absy4; - else - csm_next_state <= absy3; - end if; - when imm1 => - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"69" OR - zw_REG_OP = X"E9")) then - csm_next_state <= imm2; - elsif (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= imm1; - end if; - when imp1 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= imp1; - end if; - when irq6b => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= irq6b; - end if; - when absx5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absx5; - end if; - when absy5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absy5; - end if; - when indy6 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indy6; - end if; - when s237 => - if (rdy_i = '1') then - csm_next_state <= s348; - else - csm_next_state <= s237; - end if; - when s348 => - if (rdy_i = '1' and - (zw_REG_OP = X"C6" or - zw_REG_OP = X"E6")) then - csm_next_state <= s254; - elsif (rdy_i = '1') then - csm_next_state <= s256; - else - csm_next_state <= s348; - end if; - when s254 => - if (rdy_i = '1') then - csm_next_state <= s255; - else - csm_next_state <= s254; - end if; - when s255 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s255; - end if; - when s238 => - if (rdy_i = '1') then - csm_next_state <= s257; - else - csm_next_state <= s238; - end if; - when s257 => - if (rdy_i = '1') then - csm_next_state <= s350; - else - csm_next_state <= s257; - end if; - when s350 => - if (rdy_i = '1' and - (zw_REG_OP = X"D6" or - zw_REG_OP = X"F6")) then - csm_next_state <= s258; - elsif (rdy_i = '1') then - csm_next_state <= s261; - else - csm_next_state <= s350; - end if; - when s258 => - if (rdy_i = '1') then - csm_next_state <= s259; - else - csm_next_state <= s258; - end if; - when s259 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s259; - end if; - when s239 => - if (rdy_i = '1') then - csm_next_state <= s260; - else - csm_next_state <= s239; - end if; - when s260 => - if (rdy_i = '1') then - csm_next_state <= s352; - else - csm_next_state <= s260; - end if; - when s352 => - if (rdy_i = '1' and - (zw_REG_OP = X"CE" or - zw_REG_OP = X"EE")) then - csm_next_state <= s263; - elsif (rdy_i = '1') then - csm_next_state <= s265; - else - csm_next_state <= s352; - end if; - when s263 => - if (rdy_i = '1') then - csm_next_state <= s264; - else - csm_next_state <= s263; - end if; - when s264 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s264; - end if; - when s240 => - if (rdy_i = '1') then - csm_next_state <= s266; - else - csm_next_state <= s240; - end if; - when s266 => - if (rdy_i = '1') then - csm_next_state <= s353; - else - csm_next_state <= s266; - end if; - when s353 => - if (rdy_i = '1' AND - zw_reg_0flag = '0' and - (zw_REG_OP = X"DE" or - zw_REG_OP = X"FE")) then - csm_next_state <= s269; - elsif (rdy_i = '1' and - (zw_REG_OP = X"DE" or - zw_REG_OP = X"FE")) then - csm_next_state <= s354; - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= s274; - elsif (rdy_i = '1') then - csm_next_state <= s355; - else - csm_next_state <= s353; - end if; - when s354 => - if (rdy_i = '1') then - csm_next_state <= s269; - else - csm_next_state <= s354; - end if; - when s269 => - if (rdy_i = '1') then - csm_next_state <= s273; - else - csm_next_state <= s269; - end if; - when s273 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= s273; - end if; - when zp2w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zp2w; - end if; - when zpx3w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zpx3w; - end if; - when zpy3w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zpy3w; - end if; - when ab3w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ab3w; - end if; - when absx4w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absx4w; - end if; - when absx3w => - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= absx4w; - else - csm_next_state <= absx3w; - end if; - when absy4w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= absy4w; - end if; - when absy3w => - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= absy4w; - else - csm_next_state <= absy3w; - end if; - when ind4w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ind4w; - end if; - when indx5w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indx5w; - end if; - when indy5w => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indy5w; - end if; - when indy4w => - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - csm_next_state <= FETCH; - elsif (rdy_i = '1') then - csm_next_state <= indy5w; - else - csm_next_state <= indy4w; - end if; - when s256 => - if (rdy_i = '1') then - csm_next_state <= s255; - else - csm_next_state <= s256; - end if; - when s261 => - if (rdy_i = '1') then - csm_next_state <= s259; - else - csm_next_state <= s261; - end if; - when s265 => - if (rdy_i = '1') then - csm_next_state <= s264; - else - csm_next_state <= s265; - end if; - when s274 => - if (rdy_i = '1') then - csm_next_state <= s273; - else - csm_next_state <= s274; - end if; - when s355 => - if (rdy_i = '1') then - csm_next_state <= s274; - else - csm_next_state <= s355; - end if; - when zp3 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zp3; - end if; - when zpx4 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= zpx4; - end if; - when ab4 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ab4; - end if; - when ind5 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= ind5; - end if; - when indx6 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= indx6; - end if; - when imm2 => - if (rdy_i = '1') then - csm_next_state <= FETCH; - else - csm_next_state <= imm2; - end if; - when others => - csm_next_state <= RES; - end case; - end process csm_nextstate_proc; - - ----------------------------------------------------------------- - csm_output_proc : process ( - addr_correction, - adr_nxt_pc_i, - adr_pc_i, - adr_sp_i, - csm_current_state, - d_i, - d_regs_out_i, - irq_n_i, - nmi_i, - q_x_i, - q_y_i, - rdy_i, - reg_F, - sel_pc_in, - sel_pc_val, - sel_sp_as, - sel_sp_in, - sig_D_OUT, - sig_PC, - sig_RD, - sig_RWn, - sig_WR, - zw_REG_OP, - zw_b1, - zw_b11, - zw_b12, - zw_b2, - zw_b3, - zw_b4, - zw_b5, - zw_b6, - zw_reg_0flag, - zw_w3 - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - a_o <= sig_PC; - adr_o <= X"0000"; - ch_a_o <= X"00"; - ch_b_o <= X"00"; - d_o <= sig_D_OUT; - ld_o <= "00"; - ld_pc_o <= '0'; - ld_sp_o <= '0'; - offset_o <= X"0000"; - rd_o <= sig_RD; - rst_nmi_o <= '0'; - sel_pc_in_o <= sel_pc_in; - sel_pc_val_o <= sel_pc_val; - sel_sp_as_o <= sel_sp_as; - sel_sp_in_o <= sel_sp_in; - wr_n_o <= sig_RWn; - wr_o <= sig_WR; - -- Default Assignment To Internals - adc_sbc_finished <= '0'; - addr_correction <= X"00"; - irq_finished <= '0'; - op_fetch <= '0'; - op_finished <= '0'; - rmb_started <= '0'; - rst_finished <= '0'; - sel_pc_in <= '0'; - sel_pc_val <= "00"; - sel_sp_as <= '1'; - sel_sp_in <= '0'; - sig_D_OUT <= X"00"; - sig_PC <= X"0000"; - sig_RD <= '1'; - sig_RWn <= '1'; - sig_SYNC <= '0'; - sig_WR <= '0'; - - -- Combined Actions - case csm_current_state is - when res2 => - sig_PC <= adr_pc_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when res4 => - sig_PC <= adr_sp_i; - adr_o <= X"FFFB"; - sel_pc_in <= '1'; - sel_pc_val <= "00"; - ld_pc_o <= '1'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when res5 => - sig_PC <= adr_sp_i; - when res6 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when res7 => - sig_PC <= adr_pc_i; - adr_o <= d_i & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - rst_finished <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when res3 => - sig_PC <= adr_sp_i; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when RES => - sig_PC <= adr_pc_i; - sig_SYNC <= '1'; - when FETCH => - sig_PC <= adr_pc_i; - op_fetch <= '1'; - sig_RWn <= '1'; - sig_RD <= '1'; - sig_SYNC <= NOT (rdy_i); - ld_pc_o <= '1'; - if ((d_i = X"00") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((nmi_i = '1') and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((irq_n_i = '0' and - reg_F(2) = '0') and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"8F" or - d_i = X"9F" or - d_i = X"AF" or - d_i = X"BF" or - d_i = X"CF" or - d_i = X"DF" or - d_i = X"EF" or - d_i = X"FF" or - d_i = X"0F" or - d_i = X"1F" or - d_i = X"2F" or - d_i = X"3F" or - d_i = X"4F" or - d_i = X"5F" or - d_i = X"6F" or - d_i = X"7F") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"90" or - d_i = X"B0" or - d_i = X"F0" or - d_i = X"30" or - d_i = X"D0" or - d_i = X"10" or - d_i = X"50" or - d_i = X"70" or - d_i = X"80") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"4C" or - d_i = X"6C" or - d_i = X"7C") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"20") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"68") and (rdy_i = '1')) then - elsif ((d_i = X"FA") and (rdy_i = '1')) then - elsif ((d_i = X"C6" or - d_i = X"E6" or - d_i = X"66" or - d_i = X"06" or - d_i = X"46" or - d_i = X"26" or - d_i (3 downto 0) = X"7" or - d_i = X"14" or - d_i = X"04") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"D6" or - d_i = X"F6" or - d_i = X"76" or - d_i = X"16" or - d_i = X"56" or - d_i = X"36") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"CE" or - d_i = X"EE" or - d_i = X"6E" or - d_i = X"0E" or - d_i = X"4E" or - d_i = X"2E" or - d_i = X"1C" or - d_i = X"0C") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"DE" or - d_i = X"FE" or - d_i = X"7E" or - d_i = X"1E" or - d_i = X"5E" or - d_i = X"3E") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"09" or - d_i = X"29" or - d_i = X"49" or - d_i = X"69" or - d_i = X"89" or - d_i = X"A0" or - d_i = X"A2" or - d_i = X"A9" or - d_i = X"C9" or - d_i = X"E0" or - d_i = X"C0" or - d_i = X"E9") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"05" or - d_i = X"25" or - d_i = X"45" or - d_i = X"65" or - d_i = X"A5" or - d_i = X"24" or - d_i = X"C5" or - d_i = X"E4" or - d_i = X"C4" or - d_i = X"A6" or - d_i = X"A4" or - d_i = X"E5" or - d_i = X"85" or - d_i = X"86" or - d_i = X"84" or - d_i = X"64") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"15" or - d_i = X"35" or - d_i = X"55" or - d_i = X"75" or - d_i = X"B5" or - d_i = X"34" or - d_i = X"D5" or - d_i = X"B4" or - d_i = X"F5" or - d_i = X"95" or - d_i = X"94" or - d_i = X"74") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"B6" or - d_i = X"96") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"6D" or - d_i = X"2D" or - d_i = X"2C" or - d_i = X"CD" or - d_i = X"CC" or - d_i = X"EC" or - d_i = X"4D" or - d_i = X"AD" or - d_i = X"AE" or - d_i = X"AC" or - d_i = X"0D" or - d_i = X"ED" or - d_i = X"8D" or - d_i = X"8E" or - d_i = X"8C" or - d_i = X"9C") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"7D" or - d_i = X"3D" or - d_i = X"3C" or - d_i = X"DD" or - d_i = X"5D" or - d_i = X"BD" or - d_i = X"BC" or - d_i = X"1D" or - d_i = X"FD" or - d_i = X"9D" or - d_i = X"9E") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"79" or - d_i = X"39" or - d_i = X"D9" or - d_i = X"5D" or - d_i = X"59" or - d_i = X"B9" or - d_i = X"BE" or - d_i = X"19" or - d_i = X"F9" or - d_i = X"99") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"72" or - d_i = X"32" or - d_i = X"D2" or - d_i = X"59" or - d_i = X"52" or - d_i = X"B2" or - d_i = X"12" or - d_i = X"F2" or - d_i = X"92") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"71" or - d_i = X"31" or - d_i = X"D1" or - d_i = X"51" or - d_i = X"B1" or - d_i = X"11" or - d_i = X"F1" or - d_i = X"91") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"61" or - d_i = X"21" or - d_i = X"C1" or - d_i = X"41" or - d_i = X"A1" or - d_i = X"01" or - d_i = X"E1" or - d_i = X"81") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"B8" or - d_i = X"38" or - d_i = X"18" or - d_i = X"F8" or - d_i = X"D8" or - d_i = X"78" or - d_i = X"58" or - d_i = X"0A" or - d_i = X"4A" or - d_i = X"2A" or - d_i = X"6A" or - d_i = X"A8" or - d_i = X"98" or - d_i = X"BA" or - d_i = X"8A" or - d_i = X"AA" or - d_i = X"C8" or - d_i = X"E8" or - d_i = X"1A" or - d_i = X"88" or - d_i = X"CA" or - d_i = X"3A") and (rdy_i = '1')) then - elsif ((d_i = X"7A") and (rdy_i = '1')) then - elsif ((d_i = X"28") and (rdy_i = '1')) then - elsif ((d_i = X"9A") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"60") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"40") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"08") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"5A") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"DA") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"48") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"EA") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i(3 downto 0) = X"3" or - d_i(3 downto 0) = X"B") and (rdy_i = '1')) then - ld_o <= "11"; - sig_SYNC <= '1'; - elsif ((d_i = X"02" or - d_i = X"22" or - d_i = X"42" or - d_i = X"62" or - d_i = X"82" or - d_i = X"C2" or - d_i = X"E2") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"44") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"54" or - d_i = X"D4" or - d_i = X"F4") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"DC" or - d_i = X"FC") and (rdy_i = '1')) then - ld_o <= "11"; - elsif ((d_i = X"5C") and (rdy_i = '1')) then - ld_o <= "11"; - end if; - when s6 => - sig_PC <= adr_pc_i; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s10 => - sig_PC <= adr_pc_i; - sel_sp_in <= '1'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - adr_o <= X"01" & q_x_i; - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when s268 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and ( - (reg_F(0) = '1' and zw_REG_OP = X"90") or (reg_F(0) = '0' and zw_REG_OP = X"B0") or - (reg_F(1) = '0' and zw_REG_OP = X"F0") or (reg_F(7) = '0' and zw_REG_OP = X"30") or - (reg_F(1) = '1' and zw_REG_OP = X"D0") or (reg_F(7) = '1' and zw_REG_OP = X"10") or - (reg_F(6) = '1' and zw_REG_OP = X"50") or (reg_F(6) = '0' and zw_REG_OP = X"70"))) then - ld_o <= "11"; - sig_SYNC <= '1'; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when s305 => - sig_PC <= adr_pc_i; - addr_correction <= zw_b3 XOR adr_nxt_pc_i (15 downto 8); - sel_pc_in <= '0'; - sel_pc_val <= "10"; - offset_o <= (zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(6 downto 0)); - ld_pc_o <= '1'; - if (rdy_i = '1' and - addr_correction = X"00") then - ld_o <= "11"; - sig_SYNC <= '1'; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when s306 => - sig_PC <= zw_b3 & adr_pc_i (7 downto 0); - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when jmp1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"4C") then - ld_o <= "11"; - elsif (rdy_i = '1' and - zw_REG_OP = X"6C") then - ld_o <= "11"; - elsif (rdy_i = '1' and - zw_REG_OP = X"7C") then - ld_o <= "11"; - end if; - when jmp2_1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jmp4_12 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jmp_ex => - sig_PC <= adr_pc_i; - adr_o <= d_i & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when jmp2_2 => - sig_PC <= adr_pc_i; - when jmp3_1 => - sig_PC <= zw_b6 & zw_b5; - adr_o <= zw_b6 & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jsr1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jsr2 => - sig_PC <= adr_sp_i; - when jsr3 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jsr4 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b12; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when jsr5 => - sig_PC <= adr_pc_i; - adr_o <= d_i & zw_b1; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when brk1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when brk2 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when brk3 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b12; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when brk4 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - ld_sp_o <= '1'; - irq_finished <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when brk6 => - sig_PC <= X"FFFF"; - adr_o <= d_i & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when brk5 => - sig_PC <= X"FFFE"; - when rti1 => - sig_PC <= adr_pc_i; - when rti2 => - sig_PC <= adr_sp_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rti3 => - sig_PC <= adr_sp_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - op_finished <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rti4 => - sig_PC <= adr_sp_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rti5 => - sig_PC <= adr_sp_i; - adr_o <= d_i & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when rts1 => - sig_PC <= adr_pc_i; - when rts2 => - sig_PC <= adr_sp_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rts3 => - sig_PC <= adr_sp_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rts4 => - sig_PC <= adr_sp_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when rts5 => - sig_PC <= zw_b6 & zw_b5; - adr_o <= zw_b6 & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "00"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when pha1 => - sig_PC <= adr_pc_i; - when pha2 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= d_regs_out_i; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when php1 => - sig_PC <= adr_pc_i; - when php2 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= reg_F OR X"30"; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when pla1 => - sig_PC <= adr_pc_i; - when pla2 => - sig_PC <= adr_pc_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_pc_o <= '1'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when pla3 => - sig_PC <= adr_sp_i; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when plp1 => - sig_PC <= adr_pc_i; - when plp2 => - sig_PC <= adr_pc_i; - sel_sp_in <= '0'; - sel_sp_as <= '0'; - ld_pc_o <= '1'; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when plp3 => - sig_PC <= adr_sp_i; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when irq1 => - sig_PC <= adr_pc_i; - when irq2 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when irq3 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b12; - ld_sp_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when irq5b => - sig_PC <= X"FFFE"; - when irq5a => - sig_PC <= X"FFFA"; - when irq4 => - sig_PC <= adr_sp_i; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - ld_sp_o <= '1'; - irq_finished <= '1'; - if (rdy_i = '1' and - nmi_i = '1') then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when irq6a => - sig_PC <= X"FFFB"; - adr_o <= d_i & zw_b5; - rst_nmi_o <= '1'; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when s11 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when s12 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s20 => - sig_PC <= adr_pc_i; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s14 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s21 => - sig_PC <= adr_pc_i; - when s23 => - sig_PC <= adr_pc_i; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s15 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s25 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s28 => - sig_PC <= adr_pc_i; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s16 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s30 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s31 => - sig_PC <= adr_pc_i; - when s32 => - sig_PC <= adr_pc_i; - when s33 => - sig_PC <= adr_pc_i; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s34 => - sig_PC <= adr_pc_i; - when s36 => - sig_PC <= adr_pc_i; - when jmp3_2 => - sig_PC <= zw_b6 & zw_b5; - adr_o <= zw_b6 & zw_b5; - offset_o <= (X"00" & q_x_i); - sel_pc_in <= '1'; - sel_pc_val <= "10"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s270 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s307 => - sig_PC <= zw_w3; - addr_correction <= zw_b3 XOR adr_nxt_pc_i (15 downto 8); - sel_pc_in <= '0'; - sel_pc_val <= "10"; - offset_o <= (zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(6 downto 0)); - ld_pc_o <= '1'; - if (rdy_i = '1' and - addr_correction = X"00") then - ld_o <= "11"; - sig_SYNC <= '1'; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when s308 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and ( - (zw_b1(0) = '0' and zw_REG_OP = X"8F") or - (zw_b1(1) = '0' and zw_REG_OP = X"9F") or - (zw_b1(2) = '0' and zw_REG_OP = X"AF") or - (zw_b1(3) = '0' and zw_REG_OP = X"BF") or - (zw_b1(4) = '0' and zw_REG_OP = X"CF") or - (zw_b1(5) = '0' and zw_REG_OP = X"DF") or - (zw_b1(6) = '0' and zw_REG_OP = X"EF") or - (zw_b1(7) = '0' and zw_REG_OP = X"FF") or - (zw_b1(0) = '1' and zw_REG_OP = X"0F") or - (zw_b1(1) = '1' and zw_REG_OP = X"1F") or - (zw_b1(2) = '1' and zw_REG_OP = X"2F") or - (zw_b1(3) = '1' and zw_REG_OP = X"3F") or - (zw_b1(4) = '1' and zw_REG_OP = X"4F") or - (zw_b1(5) = '1' and zw_REG_OP = X"5F") or - (zw_b1(6) = '1' and zw_REG_OP = X"6F") or - (zw_b1(7) = '1' and zw_REG_OP = X"7F"))) then - ld_o <= "11"; - sig_SYNC <= '1'; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when s271 => - sig_PC <= X"00" & zw_b2; - when s272 => - sig_PC <= X"00" & zw_b2; - when s309 => - sig_PC <= zw_b3 & adr_pc_i(7 downto 0); - offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & - zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0)); - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when RES0 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - ld_o <= "11"; - when zp1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - (zw_REG_OP = X"85" OR - zw_REG_OP = X"86" OR - zw_REG_OP = X"64" OR - zw_REG_OP = X"84")) then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when zp2 => - sig_PC <= X"00" & zw_b5; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"65" OR - zw_REG_OP = X"E5")) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zpx1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when zpx2 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= q_x_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - (zw_REG_OP = X"95" OR - zw_REG_OP = X"74" OR - zw_REG_OP = X"94")) then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when zpx3 => - sig_PC <= X"00" & zw_b1; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"75" OR - zw_REG_OP = X"F5")) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when ab1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when ab2 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - (zw_REG_OP = X"8D" OR - zw_REG_OP = X"8E" OR - zw_REG_OP = X"9C" OR - zw_REG_OP = X"8C")) then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when ab3 => - sig_PC <= zw_b6 & zw_b5; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"6D" OR - zw_REG_OP = X"ED")) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absx1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when absx2 => - sig_PC <= adr_pc_i; - ch_a_o <= zw_b5; - ch_b_o <= q_x_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - (zw_REG_OP = X"9D" OR - zw_REG_OP = X"9E")) then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when absx4 => - sig_PC <= zw_b3 & zw_b1; - op_finished <= '1'; - adc_sbc_finished <= reg_F(3); - if ((rdy_i = '1') and ((zw_REG_OP = X"7D" or - zw_REG_OP = X"FD") and - reg_F(3) = '1')) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absx3 => - sig_PC <= zw_b6 & zw_b1; - ch_a_o <= zw_b6; - ch_b_o <= "0000000" & zw_reg_0flag; - op_finished <= NOT(zw_reg_0flag); - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"7D" or - zw_REG_OP = X"FD") and - reg_F(3) = '1')) then - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when ind1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when ind3 => - sig_PC <= X"00" & zw_b1; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"92") then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when ind4 => - sig_PC <= zw_b5 & zw_b6; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"72" OR - zw_REG_OP = X"F2")) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when ind2 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= X"01"; - when indy1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when indy2 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= X"01"; - when indy3 => - sig_PC <= X"00" & zw_b1; - ch_a_o <= zw_b2; - ch_b_o <= q_y_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"91") then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when indy5 => - sig_PC <= zw_b3 & zw_b6; - op_finished <= '1'; - adc_sbc_finished <= reg_F(3); - if ((rdy_i = '1') and ((zw_REG_OP = X"71" or - zw_REG_OP = X"F1") and - reg_F(3) = '1')) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indy4 => - sig_PC <= zw_b5 & zw_b6; - ch_a_o <= zw_b5; - ch_b_o <= "0000000" & zw_reg_0flag; - op_finished <= NOT(zw_reg_0flag); - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"71" or - zw_REG_OP = X"F1") and - reg_F(3) = '1')) then - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when indx1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when indx4 => - sig_PC <= X"00" & zw_b6; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"81") then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when indx2 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= q_x_i; - when indx3 => - sig_PC <= X"00" & zw_b1; - ch_a_o <= zw_b1; - ch_b_o <= X"01"; - when indx5 => - sig_PC <= zw_b2 & zw_b5; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"61" OR - zw_REG_OP = X"E1")) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zpy1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when zpy2 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= q_y_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"96") then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when zpy3 => - sig_PC <= X"00" & zw_b1; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absy2 => - sig_PC <= adr_pc_i; - ch_a_o <= zw_b5; - ch_b_o <= q_y_i; - ld_pc_o <= '1'; - if (rdy_i = '1' and - zw_REG_OP = X"99") then - ld_o <= "11"; - elsif (rdy_i = '1') then - ld_o <= "11"; - end if; - when absy1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when absy4 => - sig_PC <= zw_b3 & zw_b1; - op_finished <= '1'; - adc_sbc_finished <= reg_F(3); - if ((rdy_i = '1') and ((zw_REG_OP = X"79" or - zw_REG_OP = X"F9") and - reg_F(3) = '1')) then - elsif (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absy3 => - sig_PC <= zw_b6 & zw_b1; - ch_a_o <= zw_b6; - ch_b_o <= "0000000" & zw_reg_0flag; - op_finished <= NOT(zw_reg_0flag); - if ((rdy_i = '1' AND - zw_reg_0flag = '0') and ((zw_REG_OP = X"79" or - zw_REG_OP = X"F9") and - reg_F(3) = '1')) then - elsif (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when imm1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - op_finished <= '1'; - if (rdy_i = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"69" OR - zw_REG_OP = X"E9")) then - elsif (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when imp1 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - op_finished <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when irq6b => - sig_PC <= X"FFFF"; - adr_o <= d_i & zw_b5; - sel_pc_in <= '1'; - sel_pc_val <= "11"; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when absx5 => - sig_PC <= zw_b3 & zw_b1; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absy5 => - sig_PC <= zw_b3 & zw_b1; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indy6 => - sig_PC <= zw_b3 & zw_b6; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s237 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s348 => - sig_PC <= X"00" & zw_b5; - rmb_started <= '1'; - when s254 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b2; - ch_b_o <= zw_b4; - when s255 => - sig_PC <= X"00" & zw_b5; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s238 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - when s257 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= zw_b5; - ch_b_o <= q_x_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s350 => - sig_PC <= X"00" & zw_b1; - rmb_started <= '1'; - when s258 => - sig_PC <= X"00" & zw_b1; - ch_a_o <= zw_b2; - ch_b_o <= zw_b4; - when s259 => - sig_PC <= X"00" & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s239 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s260 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s352 => - sig_PC <= zw_b6 & zw_b5; - rmb_started <= '1'; - when s263 => - sig_PC <= zw_b6 & zw_b5; - ch_a_o <= zw_b2; - ch_b_o <= zw_b4; - when s264 => - sig_PC <= zw_b6 & zw_b5; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when s240 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s266 => - sig_PC <= adr_pc_i; - ch_a_o <= zw_b5; - ch_b_o <= q_x_i; - ld_pc_o <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - end if; - when s353 => - sig_PC <= zw_b6 & zw_b1; - rmb_started <= NOT(zw_reg_0flag); - ch_a_o <= zw_b6; - ch_b_o <= "0000000" & zw_reg_0flag; - when s354 => - sig_PC <= zw_b3 & zw_b1; - when s269 => - sig_PC <= zw_b3 & zw_b1; - ch_a_o <= zw_b2; - ch_b_o <= zw_b4; - when s273 => - sig_PC <= zw_b3 & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zp2w => - sig_PC <= X"00" & zw_b5; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zpx3w => - sig_PC <= X"00" & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zpy3w => - sig_PC <= X"00" & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when ab3w => - sig_PC <= zw_b6 & zw_b5; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absx4w => - sig_PC <= zw_b3 & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absx3w => - sig_PC <= zw_b6 & zw_b1; - ch_a_o <= zw_b6; - ch_b_o <= "0000000" & zw_reg_0flag; - sig_RWn <= zw_reg_0flag; - sig_RD <= zw_reg_0flag; - sig_WR <= NOT(zw_reg_0flag); - sig_D_OUT <= zw_b11; - op_finished <= NOT(zw_reg_0flag); - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when absy4w => - sig_PC <= zw_b3 & zw_b1; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when absy3w => - sig_PC <= zw_b6 & zw_b1; - ch_a_o <= zw_b6; - ch_b_o <= "0000000" & zw_reg_0flag; - sig_RWn <= zw_reg_0flag; - sig_RD <= zw_reg_0flag; - sig_WR <= NOT(zw_reg_0flag); - sig_D_OUT <= zw_b11; - op_finished <= NOT(zw_reg_0flag); - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when ind4w => - sig_PC <= zw_b5 & zw_b6; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indx5w => - sig_PC <= zw_b2 & zw_b5; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indy5w => - sig_PC <= zw_b3 & zw_b6; - sig_RWn <= '0'; - sig_RD <= '0'; - sig_WR <= '1'; - sig_D_OUT <= zw_b11; - op_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indy4w => - sig_PC <= zw_b5 & zw_b6; - ch_a_o <= zw_b5; - ch_b_o <= "0000000" & zw_reg_0flag; - sig_RWn <= zw_reg_0flag; - sig_RD <= zw_reg_0flag; - sig_WR <= NOT(zw_reg_0flag); - sig_D_OUT <= zw_b11; - op_finished <= NOT(zw_reg_0flag); - if (rdy_i = '1' AND - zw_reg_0flag = '0') then - sig_SYNC <= '1'; - end if; - when s256 => - sig_PC <= X"00" & zw_b5; - ch_a_o <= "00000" & zw_REG_OP (6 downto 4) ; - when s261 => - sig_PC <= X"00" & zw_b1; - when s265 => - sig_PC <= zw_b6 & zw_b5; - when s274 => - sig_PC <= zw_b3 & zw_b1; - when s355 => - sig_PC <= zw_b3 & zw_b1; - rmb_started <= '1'; - when zp3 => - sig_PC <= X"00" & zw_b5; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when zpx4 => - sig_PC <= X"00" & zw_b1; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when ab4 => - sig_PC <= zw_b6 & zw_b5; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when ind5 => - sig_PC <= zw_b5 & zw_b6; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when indx6 => - sig_PC <= zw_b2 & zw_b5; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - sig_SYNC <= '1'; - end if; - when imm2 => - sig_PC <= adr_pc_i; - ld_pc_o <= '1'; - adc_sbc_finished <= '1'; - if (rdy_i = '1') then - ld_o <= "11"; - sig_SYNC <= '1'; - end if; - when others => - null; - end case; - end process csm_output_proc; - - ----------------------------------------------------------------- - csm_functions_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_functions_current_state <= f_rst; - -- Default Reset Values - reg_F <= "00110100"; - zw_b10 <= "00" & X"00"; - zw_b14 <= X"00"; - zw_b7 <= "00" & X"00"; - zw_b8 <= "00" & X"00"; - zw_b9 <= "00" & X"00"; - zw_din <= X"00"; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_functions_current_state <= csm_functions_next_state; - -- Default Assignment To Internals - reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0); - zw_b10 <= zw_b10; - zw_b14 <= zw_b14; - zw_b7 <= zw_b7; - zw_b8 <= zw_b8; - zw_b9 <= zw_b9; - zw_din <= zw_din; - - -- Combined Actions - case csm_functions_current_state is - when f_idle => - zw_din <= d_i; - when f_and => - zw_din <= d_i; - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_lda => - zw_din <= d_i; - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_eor => - zw_din <= d_i; - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_cmp => - zw_din <= d_i; - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= c_detect_out; - when f_ora => - zw_din <= d_i; - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_clc => - reg_F(0) <= '0'; - when f_sec => - reg_F(0) <= '1'; - when f_cld => - reg_F(3) <= '0'; - when f_sed => - reg_F(3) <= '1'; - when f_clv => - reg_F(6) <= '0'; - when f_cli => - reg_F(2) <= '0'; - when f_sei => - reg_F(2) <= '1'; - when f_rti => - zw_din <= d_i; - reg_F(7 downto 6) <= zw_din(7 downto 6); - reg_F(3 downto 0) <= zw_din(3 downto 0); - when f_irq => - reg_F(2) <= '1'; - reg_F(3) <= '0'; - when f_res => - reg_F(2) <= '1'; - reg_F(3) <= '0'; - reg_F(5) <= '1'; - when f_bit1 => - zw_din <= d_i; - reg_F(1) <= z_detect_out; - when f_bit2 => - zw_din <= d_i; - reg_F(7) <= zw_din(7); - reg_F(6) <= zw_din(6); - reg_F(1) <= z_detect_out; - when f_de_in_a => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_adc_bin => - zw_din <= d_i; - reg_F(7) <= zw_ALU(7); - reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (NOT zw_din(7))) OR - (NOT zw_ALU(7) AND (q_a_i(7)) AND (zw_din(7))); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= zw_ALU(8); - when f_sbc_bin => - zw_din <= d_i; - reg_F(7) <= zw_ALU(7); - reg_F(6) <= (zw_ALU(7) AND (NOT q_a_i(7)) AND (zw_din(7))) OR - (NOT zw_ALU(7) AND (q_a_i(7)) AND (NOT zw_din(7))); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - reg_F(0) <= (zw_ALU(8) AND (NOT q_a_i(7)) AND (NOT zw_din(7))) OR - (zw_ALU(8) AND (q_a_i(7)) AND (zw_din(7))) OR - (NOT zw_ALU(8) AND (q_a_i(7)) AND (NOT zw_din(7))) OR - (zw_ALU(8) AND (q_a_i(7)) AND (NOT zw_din(7))); - when f_adc_dec => - zw_din <= d_i; - reg_F(6) <= (zw_ALU5(3) XOR q_a_i(7)) AND (NOT (q_a_i(7) XOR zw_din(7))); - reg_F(0) <= zw_ALU4(4); - zw_b8(8 downto 5) <= '0' & ((zw_ALU4(4))) & ((zw_ALU4(4))) & '0'; - zw_b10(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + - unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); - zw_b7(8 downto 5) <= '0' & ((zw_ALU3(4))) & ((zw_ALU3(4))) & '0'; - zw_b9(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + - unsigned ('0' & zw_din(3 downto 0)) + reg_F(0); - when f_adc_dec1 => - reg_F(7) <= zw_ALU(7); - reg_F(1) <= NOT (zw_ALU(7) OR zw_ALU(6) OR zw_ALU(5) OR - zw_ALU(4) OR zw_ALU(3) OR zw_ALU(2) OR zw_ALU(1) OR - zw_ALU(0)); - when f_sbc_dec => - zw_din <= d_i; - reg_F(6) <= (zw_ALU2(3) XOR q_a_i(7)) AND (q_a_i(7) XOR zw_din(7)); - reg_F(0) <= (zw_ALU2(4)); - zw_b9(7 downto 0) <= '0' & - (NOT zw_ALU2(4)) & - (NOT zw_ALU2(4)) & - '0' & - '0' & - (NOT zw_ALU1(4)) & - (NOT zw_ALU1(4)) & - '0'; - zw_b8(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + - unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); - zw_b7(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + - unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F(0); - when f_sbc_dec1 => - reg_F(7) <= zw_ALU(7); - reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR - (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR - (zw_ALU(0))); - when f_asla => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_l_c_out; - when f_lsra => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_r_c_out; - when f_rola => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_l_c_out; - when f_rora => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_r_c_out; - when f_tax => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_tsx => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_decr => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - when f_asl => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_l_c_out; - when f_lsr => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_r_c_out; - when f_rol => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_l_c_out; - when f_ror => - reg_F(7) <= n_detect_out; - reg_F(1) <= z_detect_out; - reg_F(0) <= shift_rot_r_c_out; - when f_trb => - reg_F(1) <= z_detect_out; - when f_tsb => - reg_F(1) <= z_detect_out; - when others => - null; - end case; - end if; - end process csm_functions_clocked_proc; - - ----------------------------------------------------------------- - csm_functions_nextstate_proc : process ( - adc_sbc_finished, - csm_functions_current_state, - irq_finished, - op_finished, - rdy_i, - reg_F, - rmb_started, - rst_finished, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - case csm_functions_current_state is - when f_idle => - if (op_finished = '1' and - (zw_REG_OP = X"29" or zw_REG_OP = X"25" or - zw_REG_OP = X"35" or zw_REG_OP = X"2D" or - zw_REG_OP = X"3D" or zw_REG_OP = X"39" or - zw_REG_OP = X"21" or zw_REG_OP = X"31" or - zw_REG_OP = X"32")) then - csm_functions_next_state <= f_and; - elsif (op_finished = '1' and - (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or - zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or - zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or - zw_REG_OP = X"CC" or zw_REG_OP = X"EC" or zw_REG_OP = X"D2")) then - csm_functions_next_state <= f_cmp; - elsif (op_finished = '1' and - (zw_REG_OP = X"49" or zw_REG_OP = X"45" or zw_REG_OP = X"55" or zw_REG_OP = X"4D" or - zw_REG_OP = X"5D" or zw_REG_OP = X"59" or zw_REG_OP = X"41" or zw_REG_OP = X"51" or - zw_REG_OP = X"52")) then - csm_functions_next_state <= f_eor; - elsif (op_finished = '1' and - (zw_REG_OP = X"09" or zw_REG_OP = X"05" or zw_REG_OP = X"15" or zw_REG_OP = X"0D" or - zw_REG_OP = X"1D" or zw_REG_OP = X"19" or zw_REG_OP = X"01" or zw_REG_OP = X"11" or - zw_REG_OP = X"12")) then - csm_functions_next_state <= f_ora; - elsif (op_finished = '1' and - (zw_REG_OP = X"A9" or zw_REG_OP = X"A5" or zw_REG_OP = X"B5" or zw_REG_OP = X"AD" or - zw_REG_OP = X"BD" or zw_REG_OP = X"B9" or zw_REG_OP = X"A1" or zw_REG_OP = X"B1" or - zw_REG_OP = X"B2" or - zw_REG_OP = X"A2" or zw_REG_OP = X"A6" or zw_REG_OP = X"B6" or zw_REG_OP = X"AE" or - zw_REG_OP = X"BE" or - zw_REG_OP = X"A0" or zw_REG_OP = X"A4" or zw_REG_OP = X"B4" or zw_REG_OP = X"AC" or - zw_REG_OP = X"BC" or - zw_REG_OP = X"68" or zw_REG_OP = X"FA" or zw_REG_OP = X"7A")) then - csm_functions_next_state <= f_lda; - elsif (op_finished = '1' and - zw_REG_OP = X"18") then - csm_functions_next_state <= f_clc; - elsif (op_finished = '1' and - zw_REG_OP = X"38") then - csm_functions_next_state <= f_sec; - elsif (op_finished = '1' and - zw_REG_OP = X"D8") then - csm_functions_next_state <= f_cld; - elsif (op_finished = '1' and - zw_REG_OP = X"F8") then - csm_functions_next_state <= f_sed; - elsif (op_finished = '1' and - zw_REG_OP = X"B8") then - csm_functions_next_state <= f_clv; - elsif (op_finished = '1' and - zw_REG_OP = X"58") then - csm_functions_next_state <= f_cli; - elsif (op_finished = '1' and - (zw_REG_OP = X"78")) then - csm_functions_next_state <= f_sei; - elsif (op_finished = '1' and - (zw_REG_OP = X"40" or - zw_REG_OP = X"28")) then - csm_functions_next_state <= f_rti; - elsif (irq_finished = '1') then - csm_functions_next_state <= f_irq; - elsif (rst_finished = '1') then - csm_functions_next_state <= f_res; - elsif (op_finished = '1' and - zw_REG_OP = X"89") then - csm_functions_next_state <= f_bit1; - elsif (op_finished = '1' and - (zw_REG_OP = X"24" or - zw_REG_OP = X"34" or - zw_REG_OP = X"2C" or - zw_REG_OP = X"3C")) then - csm_functions_next_state <= f_bit2; - elsif (op_finished = '1' and - (zw_REG_OP = X"3A" or - zw_REG_OP = X"CA" or - zw_REG_OP = X"88" or - zw_REG_OP = X"1A" or - zw_REG_OP = X"E8" or - zw_REG_OP = X"C8")) then - csm_functions_next_state <= f_de_in_a; - elsif (op_finished = '1' and - reg_F(3) = '0' and - (zw_REG_OP = X"69" or - zw_REG_OP = X"65" or - zw_REG_OP = X"75" or - zw_REG_OP = X"6D" or - zw_REG_OP = X"72" or - zw_REG_OP = X"7D" or - zw_REG_OP = X"79" or - zw_REG_OP = X"71" or - zw_REG_OP = X"61")) then - csm_functions_next_state <= f_adc_bin; - elsif (op_finished = '1' and - reg_F(3) = '0' and - (zw_REG_OP = X"E9" or - zw_REG_OP = X"E5" or - zw_REG_OP = X"F5" or - zw_REG_OP = X"ED" or - zw_REG_OP = X"F2" or - zw_REG_OP = X"FD" or - zw_REG_OP = X"F9" or - zw_REG_OP = X"F1" or - zw_REG_OP = X"E1")) then - csm_functions_next_state <= f_sbc_bin; - elsif (op_finished = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"69" or zw_REG_OP = X"65" or zw_REG_OP = X"75" or - zw_REG_OP = X"6D" or zw_REG_OP = X"72" or zw_REG_OP = X"7D" or - zw_REG_OP = X"79" or zw_REG_OP = X"71" or zw_REG_OP = X"61")) then - csm_functions_next_state <= f_adc_dec; - elsif (op_finished = '1' and - reg_F(3) = '1' and - (zw_REG_OP = X"E9" or zw_REG_OP = X"E5" or zw_REG_OP = X"F5" or - zw_REG_OP = X"ED" or zw_REG_OP = X"F2" or zw_REG_OP = X"FD" or - zw_REG_OP = X"F9" or zw_REG_OP = X"F1" or zw_REG_OP = X"E1")) then - csm_functions_next_state <= f_sbc_dec; - elsif (op_finished = '1' and - zw_REG_OP = X"0A") then - csm_functions_next_state <= f_asla; - elsif (op_finished = '1' and - zw_REG_OP = X"4A") then - csm_functions_next_state <= f_lsra; - elsif (op_finished = '1' and - zw_REG_OP = X"2A") then - csm_functions_next_state <= f_rola; - elsif (op_finished = '1' and - zw_REG_OP = X"6A") then - csm_functions_next_state <= f_rora; - elsif (op_finished = '1' and - (zw_REG_OP = X"AA" or zw_REG_OP = X"8A" or - zw_REG_OP = X"A8" or zw_REG_OP = X"98")) then - csm_functions_next_state <= f_tax; - elsif (op_finished = '1' and - zw_REG_OP = X"BA") then - csm_functions_next_state <= f_tsx; - elsif (op_finished = '1' and - (zw_REG_OP = X"C6" or zw_REG_OP = X"E6" or - zw_REG_OP = X"D6" or zw_REG_OP = X"F6" or - zw_REG_OP = X"CE" or zw_REG_OP = X"EE" or - zw_REG_OP = X"DE" or zw_REG_OP = X"FE")) then - csm_functions_next_state <= f_decr; - elsif (rmb_started = '1' and - (zw_REG_OP = X"66" or - zw_REG_OP = X"76" or - zw_REG_OP = X"6E" or - zw_REG_OP = X"7E")) then - csm_functions_next_state <= f_ror; - elsif (rmb_started = '1' and - (zw_REG_OP = X"06" or - zw_REG_OP = X"16" or - zw_REG_OP = X"0E" or - zw_REG_OP = X"1E")) then - csm_functions_next_state <= f_asl; - elsif (rmb_started = '1' and - (zw_REG_OP = X"46" or - zw_REG_OP = X"56" or - zw_REG_OP = X"4E" or - zw_REG_OP = X"5E")) then - csm_functions_next_state <= f_lsr; - elsif (rmb_started = '1' and - (zw_REG_OP = X"26" or - zw_REG_OP = X"36" or - zw_REG_OP = X"2E" or - zw_REG_OP = X"3E")) then - csm_functions_next_state <= f_rol; - elsif (rmb_started = '1' and - zw_REG_OP (7) = '0' and - zw_REG_OP (3 downto 0) = X"7") then - csm_functions_next_state <= f_rmb; - elsif (rmb_started = '1' and - zw_REG_OP (7) = '1' and - zw_REG_OP (3 downto 0) = X"7") then - csm_functions_next_state <= f_smb; - elsif (rmb_started = '1' and - (zw_REG_OP = X"14" or - zw_REG_OP = X"1C")) then - csm_functions_next_state <= f_trb; - elsif (rmb_started = '1' and - (zw_REG_OP = X"04" or - zw_REG_OP = X"0C")) then - csm_functions_next_state <= f_tsb; - else - csm_functions_next_state <= f_idle; - end if; - when f_and => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_and; - end if; - when f_lda => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_lda; - end if; - when f_rst => - csm_functions_next_state <= f_idle; - when f_eor => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_eor; - end if; - when f_cmp => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_cmp; - end if; - when f_ora => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_ora; - end if; - when f_clc => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_clc; - end if; - when f_sec => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_sec; - end if; - when f_cld => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_cld; - end if; - when f_sed => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_sed; - end if; - when f_clv => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_clv; - end if; - when f_cli => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_cli; - end if; - when f_sei => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_sei; - end if; - when f_rti => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_rti; - end if; - when f_irq => - if (irq_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_irq; - end if; - when f_res => - if (rst_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_res; - end if; - when f_bit1 => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_bit1; - end if; - when f_bit2 => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_bit2; - end if; - when f_de_in_a => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_de_in_a; - end if; - when f_adc_bin => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_adc_bin; - end if; - when f_sbc_bin => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_sbc_bin; - end if; - when f_adc_dec => - if (rdy_i = '1') then - csm_functions_next_state <= f_adc_dec1; - else - csm_functions_next_state <= f_adc_dec; - end if; - when f_adc_dec1 => - if (adc_sbc_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_adc_dec1; - end if; - when f_sbc_dec => - if (rdy_i = '1') then - csm_functions_next_state <= f_sbc_dec1; - else - csm_functions_next_state <= f_sbc_dec; - end if; - when f_sbc_dec1 => - if (adc_sbc_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_sbc_dec1; - end if; - when f_asla => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_asla; - end if; - when f_lsra => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_lsra; - end if; - when f_rola => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_rola; - end if; - when f_rora => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_rora; - end if; - when f_tax => - if (rdy_i = '1') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_tax; - end if; - when f_tsx => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_tsx; - end if; - when f_decr => - if (op_finished = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_decr; - end if; - when f_asl => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_asl; - end if; - when f_lsr => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_lsr; - end if; - when f_rol => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_rol; - end if; - when f_ror => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_ror; - end if; - when f_rmb => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_rmb; - end if; - when f_smb => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_smb; - end if; - when f_trb => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_trb; - end if; - when f_tsb => - if (rmb_started = '0') then - csm_functions_next_state <= f_idle; - else - csm_functions_next_state <= f_tsb; - end if; - when others => - csm_functions_next_state <= f_rst; - end case; - end process csm_functions_nextstate_proc; - - ----------------------------------------------------------------- - csm_functions_output_proc : process ( - adr_sp_i, - cnz_detect_in, - csm_functions_current_state, - d_alu_prio_i, - d_regs_out_i, - q_a_i, - reg_F, - shift_rot_asl_out, - shift_rot_in, - shift_rot_lsr_out, - shift_rot_rol_out, - shift_rot_ror_out, - zw_ALU, - zw_ALU1, - zw_ALU3, - zw_ALU5, - zw_b10, - zw_b11, - zw_b2, - zw_b4, - zw_b7, - zw_b8, - zw_b9, - zw_din - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - d_regs_in_o <= X"00"; - load_regs_o <= '0'; - -- Default Assignment To Internals - c_detect_out <= cnz_detect_in(8); - cnz_detect_in <= '0' & X"00"; - n_detect_out <= cnz_detect_in(7); - shift_rot_asl_out <= shift_rot_in (6 downto 0) & '0'; - shift_rot_in <= X"00"; - shift_rot_l_c_out <= shift_rot_in (7); - shift_rot_lsr_out <= '0' & shift_rot_in (7 downto 1); - shift_rot_r_c_out <= shift_rot_in (0); - shift_rot_rol_out <= shift_rot_in (6 downto 0) & reg_F(0); - shift_rot_ror_out <= reg_F(0) & shift_rot_in (7 downto 1); - z_detect_out <= NOT(cnz_detect_in(7) OR cnz_detect_in(6) OR cnz_detect_in(5) OR cnz_detect_in(4) OR cnz_detect_in(3) OR cnz_detect_in(2) OR cnz_detect_in(1) OR cnz_detect_in(0)); - zw_ALU <= "00" & X"00"; - zw_ALU1 <= "00" & X"00"; - zw_ALU2 <= "00" & X"00"; - zw_ALU3 <= "00" & X"00"; - zw_ALU4 <= "00" & X"00"; - zw_ALU5 <= "00" & X"00"; - zw_ALU6 <= "00" & X"00"; - zw_b13 <= X"00"; - - -- Combined Actions - case csm_functions_current_state is - when f_and => - d_regs_in_o <= zw_din AND q_a_i; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (zw_din AND q_a_i); - when f_lda => - d_regs_in_o <= zw_din; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (zw_din); - when f_rst => - d_regs_in_o <= X"00"; - load_regs_o <= '0'; - when f_eor => - d_regs_in_o <= zw_din XOR q_a_i; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (zw_din XOR q_a_i); - when f_cmp => - cnz_detect_in <= unsigned ('0' & d_regs_out_i) + - unsigned ('0' & NOT (zw_din)) + 1; - when f_ora => - d_regs_in_o <= zw_din OR q_a_i; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (zw_din OR q_a_i); - when f_bit1 => - cnz_detect_in <= '0' & (zw_din AND q_a_i); - when f_bit2 => - cnz_detect_in <= '0' & (zw_din AND q_a_i); - when f_de_in_a => - d_regs_in_o <= unsigned(d_regs_out_i) + unsigned(zw_b4); - load_regs_o <= '1'; - cnz_detect_in <= '0' & (unsigned(d_regs_out_i) + unsigned(zw_b4)); - when f_adc_bin => - d_regs_in_o <= zw_ALU(7 downto 0); - load_regs_o <= '1'; - zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & zw_din) + reg_F(0); - when f_sbc_bin => - d_regs_in_o <= zw_ALU(7 downto 0); - load_regs_o <= '1'; - zw_ALU(8 downto 0) <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (zw_din)) + reg_F(0); - when f_adc_dec => - zw_ALU4(4) <= zw_ALU5(4) OR - (zw_ALU5(3) AND zw_ALU5(2)) OR - (zw_ALU5(3) AND zw_ALU5(1)); - zw_ALU5(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + - unsigned ('0' & zw_din(7 downto 4)) + (zw_ALU3(4)); - zw_ALU3(4) <= zw_ALU1(4) OR - (zw_ALU1(3) AND zw_ALU1(2)) OR - (zw_ALU1(3) AND zw_ALU1(1)); - zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + - unsigned ('0' & zw_din(3 downto 0)) + reg_F(0); - when f_adc_dec1 => - d_regs_in_o <= zw_ALU(7 downto 0); - load_regs_o <= '1'; - zw_ALU(7 downto 4) <= unsigned (zw_b10(3 downto 0)) + unsigned (zw_b8(8 downto 5)); - zw_ALU(3 downto 0) <= unsigned (zw_b9(3 downto 0)) + unsigned (zw_b7(8 downto 5)); - when f_sbc_dec => - zw_ALU2(5 downto 0) <= unsigned ("00" & q_a_i(7 downto 4)) + - unsigned ("00" & NOT (zw_din(7 downto 4))) + (zw_ALU1(4)); - zw_ALU1(5 downto 0) <= unsigned ("00" & q_a_i(3 downto 0)) + - unsigned ("00" & NOT (zw_din(3 downto 0))) + reg_F(0); - when f_sbc_dec1 => - d_regs_in_o <= zw_ALU(7 downto 0); - load_regs_o <= '1'; - zw_ALU(7 downto 0) <= unsigned (( zw_b8(3 downto 0)) & ( zw_b7(3 downto 0))) - - unsigned (zw_b9(7 downto 0)); - when f_asla => - shift_rot_in <= q_a_i; - d_regs_in_o <= shift_rot_asl_out; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (shift_rot_asl_out); - when f_lsra => - shift_rot_in <= q_a_i; - d_regs_in_o <= shift_rot_lsr_out; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (shift_rot_lsr_out); - when f_rola => - shift_rot_in <= q_a_i; - d_regs_in_o <= shift_rot_rol_out; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (shift_rot_rol_out); - when f_rora => - shift_rot_in <= q_a_i; - d_regs_in_o <= shift_rot_ror_out; - load_regs_o <= '1'; - cnz_detect_in <= '0' & (shift_rot_ror_out); - when f_tax => - load_regs_o <= '1'; - cnz_detect_in <= '0' & (d_regs_out_i); - when f_tsx => - d_regs_in_o <= adr_sp_i (7 downto 0); - load_regs_o <= '1'; - cnz_detect_in <= '0' & (adr_sp_i (7 downto 0)); - when f_decr => - cnz_detect_in <= '0' & (zw_b11); - when f_asl => - shift_rot_in <= zw_b2; - zw_b13 <= shift_rot_asl_out; - cnz_detect_in <= '0' & (shift_rot_asl_out); - when f_lsr => - shift_rot_in <= zw_b2; - zw_b13 <= shift_rot_lsr_out; - cnz_detect_in <= '0' & (shift_rot_lsr_out); - when f_rol => - shift_rot_in <= zw_b2; - zw_b13 <= shift_rot_rol_out; - cnz_detect_in <= '0' & (shift_rot_rol_out); - when f_ror => - shift_rot_in <= zw_b2; - zw_b13 <= shift_rot_ror_out; - cnz_detect_in <= '0' & (shift_rot_ror_out); - when f_rmb => - zw_b13 <= zw_b2 and NOT (d_alu_prio_i); - when f_smb => - zw_b13 <= zw_b2 or d_alu_prio_i; - when f_trb => - zw_b13 <= zw_b2 and NOT (q_a_i); - cnz_detect_in <= '0' & (zw_b2 and q_a_i); - when f_tsb => - zw_b13 <= zw_b2 or q_a_i; - cnz_detect_in <= '0' & (zw_b2 and q_a_i); - when others => - null; - end case; - end process csm_functions_output_proc; - - ----------------------------------------------------------------- - csm_rb_out_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_rb_out_current_state <= rb_out_idle; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_rb_out_current_state <= csm_rb_out_next_state; - end if; - end process csm_rb_out_clocked_proc; - - ----------------------------------------------------------------- - csm_rb_out_nextstate_proc : process ( - csm_rb_out_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - case csm_rb_out_current_state is - when rb_out_idle => - if (op_fetch = '0' and - (zw_REG_OP = X"8A" or - zw_REG_OP = X"9A" or - zw_REG_OP = X"BA" or - zw_REG_OP = X"86" or - zw_REG_OP = X"96" or - zw_REG_OP = X"8E" or - zw_REG_OP = X"E8" or - zw_REG_OP = X"CA" or - zw_REG_OP = X"DA" or - zw_REG_OP = X"E0" or - zw_REG_OP = X"E4" or - zw_REG_OP = X"EC")) then - csm_rb_out_next_state <= rb_out_01; - elsif (op_fetch = '0' and - (zw_REG_OP = X"5A" or - zw_REG_OP = X"98" or - zw_REG_OP = X"84" or - zw_REG_OP = X"88" or - zw_REG_OP = X"94" or - zw_REG_OP = X"8C" or - zw_REG_OP = X"C8" or - zw_REG_OP = X"C0" or - zw_REG_OP = X"C4" or - zw_REG_OP = X"CC")) then - csm_rb_out_next_state <= rb_out_10; - elsif (op_fetch = '0' and - (zw_REG_OP = X"9C" or - zw_REG_OP = X"9E" or - zw_REG_OP = X"64" or - zw_REG_OP = X"74")) then - csm_rb_out_next_state <= rb_out_11; - else - csm_rb_out_next_state <= rb_out_idle; - end if; - when rb_out_01 => - if (op_fetch = '1') then - csm_rb_out_next_state <= rb_out_idle; - else - csm_rb_out_next_state <= rb_out_01; - end if; - when rb_out_10 => - if (op_fetch = '1') then - csm_rb_out_next_state <= rb_out_idle; - else - csm_rb_out_next_state <= rb_out_10; - end if; - when rb_out_11 => - if (op_fetch = '1') then - csm_rb_out_next_state <= rb_out_idle; - else - csm_rb_out_next_state <= rb_out_11; - end if; - when others => - csm_rb_out_next_state <= rb_out_idle; - end case; - end process csm_rb_out_nextstate_proc; - - ----------------------------------------------------------------- - csm_rb_out_output_proc : process ( - csm_rb_out_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - sel_rb_out_o <= "00"; - - -- Combined Actions - case csm_rb_out_current_state is - when rb_out_idle => - sel_rb_out_o <= "00"; - if (op_fetch = '0' and - (zw_REG_OP = X"8A" or - zw_REG_OP = X"9A" or - zw_REG_OP = X"BA" or - zw_REG_OP = X"86" or - zw_REG_OP = X"96" or - zw_REG_OP = X"8E" or - zw_REG_OP = X"E8" or - zw_REG_OP = X"CA" or - zw_REG_OP = X"DA" or - zw_REG_OP = X"E0" or - zw_REG_OP = X"E4" or - zw_REG_OP = X"EC")) then - sel_rb_out_o <= "01"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"5A" or - zw_REG_OP = X"98" or - zw_REG_OP = X"84" or - zw_REG_OP = X"88" or - zw_REG_OP = X"94" or - zw_REG_OP = X"8C" or - zw_REG_OP = X"C8" or - zw_REG_OP = X"C0" or - zw_REG_OP = X"C4" or - zw_REG_OP = X"CC")) then - sel_rb_out_o <= "10"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"9C" or - zw_REG_OP = X"9E" or - zw_REG_OP = X"64" or - zw_REG_OP = X"74")) then - sel_rb_out_o <= "11"; - end if; - when rb_out_01 => - sel_rb_out_o <= "01"; - when rb_out_10 => - sel_rb_out_o <= "10"; - when rb_out_11 => - sel_rb_out_o <= "11"; - when others => - null; - end case; - end process csm_rb_out_output_proc; - - ----------------------------------------------------------------- - csm_reg_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_reg_current_state <= reg_idle; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_reg_current_state <= csm_reg_next_state; - end if; - end process csm_reg_clocked_proc; - - ----------------------------------------------------------------- - csm_reg_nextstate_proc : process ( - csm_reg_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - case csm_reg_current_state is - when reg_idle => - if (op_fetch = '0' and - (zw_REG_OP = X"FA" or - zw_REG_OP = X"BA" or - zw_REG_OP = X"AA" or - zw_REG_OP = X"A2" or - zw_REG_OP = X"A6" or - zw_REG_OP = X"B6" or - zw_REG_OP = X"AE" or - zw_REG_OP = X"BE" or - zw_REG_OP = X"E8" or - zw_REG_OP = X"CA")) then - csm_reg_next_state <= reg_01; - elsif (op_fetch = '0' and - (zw_REG_OP = X"A8" or - zw_REG_OP = X"7A" or - zw_REG_OP = X"A0" or - zw_REG_OP = X"A4" or - zw_REG_OP = X"B4" or - zw_REG_OP = X"AC" or - zw_REG_OP = X"BC" or - zw_REG_OP = X"C8" or - zw_REG_OP = X"88")) then - csm_reg_next_state <= reg_10; - elsif (op_fetch = '0' and - (zw_REG_OP = X"9A")) then - csm_reg_next_state <= reg_11; - else - csm_reg_next_state <= reg_idle; - end if; - when reg_10 => - if (op_fetch = '1') then - csm_reg_next_state <= reg_idle; - else - csm_reg_next_state <= reg_10; - end if; - when reg_11 => - if (op_fetch = '1') then - csm_reg_next_state <= reg_idle; - else - csm_reg_next_state <= reg_11; - end if; - when reg_01 => - if (op_fetch = '1') then - csm_reg_next_state <= reg_idle; - else - csm_reg_next_state <= reg_01; - end if; - when others => - csm_reg_next_state <= reg_idle; - end case; - end process csm_reg_nextstate_proc; - - ----------------------------------------------------------------- - csm_reg_output_proc : process ( - csm_reg_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - sel_reg_o <= "00"; - - -- Combined Actions - case csm_reg_current_state is - when reg_idle => - sel_reg_o<= "00"; - if (op_fetch = '0' and - (zw_REG_OP = X"FA" or - zw_REG_OP = X"BA" or - zw_REG_OP = X"AA" or - zw_REG_OP = X"A2" or - zw_REG_OP = X"A6" or - zw_REG_OP = X"B6" or - zw_REG_OP = X"AE" or - zw_REG_OP = X"BE" or - zw_REG_OP = X"E8" or - zw_REG_OP = X"CA")) then - sel_reg_o <= "01"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"A8" or - zw_REG_OP = X"7A" or - zw_REG_OP = X"A0" or - zw_REG_OP = X"A4" or - zw_REG_OP = X"B4" or - zw_REG_OP = X"AC" or - zw_REG_OP = X"BC" or - zw_REG_OP = X"C8" or - zw_REG_OP = X"88")) then - sel_reg_o <= "10"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"9A")) then - sel_reg_o <= "11"; - end if; - when reg_10 => - sel_reg_o <= "10"; - when reg_11 => - sel_reg_o <= "11"; - when reg_01 => - sel_reg_o <= "01"; - when others => - null; - end case; - end process csm_reg_output_proc; - - ----------------------------------------------------------------- - csm_rb_in_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_rb_in_current_state <= rb_in_idle; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_rb_in_current_state <= csm_rb_in_next_state; - end if; - end process csm_rb_in_clocked_proc; - - ----------------------------------------------------------------- - csm_rb_in_nextstate_proc : process ( - csm_rb_in_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - case csm_rb_in_current_state is - when rb_in_idle => - if (op_fetch = '0' and - (zw_REG_OP = X"A8" or - zw_REG_OP = X"AA")) then - csm_rb_in_next_state <= rb_in_00; - elsif (op_fetch = '0' and - (zw_REG_OP = X"98")) then - csm_rb_in_next_state <= rb_in_01; - elsif (op_fetch = '0' and - (zw_REG_OP = X"8A")) then - csm_rb_in_next_state <= rb_in_10; - else - csm_rb_in_next_state <= rb_in_idle; - end if; - when rb_in_01 => - if (op_fetch = '1') then - csm_rb_in_next_state <= rb_in_idle; - else - csm_rb_in_next_state <= rb_in_01; - end if; - when rb_in_10 => - if (op_fetch = '1') then - csm_rb_in_next_state <= rb_in_idle; - else - csm_rb_in_next_state <= rb_in_10; - end if; - when rb_in_00 => - if (op_fetch = '1') then - csm_rb_in_next_state <= rb_in_idle; - else - csm_rb_in_next_state <= rb_in_00; - end if; - when others => - csm_rb_in_next_state <= rb_in_idle; - end case; - end process csm_rb_in_nextstate_proc; - - ----------------------------------------------------------------- - csm_rb_in_output_proc : process ( - csm_rb_in_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - -- Default Assignment - sel_rb_in_o <= "00"; - - -- Combined Actions - case csm_rb_in_current_state is - when rb_in_idle => - sel_rb_in_o <= "11"; - if (op_fetch = '0' and - (zw_REG_OP = X"A8" or - zw_REG_OP = X"AA")) then - sel_rb_in_o <= "00"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"98")) then - sel_rb_in_o <= "01"; - elsif (op_fetch = '0' and - (zw_REG_OP = X"8A")) then - sel_rb_in_o <= "10"; - end if; - when rb_in_01 => - sel_rb_in_o <= "01"; - when rb_in_10 => - sel_rb_in_o <= "10"; - when rb_in_00 => - sel_rb_in_o <= "00"; - when others => - null; - end case; - end process csm_rb_in_output_proc; - - ----------------------------------------------------------------- - csm_add_value_clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - csm_add_value_current_state <= add_val_idle; - elsif (clk_clk_i'event and clk_clk_i = '1') then - csm_add_value_current_state <= csm_add_value_next_state; - end if; - end process csm_add_value_clocked_proc; - - ----------------------------------------------------------------- - csm_add_value_nextstate_proc : process ( - csm_add_value_current_state, - op_fetch, - zw_REG_OP - ) - ----------------------------------------------------------------- - begin - case csm_add_value_current_state is - when add_val_idle => - if (op_fetch = '0' and - (zw_REG_OP = X"C6" or - zw_REG_OP = X"D6" or - zw_REG_OP = X"CE" or - zw_REG_OP = X"DE" or - zw_REG_OP = X"CA" or - zw_REG_OP = X"88" or - zw_REG_OP = X"3A")) then - csm_add_value_next_state <= add_val; - else - csm_add_value_next_state <= add_val_idle; - end if; - when add_val => - if (op_fetch = '1') then - csm_add_value_next_state <= add_val_idle; - else - csm_add_value_next_state <= add_val; - end if; - when others => - csm_add_value_next_state <= add_val_idle; - end case; - end process csm_add_value_nextstate_proc; - - ----------------------------------------------------------------- - csm_add_value_output_proc : process ( - csm_add_value_current_state - ) - ----------------------------------------------------------------- - begin - -- Default Assignment To Internals - zw_b4 <= X"00"; - - -- Combined Actions - case csm_add_value_current_state is - when add_val_idle => - zw_b4 <= X"01"; - when add_val => - zw_b4 <= X"FF"; - when others => - null; - end case; - end process csm_add_value_output_proc; - - -- Concurrent Statements - -- Clocked output assignments - sync_o <= sync_o_cld; -end fsm; Index: rtl/vhdl/reg_pc.vhd =================================================================== --- rtl/vhdl/reg_pc.vhd (revision 23) +++ rtl/vhdl/reg_pc.vhd (nonexistent) @@ -1,237 +0,0 @@ --- VHDL Entity r65c02_tc.reg_pc.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:59:59 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity reg_pc is - port( - adr_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic; - ld_i : in std_logic_vector (1 downto 0); - ld_pc_i : in std_logic; - offset_i : in std_logic_vector (15 downto 0); - rst_rst_n_i : in std_logic; - sel_pc_in_i : in std_logic; - sel_pc_val_i : in std_logic_vector (1 downto 0); - adr_nxt_pc_o : out std_logic_vector (15 downto 0); - adr_pc_o : out std_logic_vector (15 downto 0) - ); - --- Declarations - -end reg_pc ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.reg_pc.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:59:59 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of reg_pc is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_pc_high_o_i : std_logic_vector(7 downto 0); - signal adr_pc_low_o_i : std_logic_vector(7 downto 0); - signal adr_pc_o_i : std_logic_vector(15 downto 0); - signal ci_o_i : std_logic; - signal cout_pc_o_i : std_logic; - signal load3_o_i : std_logic; - signal load_o_i : std_logic; - signal offset_high_o_i : std_logic_vector(7 downto 0); - signal offset_low_o_i : std_logic_vector(7 downto 0); - signal val_o_i : std_logic_vector(7 downto 0); - signal val_one : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0); - signal adr_pc_o_internal : std_logic_vector (15 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split' - signal mw_U_3temp_din : std_logic_vector(15 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split' - signal mw_U_5temp_din : std_logic_vector(15 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_2' of 'add' - u_2combo_proc: process (adr_pc_low_o_i, val_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_pc_low_o_i; - temp_din1 := '0' & val_o_i; - temp_carry := '0'; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8); - cout_pc_o_i <= temp_sum(8) ; - end process u_2combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_11' of 'add' - u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_pc_high_o_i; - temp_din1 := '0' & offset_high_o_i; - temp_carry := ci_o_i; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8); - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0); - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' - adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load3_o_i = '1') then - mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8); - end if; - end if; - end process u_4seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= ld_pc_i and ld_i(0); - - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load3_o_i <= ld_pc_i and ld_i(1); - - -- ModuleWare code(v1.12) for instance 'U_10' of 'and' - ci_o_i <= cout_pc_o_i and ld_pc_i; - - -- ModuleWare code(v1.12) for instance 'U_1' of 'constval' - val_zero <= "00000000"; - - -- ModuleWare code(v1.12) for instance 'U_9' of 'constval' - val_one <= "00000001"; - - -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' - u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i) - begin - case sel_pc_in_i is - when '0' => adr_pc_o_i <= adr_pc_o_internal; - when '1' => adr_pc_o_i <= adr_i; - when others => adr_pc_o_i <= (others => 'X'); - end case; - end process u_8combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_13' of 'mux' - u_13combo_proc: process(val_one, val_zero, offset_low_o_i, - sel_pc_val_i) - begin - case sel_pc_val_i is - when "00" => val_o_i <= val_one; - when "01" => val_o_i <= val_zero; - when "10" => val_o_i <= offset_low_o_i; - when "11" => val_o_i <= val_zero; - when others => val_o_i <= (others => 'X'); - end case; - end process u_13combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'split' - mw_U_3temp_din <= adr_pc_o_i; - u_3combo_proc: process (mw_U_3temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_3temp_din(15 downto 0); - adr_pc_low_o_i <= temp_din(7 downto 0); - adr_pc_high_o_i <= temp_din(15 downto 8); - end process u_3combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_5' of 'split' - mw_U_5temp_din <= offset_i; - u_5combo_proc: process (mw_U_5temp_din) - variable temp_din: std_logic_vector(15 downto 0); - begin - temp_din := mw_U_5temp_din(15 downto 0); - offset_low_o_i <= temp_din(7 downto 0); - offset_high_o_i <= temp_din(15 downto 8); - end process u_5combo_proc; - - -- Instance port mappings. - - -- Implicit buffered output assignments - adr_nxt_pc_o <= adr_nxt_pc_o_internal; - adr_pc_o <= adr_pc_o_internal; - -end struct; Index: rtl/vhdl/regbank_axy.vhd =================================================================== --- rtl/vhdl/regbank_axy.vhd (revision 23) +++ rtl/vhdl/regbank_axy.vhd (nonexistent) @@ -1,207 +0,0 @@ --- VHDL Entity r65c02_tc.regbank_axy.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 20:45:48 27.08.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity regbank_axy is - port( - clk_clk_i : in std_logic; - d_regs_in_i : in std_logic_vector (7 downto 0); - load_regs_i : in std_logic; - rst_rst_n_i : in std_logic; - sel_rb_in_i : in std_logic_vector (1 downto 0); - sel_rb_out_i : in std_logic_vector (1 downto 0); - sel_reg_i : in std_logic_vector (1 downto 0); - d_regs_out_o : out std_logic_vector (7 downto 0); - q_a_o : out std_logic_vector (7 downto 0); - q_x_o : out std_logic_vector (7 downto 0); - q_y_o : out std_logic_vector (7 downto 0) - ); - --- Declarations - -end regbank_axy ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.regbank_axy.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:48 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of regbank_axy is - - -- Architecture declarations - - -- Internal signal declarations - signal ld : std_logic_vector(2 downto 0); - signal load1_o_i : std_logic; - signal load2_o_i : std_logic; - signal load_o_i : std_logic; - signal q_mux_o_i : std_logic_vector(7 downto 0); - signal val_zero : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal q_a_o_internal : std_logic_vector (7 downto 0); - signal q_x_o_internal : std_logic_vector (7 downto 0); - signal q_y_o_internal : std_logic_vector (7 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff' - signal mw_U_4reg_cval : std_logic_vector(7 downto 0); - - -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'adff' - signal mw_U_5reg_cval : std_logic_vector(7 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - q_a_o_internal <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= q_mux_o_i; - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'adff' - q_x_o_internal <= mw_U_4reg_cval; - u_4seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_4reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load1_o_i = '1') then - mw_U_4reg_cval <= q_mux_o_i; - end if; - end if; - end process u_4seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_5' of 'adff' - q_y_o_internal <= mw_U_5reg_cval; - u_5seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_5reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load2_o_i = '1') then - mw_U_5reg_cval <= q_mux_o_i; - end if; - end if; - end process u_5seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= load_regs_i and ld(0); - - -- ModuleWare code(v1.12) for instance 'U_7' of 'and' - load1_o_i <= load_regs_i and ld(1); - - -- ModuleWare code(v1.12) for instance 'U_8' of 'and' - load2_o_i <= load_regs_i and ld(2); - - -- ModuleWare code(v1.12) for instance 'U_11' of 'constval' - val_zero <= "00000000"; - - -- ModuleWare code(v1.12) for instance 'U_1' of 'decoder1' - u_1combo_proc: process (sel_reg_i) - begin - ld <= (others => '0'); - case sel_reg_i is - when "00" => ld(0) <= '1'; - when "01" => ld(1) <= '1'; - when "10" => ld(2) <= '1'; - when others => ld <= (others => '0'); - end case; - end process u_1combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_2' of 'mux' - u_2combo_proc: process(q_a_o_internal, q_x_o_internal, q_y_o_internal, - val_zero, sel_rb_out_i) - begin - case sel_rb_out_i is - when "00" => d_regs_out_o <= q_a_o_internal; - when "01" => d_regs_out_o <= q_x_o_internal; - when "10" => d_regs_out_o <= q_y_o_internal; - when "11" => d_regs_out_o <= val_zero; - when others => d_regs_out_o <= (others => 'X'); - end case; - end process u_2combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'mux' - u_3combo_proc: process(q_a_o_internal, q_y_o_internal, q_x_o_internal, - d_regs_in_i, sel_rb_in_i) - begin - case sel_rb_in_i is - when "00" => q_mux_o_i <= q_a_o_internal; - when "01" => q_mux_o_i <= q_y_o_internal; - when "10" => q_mux_o_i <= q_x_o_internal; - when "11" => q_mux_o_i <= d_regs_in_i; - when others => q_mux_o_i <= (others => 'X'); - end case; - end process u_3combo_proc; - - -- Instance port mappings. - - -- Implicit buffered output assignments - q_a_o <= q_a_o_internal; - q_x_o <= q_x_o_internal; - q_y_o <= q_y_o_internal; - -end struct; Index: rtl/vhdl/reg_sp.vhd =================================================================== --- rtl/vhdl/reg_sp.vhd (revision 23) +++ rtl/vhdl/reg_sp.vhd (nonexistent) @@ -1,161 +0,0 @@ --- VHDL Entity r65c02_tc.reg_sp.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:08 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity reg_sp is - port( - adr_low_i : in std_logic_vector (7 downto 0); - clk_clk_i : in std_logic; - ld_low_i : in std_logic; - ld_sp_i : in std_logic; - rst_rst_n_i : in std_logic; - sel_sp_as_i : in std_logic; - sel_sp_in_i : in std_logic; - adr_sp_o : out std_logic_vector (15 downto 0) - ); - --- Declarations - -end reg_sp ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.reg_sp.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:04:08 06.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - - -architecture struct of reg_sp is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_sp_low_o_i : std_logic_vector(7 downto 0); - signal load_o_i : std_logic; - signal result_low1_o_i : std_logic_vector(7 downto 0); - signal result_low_o_i : std_logic_vector(7 downto 0); - signal sp_as_n_o_i : std_logic; - signal val_one : std_logic_vector(7 downto 0); - - -- Implicit buffer signal declarations - signal adr_sp_o_internal : std_logic_vector (15 downto 0); - - - -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff' - signal mw_U_0reg_cval : std_logic_vector(7 downto 0); - - -begin - - -- ModuleWare code(v1.12) for instance 'U_11' of 'addsub' - u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & adr_sp_low_o_i; - temp_din1 := '0' & val_one; - temp_carry := '0'; - if (sp_as_n_o_i = '1') then - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - else - temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry; - end if; - result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_0' of 'adff' - adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval; - u_0seq_proc: process (clk_clk_i, rst_rst_n_i) - begin - if (rst_rst_n_i = '0') then - mw_U_0reg_cval <= "00000000"; - elsif (clk_clk_i'event and clk_clk_i='1') then - if (load_o_i = '1') then - mw_U_0reg_cval <= result_low1_o_i; - end if; - end if; - end process u_0seq_proc; - - -- ModuleWare code(v1.12) for instance 'U_6' of 'and' - load_o_i <= ld_sp_i and ld_low_i; - - -- ModuleWare code(v1.12) for instance 'U_3' of 'buff' - adr_sp_o_internal(15 DOWNTO 8) <= val_one; - - -- ModuleWare code(v1.12) for instance 'U_4' of 'constval' - val_one <= "00000001"; - - -- ModuleWare code(v1.12) for instance 'U_2' of 'inv' - sp_as_n_o_i <= not(sel_sp_as_i); - - -- ModuleWare code(v1.12) for instance 'U_8' of 'mux' - u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i) - begin - case sel_sp_in_i is - when '0' => result_low1_o_i <= result_low_o_i; - when '1' => result_low1_o_i <= adr_low_i; - when others => result_low1_o_i <= (others => 'X'); - end case; - end process u_8combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_10' of 'tap' - adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0); - - -- Instance port mappings. - - -- Implicit buffered output assignments - adr_sp_o <= adr_sp_o_internal; - -end struct; Index: rtl/vhdl/r65c02_tc.vhd =================================================================== --- rtl/vhdl/r65c02_tc.vhd (revision 23) +++ rtl/vhdl/r65c02_tc.vhd (nonexistent) @@ -1,177 +0,0 @@ --- VHDL Entity r65c02_tc.r65c02_tc.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 15:49:08 04.10.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity r65c02_tc is - port( - clk_clk_i : in std_logic; - d_i : in std_logic_vector (7 downto 0); - irq_n_i : in std_logic; - nmi_n_i : in std_logic; - rdy_i : in std_logic; - rst_rst_n_i : in std_logic; - so_n_i : in std_logic; - a_o : out std_logic_vector (15 downto 0); - d_o : out std_logic_vector (7 downto 0); - rd_o : out std_logic; - sync_o : out std_logic; - wr_n_o : out std_logic; - wr_o : out std_logic - ); - --- Declarations - -end r65c02_tc ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 2.00RC 2018/10/14 11:50:00 jens --- - Performance improvements --- Revision 1.52 2018/09/10 12:14:00 jens --- - RESET generates SYNC now, 1 dead cycle delayed --- Revision 1.52 RC 2018/09/09 03:00:00 jens --- - ADC / SBC flags and A like R65C02 now --- Revision 1.52 BETA 2018/09/05 19:35:00 jens --- - BBRx/BBSx internal cycles like real 65C02 now --- - Bug Fix ADC and SBC in decimal mode (all op codes - --- 1 cycle is missing --- - Bug Fix ADC and SBC in decimal mode (all op codes - --- "Overflow" flag was computed wrong) --- Revision 1.52 BETA 2018/09/02 18:49:00 jens --- - Interrupt NMI and IRQ processing via FETCH stage now --- Revision 1.52 BETA 2018/08/30 15:39:00 jens --- - Interrupt priority order is now: BRQ - NMI - IRQ --- - Performance improvements on-going (Mealy -> Moore) --- Revision 1.52 BETA 2018/08/23 20:27:00 jens --- - Bug Fixes All Branch Instructions --- (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA) --- 3 cycles now if branch forward occur and the branch --- instruction lies on a xxFEh location. --- (BBR, BBS) 6 cycles now if branch forward occur and the --- branch instruction lies on a xxFDh location. --- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now --- - Bug Fix Now all cycles are delayable (WR and internal) --- --- Revision 1.51 RC 2014/04/19 14:44:00 jens --- (never submitted to opencores) --- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH. --- When the ABS address data bytes cross the page --- boundary (e.g. $02FE JMP hhll reads hh from --- $02FF and ll from $0200, instead $02FF and $0300) --- --- Revision 1.5 RC 2013/08/01 11:00:00 jens --- - Change Block name to lower case --- - Bug Fix CMP (IND) - wrongly decoded as function AND --- - Bug Fix BRK should clear decimal flag in P Reg --- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no High Address --- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) - new NOPs created --- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag was computed wrong) --- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed --- - Bug Fix RTI - should increment stack pointer --- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1" in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates. --- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong) --- - Bug Fix RMB, SMB Bug - Bit position decoded wrong --- --- Revision 1.4 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- - Bug Fix STA [(IND)] op$92 ($92 was missed in the connection list at state FETCH) --- --- Revision 1.3 2009/01/04 10:20:50 eda --- Changes for cosmetic issues only --- --- Revision 1.2 2009/01/04 09:23:12 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- - Re-arrage FSM symbols in block FSM_Execution_Unit --- --- Revision 1.1 2009/01/03 16:36:48 eda --- -- no description -- --- --- --- --- VHDL Architecture r65c02_tc.r65c02_tc.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 11:59:49 14.10.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -library r65c02_tc; - -architecture struct of r65c02_tc is - - -- Architecture declarations - - -- Internal signal declarations - - - -- Component Declarations - component core - port ( - clk_clk_i : in std_logic ; - d_i : in std_logic_vector (7 downto 0); - irq_n_i : in std_logic ; - nmi_n_i : in std_logic ; - rdy_i : in std_logic ; - rst_rst_n_i : in std_logic ; - so_n_i : in std_logic ; - a_o : out std_logic_vector (15 downto 0); - d_o : out std_logic_vector (7 downto 0); - rd_o : out std_logic ; - sync_o : out std_logic ; - wr_n_o : out std_logic ; - wr_o : out std_logic - ); - end component; - - -- Optional embedded configurations - -- pragma synthesis_off - for all : core use entity r65c02_tc.core; - -- pragma synthesis_on - - -begin - - -- Instance port mappings. - U_0 : core - port map ( - clk_clk_i => clk_clk_i, - d_i => d_i, - irq_n_i => irq_n_i, - nmi_n_i => nmi_n_i, - rdy_i => rdy_i, - rst_rst_n_i => rst_rst_n_i, - so_n_i => so_n_i, - a_o => a_o, - d_o => d_o, - rd_o => rd_o, - sync_o => sync_o, - wr_n_o => wr_n_o, - wr_o => wr_o - ); - -end struct; Index: rtl/vhdl/core.vhd =================================================================== --- rtl/vhdl/core.vhd (revision 23) +++ rtl/vhdl/core.vhd (nonexistent) @@ -1,396 +0,0 @@ --- VHDL Entity r65c02_tc.core.symbol --- --- Created: --- by - jens.Domain Users (ENTW-7HPZ200) --- at - 11:09:21 08/01/13 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity core is - port( - clk_clk_i : in std_logic; - d_i : in std_logic_vector (7 downto 0); - irq_n_i : in std_logic; - nmi_n_i : in std_logic; - rdy_i : in std_logic; - rst_rst_n_i : in std_logic; - so_n_i : in std_logic; - a_o : out std_logic_vector (15 downto 0); - d_o : out std_logic_vector (7 downto 0); - rd_o : out std_logic; - sync_o : out std_logic; - wr_n_o : out std_logic; - wr_o : out std_logic - ); - --- Declarations - -end core ; - --- (C) 2008 - 2018 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.8 2013/08/01 11:00:00 jens --- - Change Block names to lower case --- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder. --- --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.core.struct --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 17:51:04 27.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -library r65c02_tc; - -architecture struct of core is - - -- Architecture declarations - - -- Internal signal declarations - signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); - signal adr_o_i : std_logic_vector(15 downto 0); - signal adr_pc_o_i : std_logic_vector(15 downto 0); - signal adr_sp_o_i : std_logic_vector(15 downto 0); - signal ch_a_o_i : std_logic_vector(7 downto 0); - signal ch_b_o_i : std_logic_vector(7 downto 0); - signal d_alu_n_o_i : std_logic; - signal d_alu_o_i : std_logic_vector(7 downto 0); - signal d_alu_or_o_i : std_logic; - signal d_alu_prio_o_i : std_logic_vector(7 downto 0); - signal d_regs_in_o_i : std_logic_vector(7 downto 0); - signal d_regs_out_o_i : std_logic_vector(7 downto 0); - signal ld_o_i : std_logic_vector(1 downto 0); - signal ld_pc_o_i : std_logic; - signal ld_sp_o_i : std_logic; - signal load_regs_o_i : std_logic; - signal nmi_o_i : std_logic; - signal offset_o_i : std_logic_vector(15 downto 0); - signal q_a_o_i : std_logic_vector(7 downto 0); - signal q_x_o_i : std_logic_vector(7 downto 0); - signal q_y_o_i : std_logic_vector(7 downto 0); - signal reg_0flag_o_i : std_logic; - signal reg_1flag_o_i : std_logic; - signal reg_7flag_o_i : std_logic; - signal rst_nmi_o_i : std_logic; - signal sel_pc_in_o_i : std_logic; - signal sel_pc_val_o_i : std_logic_vector(1 downto 0); - signal sel_rb_in_o_i : std_logic_vector(1 downto 0); - signal sel_rb_out_o_i : std_logic_vector(1 downto 0); - signal sel_reg_o_i : std_logic_vector(1 downto 0); - signal sel_sp_as_o_i : std_logic; - signal sel_sp_in_o_i : std_logic; - signal var_shift_data_o_i : std_logic_vector(7 downto 0); - - - -- Component Declarations - component fsm_execution_unit - port ( - adr_nxt_pc_i : in std_logic_vector (15 downto 0); - adr_pc_i : in std_logic_vector (15 downto 0); - adr_sp_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic ; - d_alu_i : in std_logic_vector ( 7 downto 0 ); - d_alu_prio_i : in std_logic_vector (7 downto 0); - d_i : in std_logic_vector ( 7 downto 0 ); - d_regs_out_i : in std_logic_vector ( 7 downto 0 ); - irq_n_i : in std_logic ; - nmi_i : in std_logic ; - q_a_i : in std_logic_vector ( 7 downto 0 ); - q_x_i : in std_logic_vector ( 7 downto 0 ); - q_y_i : in std_logic_vector ( 7 downto 0 ); - rdy_i : in std_logic ; - reg_0flag_i : in std_logic ; - reg_1flag_i : in std_logic ; - reg_7flag_i : in std_logic ; - rst_rst_n_i : in std_logic ; - so_n_i : in std_logic ; - a_o : out std_logic_vector (15 downto 0); - adr_o : out std_logic_vector (15 downto 0); - ch_a_o : out std_logic_vector ( 7 downto 0 ); - ch_b_o : out std_logic_vector ( 7 downto 0 ); - d_o : out std_logic_vector ( 7 downto 0 ); - d_regs_in_o : out std_logic_vector ( 7 downto 0 ); - ld_o : out std_logic_vector ( 1 downto 0 ); - ld_pc_o : out std_logic ; - ld_sp_o : out std_logic ; - load_regs_o : out std_logic ; - offset_o : out std_logic_vector ( 15 downto 0 ); - rd_o : out std_logic ; - rst_nmi_o : out std_logic ; - sel_pc_in_o : out std_logic ; - sel_pc_val_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_in_o : out std_logic_vector ( 1 downto 0 ); - sel_rb_out_o : out std_logic_vector ( 1 downto 0 ); - sel_reg_o : out std_logic_vector ( 1 downto 0 ); - sel_sp_as_o : out std_logic ; - sel_sp_in_o : out std_logic ; - sync_o : out std_logic ; - wr_n_o : out std_logic ; - wr_o : out std_logic - ); - end component; - component fsm_intnmi - port ( - clk_clk_i : in std_logic ; - nmi_n_i : in std_logic ; - rst_nmi_i : in std_logic ; - rst_rst_n_i : in std_logic ; - nmi_o : out std_logic - ); - end component; - component reg_pc - port ( - adr_i : in std_logic_vector (15 downto 0); - clk_clk_i : in std_logic ; - ld_i : in std_logic_vector (1 downto 0); - ld_pc_i : in std_logic ; - offset_i : in std_logic_vector (15 downto 0); - rst_rst_n_i : in std_logic ; - sel_pc_in_i : in std_logic ; - sel_pc_val_i : in std_logic_vector (1 downto 0); - adr_nxt_pc_o : out std_logic_vector (15 downto 0); - adr_pc_o : out std_logic_vector (15 downto 0) - ); - end component; - component reg_sp - port ( - adr_low_i : in std_logic_vector (7 downto 0); - clk_clk_i : in std_logic ; - ld_low_i : in std_logic ; - ld_sp_i : in std_logic ; - rst_rst_n_i : in std_logic ; - sel_sp_as_i : in std_logic ; - sel_sp_in_i : in std_logic ; - adr_sp_o : out std_logic_vector (15 downto 0) - ); - end component; - component regbank_axy - port ( - clk_clk_i : in std_logic ; - d_regs_in_i : in std_logic_vector (7 downto 0); - load_regs_i : in std_logic ; - rst_rst_n_i : in std_logic ; - sel_rb_in_i : in std_logic_vector (1 downto 0); - sel_rb_out_i : in std_logic_vector (1 downto 0); - sel_reg_i : in std_logic_vector (1 downto 0); - d_regs_out_o : out std_logic_vector (7 downto 0); - q_a_o : out std_logic_vector (7 downto 0); - q_x_o : out std_logic_vector (7 downto 0); - q_y_o : out std_logic_vector (7 downto 0) - ); - end component; - - -- Optional embedded configurations - -- pragma synthesis_off - for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit; - for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi; - for all : reg_pc use entity r65c02_tc.reg_pc; - for all : reg_sp use entity r65c02_tc.reg_sp; - for all : regbank_axy use entity r65c02_tc.regbank_axy; - -- pragma synthesis_on - - -begin - -- Architecture concurrent statements - -- HDL Embedded Text Block 1 eb1 - -- eb1 1 - var_shift_data_o_i <= x"01"; - - - -- ModuleWare code(v1.12) for instance 'U_11' of 'add' - u_11combo_proc: process (ch_a_o_i, ch_b_o_i) - variable temp_din0 : std_logic_vector(8 downto 0); - variable temp_din1 : std_logic_vector(8 downto 0); - variable temp_sum : unsigned(8 downto 0); - variable temp_carry : std_logic; - begin - temp_din0 := '0' & ch_a_o_i; - temp_din1 := '0' & ch_b_o_i; - temp_carry := '0'; - temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; - d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8); - reg_0flag_o_i <= temp_sum(8) ; - end process u_11combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_8' of 'inv' - reg_1flag_o_i <= not(d_alu_or_o_i); - - -- ModuleWare code(v1.12) for instance 'U_9' of 'inv' - reg_7flag_o_i <= not(d_alu_n_o_i); - - -- ModuleWare code(v1.12) for instance 'U_10' of 'inv' - d_alu_n_o_i <= not(d_alu_o_i(7)); - - -- ModuleWare code(v1.12) for instance 'U_5' of 'lshift' - u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i) - variable temp_shift : std_logic_vector (3 downto 0); - variable temp_dout : std_logic_vector (7 downto 0); - variable temp_din : std_logic_vector (7 downto 0); - begin - temp_din := (others=> 'X'); - temp_shift := ch_a_o_i(3 downto 0); - temp_din := var_shift_data_o_i; - for i in 0 to 3 loop - if (i < 3) then - if (temp_shift(i) = '1') then - temp_dout := (others => '0'); - temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0); - elsif (temp_shift(i) = '0') then - temp_dout := temp_din; - else - temp_dout := (others => 'X'); - end if; - else - if (temp_shift(i) = '1') then - temp_dout := (others => '0'); - elsif (temp_shift(i) = '0') then - temp_dout := temp_din; - else - temp_dout := (others => 'X'); - end if; - end if; - temp_din := temp_dout; - end loop; - d_alu_prio_o_i <= temp_dout; - end process u_5combo_proc; - - -- ModuleWare code(v1.12) for instance 'U_7' of 'por' - d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7); - - -- Instance port mappings. - U_4 : fsm_execution_unit - port map ( - adr_nxt_pc_i => adr_nxt_pc_o_i, - adr_pc_i => adr_pc_o_i, - adr_sp_i => adr_sp_o_i, - clk_clk_i => clk_clk_i, - d_alu_i => d_alu_o_i, - d_alu_prio_i => d_alu_prio_o_i, - d_i => d_i, - d_regs_out_i => d_regs_out_o_i, - irq_n_i => irq_n_i, - nmi_i => nmi_o_i, - q_a_i => q_a_o_i, - q_x_i => q_x_o_i, - q_y_i => q_y_o_i, - rdy_i => rdy_i, - reg_0flag_i => reg_0flag_o_i, - reg_1flag_i => reg_1flag_o_i, - reg_7flag_i => reg_7flag_o_i, - rst_rst_n_i => rst_rst_n_i, - so_n_i => so_n_i, - a_o => a_o, - adr_o => adr_o_i, - ch_a_o => ch_a_o_i, - ch_b_o => ch_b_o_i, - d_o => d_o, - d_regs_in_o => d_regs_in_o_i, - ld_o => ld_o_i, - ld_pc_o => ld_pc_o_i, - ld_sp_o => ld_sp_o_i, - load_regs_o => load_regs_o_i, - offset_o => offset_o_i, - rd_o => rd_o, - rst_nmi_o => rst_nmi_o_i, - sel_pc_in_o => sel_pc_in_o_i, - sel_pc_val_o => sel_pc_val_o_i, - sel_rb_in_o => sel_rb_in_o_i, - sel_rb_out_o => sel_rb_out_o_i, - sel_reg_o => sel_reg_o_i, - sel_sp_as_o => sel_sp_as_o_i, - sel_sp_in_o => sel_sp_in_o_i, - sync_o => sync_o, - wr_n_o => wr_n_o, - wr_o => wr_o - ); - U_3 : fsm_intnmi - port map ( - clk_clk_i => clk_clk_i, - nmi_n_i => nmi_n_i, - rst_nmi_i => rst_nmi_o_i, - rst_rst_n_i => rst_rst_n_i, - nmi_o => nmi_o_i - ); - U_0 : reg_pc - port map ( - adr_i => adr_o_i, - clk_clk_i => clk_clk_i, - ld_i => ld_o_i, - ld_pc_i => ld_pc_o_i, - offset_i => offset_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_pc_in_i => sel_pc_in_o_i, - sel_pc_val_i => sel_pc_val_o_i, - adr_nxt_pc_o => adr_nxt_pc_o_i, - adr_pc_o => adr_pc_o_i - ); - U_1 : reg_sp - port map ( - adr_low_i => adr_o_i(7 DOWNTO 0), - clk_clk_i => clk_clk_i, - ld_low_i => ld_o_i(0), - ld_sp_i => ld_sp_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_sp_as_i => sel_sp_as_o_i, - sel_sp_in_i => sel_sp_in_o_i, - adr_sp_o => adr_sp_o_i - ); - U_2 : regbank_axy - port map ( - clk_clk_i => clk_clk_i, - d_regs_in_i => d_regs_in_o_i, - load_regs_i => load_regs_o_i, - rst_rst_n_i => rst_rst_n_i, - sel_rb_in_i => sel_rb_in_o_i, - sel_rb_out_i => sel_rb_out_o_i, - sel_reg_i => sel_reg_o_i, - d_regs_out_o => d_regs_out_o_i, - q_a_o => q_a_o_i, - q_x_o => q_x_o_i, - q_y_o => q_y_o_i - ); - -end struct; Index: rtl/vhdl/fsm_intnmi.vhd =================================================================== --- rtl/vhdl/fsm_intnmi.vhd (revision 23) +++ rtl/vhdl/fsm_intnmi.vhd (nonexistent) @@ -1,167 +0,0 @@ --- VHDL Entity r65c02_tc.fsm_intnmi.symbol --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:35:56 10.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -entity fsm_intnmi is - port( - clk_clk_i : in std_logic; - nmi_n_i : in std_logic; - rst_nmi_i : in std_logic; - rst_rst_n_i : in std_logic; - nmi_o : out std_logic - ); - --- Declarations - -end fsm_intnmi ; - --- (C) 2008 - 2013 Jens Gutschmidt --- (email: opencores@vivare-services.com) --- --- Versions: --- Revision 1.8 2018/09/01 18:07:00 jens --- - NMI = '0' need at least 1 cycles for correct --- operation now (2 cycles in the past) --- --- Revision 1.7 2013/07/21 11:11:00 jens --- - Changing the title block and internal revision history --- --- Revision 1.6 2009/01/04 10:20:47 eda --- Changes for cosmetic issues only --- --- Revision 1.5 2009/01/04 09:23:10 eda --- - Delete unused nets and blocks (same as R6502_TC) --- - Rename blocks --- --- Revision 1.4 2009/01/03 16:53:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.3 2009/01/03 16:42:02 eda --- - Unused nets and blocks deleted --- - Renamed blocks --- --- Revision 1.2 2008/12/31 19:31:24 eda --- Production Release --- --- --- --- VHDL Architecture r65c02_tc.fsm_intnmi.fsm --- --- Created: --- by - eda.UNKNOWN (ENTW-7HPZ200) --- at - 12:35:56 10.09.2018 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5) --- --- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt --- --- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version. --- --- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License along with this program. If not, see . --- --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; - -architecture fsm of fsm_intnmi is - - type state_type is ( - idle, - idle1, - IMP - ); - - -- State vector declaration - attribute state_vector : string; - attribute state_vector of fsm : architecture is "current_state"; - - -- Declare current and next state signals - signal current_state : state_type; - signal next_state : state_type; - - -- Declare any pre-registered internal signals - signal nmi_o_cld : std_logic ; - -begin - - ----------------------------------------------------------------- - clocked_proc : process ( - clk_clk_i, - rst_rst_n_i - ) - ----------------------------------------------------------------- - begin - if (rst_rst_n_i = '0') then - current_state <= idle; - -- Default Reset Values - nmi_o_cld <= '0'; - elsif (clk_clk_i'event and clk_clk_i = '1') then - current_state <= next_state; - -- Default Assignment To Internals - nmi_o_cld <= '0'; - - -- Combined Actions - case current_state is - when idle1 => - if (nmi_n_i = '0') then - nmi_o_cld <= '1'; - end if; - when IMP => - nmi_o_cld <= '1'; - if (rst_nmi_i = '1') then - nmi_o_cld <= '0'; - end if; - when others => - null; - end case; - end if; - end process clocked_proc; - - ----------------------------------------------------------------- - nextstate_proc : process ( - current_state, - nmi_n_i, - rst_nmi_i - ) - ----------------------------------------------------------------- - begin - case current_state is - when idle => - if (nmi_n_i = '1') then - next_state <= idle1; - else - next_state <= idle; - end if; - when idle1 => - if (nmi_n_i = '0') then - next_state <= IMP; - else - next_state <= idle1; - end if; - when IMP => - if (rst_nmi_i = '1') then - next_state <= idle; - else - next_state <= IMP; - end if; - when others => - next_state <= idle; - end case; - end process nextstate_proc; - - -- Concurrent Statements - -- Clocked output assignments - nmi_o <= nmi_o_cld; -end fsm; Index: rtl/vhdl/__empty__ ===================================================================

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