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https://opencores.org/ocsvn/csa/csa/trunk
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- This comparison shows the changes necessary to convert path
/csa/trunk/bench
- from Rev 48 to Rev 49
- ↔ Reverse comparison
Rev 48 → Rev 49
/group_decrypt_tb.v
0,0 → 1,143
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// this is the test bench for decrypt module |
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`include "../bench/timescale.v" |
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module group_decrypt_tb; |
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reg clk; |
reg rst; |
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reg [ 8*8-1:0] ck; |
reg ks_start; |
reg init; |
reg last; |
reg gd_en; |
wire [ 8*8-1:0] dec_packet; |
reg [ 8*8-1:0] enc_packet; |
wire [56*8-1:0] kk; |
wire valid; |
integer ii; |
integer jj; |
integer offset; |
initial |
begin |
$read_data( |
"../test_dat/group_decrypt.in" |
,ck |
); |
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init=1'h0; |
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// calculate kk |
repeat(4) @(posedge clk) |
ks_start=1'h1; |
@(posedge clk); |
ks_start=1'h0; |
repeat(14) @(posedge clk) |
jj=0; |
$display("kk=%x",kk); |
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// input encrypt packets |
offset=8+(0)*8; |
$read_data( |
"../test_dat/group_decrypt.in" |
, offset |
, enc_packet); |
init=1'h1; |
last=1'h0; |
gd_en=1'h1; |
@(posedge clk); |
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for(ii=1;ii<23-1;ii=ii+1) |
begin |
init=1'h0; |
last=1'h0; |
gd_en=1'h1; |
offset=8+(ii)*8; |
$read_data( |
"../test_dat/group_decrypt.in" |
, offset |
, enc_packet); |
@(posedge clk); |
end |
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offset=8+(23-1)*8; |
$read_data( |
"../test_dat/group_decrypt.in" |
, offset |
, enc_packet); |
init=1'h0; |
last=1'h1; |
gd_en=1'h1; |
@(posedge clk); |
gd_en=1'h0; |
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repeat(10)@(posedge clk); |
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$stop; |
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end |
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always @(posedge clk) |
if(valid) |
begin |
if(jj==0) |
begin |
$write_data( |
"../test_dat/group_decrypt.out.v" |
, dec_packet); |
jj=1; |
end |
else |
$write_data( |
"../test_dat/group_decrypt.out.v" |
, "a" |
, dec_packet); |
end |
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group_decrypt group_decrypt( |
. clk (clk) |
, . rst (rst) |
, . en (gd_en) |
, . init (init) |
, . last (last) |
, . ck (ck) |
, . kk (kk) |
, . group (enc_packet) |
, . valid (valid) |
, . ogroup (dec_packet) |
); |
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key_schedule key_schedule( |
.clk (clk) |
, .rst (rst) |
, .start (ks_start) |
, .ck (ck) |
, .busy () |
, .done () |
, .kk (kk) |
); |
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initial |
begin |
clk=1'b0; |
forever #5 clk=~clk; |
end |
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initial |
begin |
rst=1'b1; |
@(posedge clk); |
@(posedge clk); |
rst=1'h0; |
end |
endmodule |
/timescale.v
1,0 → 1,143
`timescale 10ns/1ns |
`timescale 1ns/100ps |