URL
https://opencores.org/ocsvn/csa/csa/trunk
Subversion Repositories csa
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- This comparison shows the changes necessary to convert path
/csa/trunk
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/quartus10/csa_fpga.v
37,28 → 37,12
`define STA_WIDTH 4 |
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//////////////////////////////////////////////////////////////////////////////// |
// led control |
// led segement control |
//////////////////////////////////////////////////////////////////////////////// |
reg [`CNT_WIDTH-1:0]led_cnt; |
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always @(posedge usbclk) |
led_cnt <= led_cnt + `CNT_WIDTH'h00001; |
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wire sec_clk = led_cnt[`CNT_WIDTH-1]; |
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led_cnt led1( |
.clk (usbclk) |
, .rst (rst) |
, .scan (sec_clk) |
, .led (led) |
); |
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wire seg_clk = led_cnt[`CNT_WIDTH-16]; |
ledseg_cnt ledseg1( |
ledseg_cnt ledseg_cnt( |
.clk (usbclk) |
, .rst (rst) |
, .scan (seg_clk) |
, .data (usb_dat_in) |
, .seg (ledseg) |
, .segd (seg_d) |
/quartus10/hex2seg.v
0,0 → 1,26
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module hex2seg( |
input [3:0] hex |
, output reg [7:0] seg |
); |
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always @(hex) |
case (hex) // hgfedcba |
4'h0:seg<=~8'b00111111; |
4'h1:seg<=~8'b00000110; |
4'h2:seg<=~8'b01011011; |
4'h3:seg<=~8'b01001111; |
4'h4:seg<=~8'b01100110; |
4'h5:seg<=~8'b01101101; |
4'h6:seg<=~8'b01111101; |
4'h7:seg<=~8'b00000111; |
4'h8:seg<=~8'b01111111; |
4'h9:seg<=~8'b01101111; |
4'ha:seg<=~8'b01110111; |
4'hb:seg<=~8'b01111100; |
4'hc:seg<=~8'b00111001; |
4'hd:seg<=~8'b01011110; |
4'he:seg<=~8'b01111001; |
4'hf:seg<=~8'b01110001; |
endcase |
endmodule |
/quartus10/ledseg_cnt.v
0,0 → 1,52
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|
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// this file control led segment controler module |
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module ledseg_cnt( |
input clk // clock |
, input rst // reset , high active |
, input [15:0] data // the data want output at led segment |
, output reg [ 3:0] seg // led segment scan signal |
, output [ 7:0] segd // led segment output |
); |
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`define CNT_W 11 // count reg width |
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// interival variable |
reg [`CNT_W-1:0] cnt; |
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always @(posedge clk) |
cnt<=cnt+11'h001; // up reg |
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reg h; |
always @(cnt or data) |
begin |
case (cnt[`CNT_W-1:`CNT_W-2]) |
2'b00:h = data[15:12]; |
2'b01:h = data[11: 8]; |
2'b10:h = data[7 : 4]; |
2'b11:h = data[3 : 0]; |
default:h = 4'hf; |
endcase |
end |
|
always @(cnt) |
begin |
case (cnt[`CNT_W-1:`CNT_W-2]) |
2'b00:seg = 4'b1110; |
2'b01:seg = 4'b1101; |
2'b10:seg = 4'b1011; |
2'b11:seg = 4'b0111; |
default:seg = 4'hf; |
endcase |
end |
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hex2seg h2s( |
.hex(h) |
, .seg(segd) |
); |
|
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endmodule |
/quartus10/led_cnt.v
0,0 → 1,22
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// this file |
// led controler |
|
module led_cnt( |
input clk // clock |
, input rst // reset , high active |
, input scan |
, output reg [7:0] led |
); |
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reg scan_l; |
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always @(posedge clk) |
scan_l <= scan; |
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always @(posedge clk) |
if(~rst) |
led <= 8'hfe; |
else if (scan & ~scan_l) |
led <= {led[0],led[7:1]}; |
endmodule |