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/verilog/dbg_cpu.v

verilog/dbg_cpu.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/dbg_cpu_defines.v =================================================================== --- verilog/dbg_cpu_defines.v (nonexistent) +++ verilog/dbg_cpu_defines.v (revision 158) @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_cpu_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2004/03/31 14:34:09 igorm +// data_cnt_lim length changed to reduce number of warnings. +// +// Revision 1.4 2004/03/28 20:27:02 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.3 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.2 2004/01/17 17:01:14 mohor +// Almost finished. +// +// Revision 1.1 2004/01/16 14:53:33 mohor +// *** empty log message *** +// +// +// + + + +// Defining length of the command +`define DBG_CPU_CMD_LEN 3'd4 +`define DBG_CPU_CMD_CNT_WIDTH 3 + +// Defining length of the access_type field +`define DBG_CPU_ACC_TYPE_LEN 3'd4 + +// Defining length of the address +`define DBG_CPU_ADR_LEN 6'd32 + +// Defining length of the length register +`define DBG_CPU_LEN_LEN 5'd16 + +// Defining total length of the DR needed +`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN) + +// Defining length of the CRC +`define DBG_CPU_CRC_LEN 6'd32 +`define DBG_CPU_CRC_CNT_WIDTH 6 + +// Defining length of status +`define DBG_CPU_STATUS_LEN 3'd4 +`define DBG_CPU_STATUS_CNT_WIDTH 3 + +// Defining length of the data +`define DBG_CPU_DATA_CNT_WIDTH (`DBG_CPU_LEN_LEN + 3) +`define DBG_CPU_DATA_CNT_LIM_WIDTH `DBG_CPU_LEN_LEN + +// Defining length of the control register +`define DBG_CPU_CTRL_LEN 2 + +//Defining commands +`define DBG_CPU_GO 4'h0 +`define DBG_CPU_RD_COMM 4'h1 +`define DBG_CPU_WR_COMM 4'h2 +`define DBG_CPU_RD_CTRL 4'h3 +`define DBG_CPU_WR_CTRL 4'h4 + +// Defining access types for wishbone +`define DBG_CPU_WRITE 4'h2 +`define DBG_CPU_READ 4'h6 + +

verilog/dbg_cpu_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/dbg_wb.v =================================================================== --- verilog/dbg_wb.v (nonexistent) +++ verilog/dbg_wb.v (revision 158) @@ -0,0 +1,1175 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_wb.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.22 2004/04/01 11:56:59 igorm +// Port names and defines for the supported CPUs changed. +// +// Revision 1.21 2004/03/31 14:34:09 igorm +// data_cnt_lim length changed to reduce number of warnings. +// +// Revision 1.20 2004/03/28 20:27:02 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.19 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.18 2004/01/25 14:04:18 mohor +// All flipflops are reset. +// +// Revision 1.17 2004/01/22 13:58:53 mohor +// Port signals are all set to zero after reset. +// +// Revision 1.16 2004/01/19 07:32:41 simons +// Reset values width added because of FV, a good sentence changed because some tools can not handle it. +// +// Revision 1.15 2004/01/17 18:01:24 mohor +// New version. +// +// Revision 1.14 2004/01/16 14:51:33 mohor +// cpu registers added. +// +// Revision 1.13 2004/01/15 12:09:43 mohor +// Working. +// +// Revision 1.12 2004/01/14 22:59:18 mohor +// Temp version. +// +// Revision 1.11 2004/01/14 12:29:40 mohor +// temp version. Resets will be changed in next version. +// +// Revision 1.10 2004/01/13 11:28:14 mohor +// tmp version. +// +// Revision 1.9 2004/01/10 07:50:24 mohor +// temp version. +// +// Revision 1.8 2004/01/09 12:48:44 mohor +// tmp version. +// +// Revision 1.7 2004/01/08 17:53:36 mohor +// tmp version. +// +// Revision 1.6 2004/01/07 11:58:56 mohor +// temp4 version. +// +// Revision 1.5 2004/01/06 17:15:19 mohor +// temp3 version. +// +// Revision 1.4 2004/01/05 12:16:00 mohor +// tmp2 version. +// +// Revision 1.3 2003/12/23 16:22:46 mohor +// Tmp version. +// +// Revision 1.2 2003/12/23 15:26:26 mohor +// Small fix. +// +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_wb_defines.v" + +// Top module +module dbg_wb( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + + wishbone_ce_i, + crc_match_i, + crc_en_o, + shift_crc_o, + rst_i, + + // WISHBONE common signals + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o, + wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o + + ); + +// JTAG signals +input tck_i; +input tdi_i; +output tdo_o; + +// TAP states +input shift_dr_i; +input pause_dr_i; +input update_dr_i; + +input wishbone_ce_i; +input crc_match_i; +output crc_en_o; +output shift_crc_o; +input rst_i; +// WISHBONE common signals +input wb_clk_i; + +// WISHBONE master interface +output [31:0] wb_adr_o; +output [31:0] wb_dat_o; +input [31:0] wb_dat_i; +output wb_cyc_o; +output wb_stb_o; +output [3:0] wb_sel_o; +output wb_we_o; +input wb_ack_i; +output wb_cab_o; +input wb_err_i; +output [2:0] wb_cti_o; +output [1:0] wb_bte_o; + +reg wb_cyc_o; + +reg tdo_o; + +reg [31:0] wb_dat_tmp, wb_dat_dsff; +reg [31:0] wb_adr_dsff; +reg [3:0] wb_sel_dsff; +reg wb_we_dsff; +reg [`DBG_WB_DR_LEN -1 :0] dr; +wire enable; +wire cmd_cnt_en; +reg [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt; +wire cmd_cnt_end; +reg cmd_cnt_end_q; +reg addr_len_cnt_en; +reg [5:0] addr_len_cnt; +wire addr_len_cnt_end; +reg addr_len_cnt_end_q; +reg crc_cnt_en; +reg [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt; +wire crc_cnt_end; +reg crc_cnt_end_q; +reg data_cnt_en; +reg [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt; +reg [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit; +wire data_cnt_end; +reg data_cnt_end_q; + +reg crc_match_reg; + +reg [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type; +reg [`DBG_WB_ADR_LEN -1:0] adr; +reg [`DBG_WB_LEN_LEN -1:0] len; +reg [`DBG_WB_LEN_LEN:0] len_var; +reg start_rd_tck; +reg rd_tck_started; +reg start_rd_csff; +reg start_wb_rd; +reg start_wb_rd_q; +reg start_wr_tck; +reg start_wr_csff; +reg start_wb_wr; +reg start_wb_wr_q; + +reg status_cnt_en; +wire status_cnt_end; + +wire byte, half, long; +reg byte_q, half_q, long_q; + +reg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt; + +reg [`DBG_WB_STATUS_LEN -1:0] status; + +reg wb_error, wb_error_csff, wb_error_tck; +reg wb_overrun, wb_overrun_csff, wb_overrun_tck; +reg underrun_tck; + +reg busy_wb; +reg busy_tck; +reg wb_end; +reg wb_end_rst; +reg wb_end_rst_csff; +reg wb_end_csff; +reg wb_end_tck, wb_end_tck_q; +reg busy_csff; +reg latch_data; +reg update_dr_csff, update_dr_wb; + +reg set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q; +wire [31:0] input_data; + +wire len_eq_0; +wire crc_cnt_31; + +reg [1:0] ptr; +reg [2:0] fifo_cnt; +wire fifo_full; +wire fifo_empty; +reg [7:0] mem [0:3]; +reg [2:0] mem_ptr_dsff; +reg wishbone_ce_csff; +reg mem_ptr_init; +reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd; +wire curr_cmd_go; +reg curr_cmd_go_q; +wire curr_cmd_wr_comm; +wire curr_cmd_rd_comm; +wire acc_type_read; +wire acc_type_write; +wire acc_type_8bit; +wire acc_type_16bit; +wire acc_type_32bit; + + +assign enable = wishbone_ce_i & shift_dr_i; +assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); +assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC + +assign curr_cmd_go = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end; +assign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end; +assign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end; + +assign acc_type_read = (acc_type == `DBG_WB_READ8 || acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_READ32); +assign acc_type_write = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32); + +assign acc_type_8bit = (acc_type == `DBG_WB_READ8 || acc_type == `DBG_WB_WRITE8); +assign acc_type_16bit = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16); +assign acc_type_32bit = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32); + + +// Selecting where to take the data from +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + ptr <= #1 2'h0; + else if (update_dr_i) + ptr <= #1 2'h0; + else if (curr_cmd_go && acc_type_read && crc_cnt_31) // first latch + ptr <= #1 ptr + 1'b1; + else if (curr_cmd_go && acc_type_read && byte && (!byte_q)) + ptr <= ptr + 1'd1; +end + + +// Shift register for shifting in and out the data +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + latch_data <= #1 1'b0; + dr <= #1 {`DBG_WB_DR_LEN{1'b0}}; + end + else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from iternal regs) + begin + dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <= #1 {acc_type, adr, len}; + end + else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB) + begin + dr[31:0] <= #1 input_data[31:0]; + latch_data <= #1 1'b1; + end + else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB) + begin + if (acc_type == `DBG_WB_READ8) + begin + if(byte & (~byte_q)) + begin + case (ptr) // synthesis parallel_case + 2'b00 : dr[31:24] <= #1 input_data[31:24]; + 2'b01 : dr[31:24] <= #1 input_data[23:16]; + 2'b10 : dr[31:24] <= #1 input_data[15:8]; + 2'b11 : dr[31:24] <= #1 input_data[7:0]; + endcase + latch_data <= #1 1'b1; + end + else + begin + dr[31:24] <= #1 {dr[30:24], 1'b0}; + latch_data <= #1 1'b0; + end + end + else if (acc_type == `DBG_WB_READ16) + begin + if(half & (~half_q)) + begin + if (ptr[1]) + dr[31:16] <= #1 input_data[15:0]; + else + dr[31:16] <= #1 input_data[31:16]; + latch_data <= #1 1'b1; + end + else + begin + dr[31:16] <= #1 {dr[30:16], 1'b0}; + latch_data <= #1 1'b0; + end + end + else if (acc_type == `DBG_WB_READ32) + begin + if(long & (~long_q)) + begin + dr[31:0] <= #1 input_data[31:0]; + latch_data <= #1 1'b1; + end + else + begin + dr[31:0] <= #1 {dr[30:0], 1'b0}; + latch_data <= #1 1'b0; + end + end + end + else if (enable && (!addr_len_cnt_end)) + begin + dr <= #1 {dr[`DBG_WB_DR_LEN -2:0], tdi_i}; + end +end + + + +assign cmd_cnt_en = enable & (~cmd_cnt_end); + + +// Command counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}}; + else if (update_dr_i) + cmd_cnt <= #1 {`DBG_WB_CMD_CNT_WIDTH{1'b0}}; + else if (cmd_cnt_en) + cmd_cnt <= #1 cmd_cnt + 1'b1; +end + + +// Assigning current command +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + curr_cmd <= #1 {`DBG_WB_CMD_LEN{1'b0}}; + else if (update_dr_i) + curr_cmd <= #1 {`DBG_WB_CMD_LEN{1'b0}}; + else if (cmd_cnt == (`DBG_WB_CMD_LEN -1)) + curr_cmd <= #1 {dr[`DBG_WB_CMD_LEN-2 :0], tdi_i}; +end + + +// Assigning current command +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + curr_cmd_go_q <= #1 1'b0; + else + curr_cmd_go_q <= #1 curr_cmd_go; +end + + +always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end) +begin + if (enable && (!addr_len_cnt_end)) + begin + if (cmd_cnt_end && curr_cmd_wr_comm) + addr_len_cnt_en = 1'b1; + else if (crc_cnt_end && curr_cmd_rd_comm) + addr_len_cnt_en = 1'b1; + else + addr_len_cnt_en = 1'b0; + end + else + addr_len_cnt_en = 1'b0; +end + + +// Address/length counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + addr_len_cnt <= #1 6'h0; + else if (update_dr_i) + addr_len_cnt <= #1 6'h0; + else if (addr_len_cnt_en) + addr_len_cnt <= #1 addr_len_cnt + 1'b1; +end + + +always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end) +begin + if (enable && (!data_cnt_end)) + begin + if (cmd_cnt_end && curr_cmd_go && acc_type_write) + data_cnt_en = 1'b1; + else if (crc_cnt_end && curr_cmd_go && acc_type_read) + data_cnt_en = 1'b1; + else + data_cnt_en = 1'b0; + end + else + data_cnt_en = 1'b0; +end + + +// Data counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + data_cnt <= #1 {`DBG_WB_DATA_CNT_WIDTH{1'b0}}; + else if (update_dr_i) + data_cnt <= #1 {`DBG_WB_DATA_CNT_WIDTH{1'b0}}; + else if (data_cnt_en) + data_cnt <= #1 data_cnt + 1'b1; +end + + + +// Upper limit. Data counter counts until this value is reached. +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + data_cnt_limit <= #1 {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}}; + else if (update_dr_i) + data_cnt_limit <= #1 len + 1'b1; +end + + +always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end) +begin + if (enable && (!crc_cnt_end) && cmd_cnt_end) + begin + if (addr_len_cnt_end && curr_cmd_wr_comm) + crc_cnt_en = 1'b1; + else if (data_cnt_end && curr_cmd_go && acc_type_write) + crc_cnt_en = 1'b1; + else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm)) + crc_cnt_en = 1'b1; + else + crc_cnt_en = 1'b0; + end + else + crc_cnt_en = 1'b0; +end + + +// crc counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_cnt <= #1 {`DBG_WB_CRC_CNT_WIDTH{1'b0}}; + else if(crc_cnt_en) + crc_cnt <= #1 crc_cnt + 1'b1; + else if (update_dr_i) + crc_cnt <= #1 {`DBG_WB_CRC_CNT_WIDTH{1'b0}}; +end + +assign cmd_cnt_end = cmd_cnt == `DBG_WB_CMD_LEN; +assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN; +assign crc_cnt_end = crc_cnt == `DBG_WB_CRC_CNT_WIDTH'd32; +assign crc_cnt_31 = crc_cnt == `DBG_WB_CRC_CNT_WIDTH'd31; +assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000}); + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + crc_cnt_end_q <= #1 1'b0; + cmd_cnt_end_q <= #1 1'b0; + data_cnt_end_q <= #1 1'b0; + addr_len_cnt_end_q <= #1 1'b0; + end + else + begin + crc_cnt_end_q <= #1 crc_cnt_end; + cmd_cnt_end_q <= #1 cmd_cnt_end; + data_cnt_end_q <= #1 data_cnt_end; + addr_len_cnt_end_q <= #1 addr_len_cnt_end; + end +end + + +// Status counter is made of 4 serialy connected registers +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + status_cnt <= #1 {`DBG_WB_STATUS_CNT_WIDTH{1'b0}}; + else if (update_dr_i) + status_cnt <= #1 {`DBG_WB_STATUS_CNT_WIDTH{1'b0}}; + else if (status_cnt_en) + status_cnt <= #1 status_cnt + 1'b1; +end + + +always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end) +begin + if (enable && (!status_cnt_end)) + begin + if (crc_cnt_end && curr_cmd_wr_comm) + status_cnt_en = 1'b1; + else if (crc_cnt_end && curr_cmd_go && acc_type_write) + status_cnt_en = 1'b1; + else if (data_cnt_end && curr_cmd_go && acc_type_read) + status_cnt_en = 1'b1; + else if (addr_len_cnt_end && curr_cmd_rd_comm) + status_cnt_en = 1'b1; + else + status_cnt_en = 1'b0; + end + else + status_cnt_en = 1'b0; +end + + +assign status_cnt_end = status_cnt == `DBG_WB_STATUS_LEN; + + +// Latching acc_type, address and length +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + acc_type <= #1 {`DBG_WB_ACC_TYPE_LEN{1'b0}}; + adr <= #1 {`DBG_WB_ADR_LEN{1'b0}}; + len <= #1 {`DBG_WB_LEN_LEN{1'b0}}; + set_addr <= #1 1'b0; + end + else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm) + begin + acc_type <= #1 dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN]; + adr <= #1 dr[`DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_LEN_LEN]; + len <= #1 dr[`DBG_WB_LEN_LEN -1:0]; + set_addr <= #1 1'b1; + end + else if(wb_end_tck) // Writing back the address + begin + adr <= #1 wb_adr_dsff; + end + else + set_addr <= #1 1'b0; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_match_reg <= #1 1'b0; + else if(crc_cnt_end & (~crc_cnt_end_q)) + crc_match_reg <= #1 crc_match_i; +end + + +// Length counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}}; + else if(update_dr_i) + len_var <= #1 len + 1'b1; + else if (start_rd_tck) + begin + case (acc_type) // synthesis parallel_case + `DBG_WB_READ8 : + if (len_var > 'd1) + len_var <= #1 len_var - 1'd1; + else + len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}}; + `DBG_WB_READ16: + if (len_var > 'd2) + len_var <= #1 len_var - 2'd2; + else + len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}}; + `DBG_WB_READ32: + if (len_var > 'd4) + len_var <= #1 len_var - 3'd4; + else + len_var <= #1 {1'b0, {`DBG_WB_LEN_LEN{1'b0}}}; + default: len_var <= #1 {1'bx, {`DBG_WB_LEN_LEN{1'bx}}}; + endcase + end +end + + +assign len_eq_0 = len_var == 'h0; + + +assign byte = data_cnt[2:0] == 3'd7; +assign half = data_cnt[3:0] == 4'd15; +assign long = data_cnt[4:0] == 5'd31; + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + byte_q <= #1 1'b0; + half_q <= #1 1'b0; + long_q <= #1 1'b0; + end + else + begin + byte_q <= #1 byte; + half_q <= #1 half; + long_q <= #1 long; + end +end + + +// Start wishbone write cycle +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + start_wr_tck <= #1 1'b0; + wb_dat_tmp <= #1 32'h0; + end + else if (curr_cmd_go && acc_type_write) + begin + case (acc_type) // synthesis parallel_case full_case + `DBG_WB_WRITE8 : begin + if (byte_q) + begin + start_wr_tck <= #1 1'b1; + wb_dat_tmp <= #1 {4{dr[7:0]}}; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + `DBG_WB_WRITE16 : begin + if (half_q) + begin + start_wr_tck <= #1 1'b1; + wb_dat_tmp <= #1 {2{dr[15:0]}}; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + `DBG_WB_WRITE32 : begin + if (long_q) + begin + start_wr_tck <= #1 1'b1; + wb_dat_tmp <= #1 dr[31:0]; + end + else + begin + start_wr_tck <= #1 1'b0; + end + end + endcase + end + else + start_wr_tck <= #1 1'b0; +end + + +// wb_dat_o in WB clk domain +always @ (posedge wb_clk_i) +begin + wb_dat_dsff <= #1 wb_dat_tmp; +end + +assign wb_dat_o = wb_dat_dsff; + + +// Start wishbone read cycle +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + start_rd_tck <= #1 1'b0; + else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read) // First read after cmd is entered + start_rd_tck <= #1 1'b1; + else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started)) + start_rd_tck <= #1 1'b1; + else + start_rd_tck <= #1 1'b0; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + rd_tck_started <= #1 1'b0; + else if (update_dr_i || wb_end_tck && (!wb_end_tck_q)) + rd_tck_started <= #1 1'b0; + else if (start_rd_tck) + rd_tck_started <= #1 1'b1; +end + + + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + begin + start_rd_csff <= #1 1'b0; + start_wb_rd <= #1 1'b0; + start_wb_rd_q <= #1 1'b0; + + start_wr_csff <= #1 1'b0; + start_wb_wr <= #1 1'b0; + start_wb_wr_q <= #1 1'b0; + + set_addr_csff <= #1 1'b0; + set_addr_wb <= #1 1'b0; + set_addr_wb_q <= #1 1'b0; + end + else + begin + start_rd_csff <= #1 start_rd_tck; + start_wb_rd <= #1 start_rd_csff; + start_wb_rd_q <= #1 start_wb_rd; + + start_wr_csff <= #1 start_wr_tck; + start_wb_wr <= #1 start_wr_csff; + start_wb_wr_q <= #1 start_wb_wr; + + set_addr_csff <= #1 set_addr; + set_addr_wb <= #1 set_addr_csff; + set_addr_wb_q <= #1 set_addr_wb; + end +end + + +// wb_cyc_o +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_cyc_o <= #1 1'b0; + else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q))) + wb_cyc_o <= #1 1'b1; + else if (wb_ack_i || wb_err_i) + wb_cyc_o <= #1 1'b0; +end + + +// wb_adr_o logic +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_adr_dsff <= #1 32'h0; + else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address + wb_adr_dsff <= #1 adr; + else if (wb_ack_i) + begin + if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8)) + wb_adr_dsff <= #1 wb_adr_dsff + 1'd1; + else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16)) + wb_adr_dsff <= #1 wb_adr_dsff + 2'd2; + else + wb_adr_dsff <= #1 wb_adr_dsff + 3'd4; + end +end + + +assign wb_adr_o = wb_adr_dsff; + + +// adr byte | short | long +// 0 1000 1100 1111 +// 1 0100 err err +// 2 0010 0011 err +// 3 0001 err err +// wb_sel_o logic + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_sel_dsff[3:0] <= #1 4'h0; + else + begin + case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case + {2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8; + {2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC; + {2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF; + {2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4; + {2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2; + {2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3; + {2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1; + default: wb_sel_dsff[3:0] <= #1 4'hx; + endcase + end +end + + +assign wb_sel_o = wb_sel_dsff; + + +always @ (posedge wb_clk_i) +begin + wb_we_dsff <= #1 curr_cmd_go && acc_type_write; +end + + +assign wb_we_o = wb_we_dsff; +assign wb_cab_o = 1'b0; +assign wb_stb_o = wb_cyc_o; +assign wb_cti_o = 3'h0; // always performing single access +assign wb_bte_o = 2'h0; // always performing single access + + + +// Logic for detecting end of transaction +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_end <= #1 1'b0; + else if (wb_ack_i || wb_err_i) + wb_end <= #1 1'b1; + else if (wb_end_rst) + wb_end <= #1 1'b0; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + wb_end_csff <= #1 1'b0; + wb_end_tck <= #1 1'b0; + wb_end_tck_q <= #1 1'b0; + end + else + begin + wb_end_csff <= #1 wb_end; + wb_end_tck <= #1 wb_end_csff; + wb_end_tck_q <= #1 wb_end_tck; + end +end + + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + begin + wb_end_rst_csff <= #1 1'b0; + wb_end_rst <= #1 1'b0; + end + else + begin + wb_end_rst_csff <= #1 wb_end_tck; + wb_end_rst <= #1 wb_end_rst_csff; + end +end + + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + busy_wb <= #1 1'b0; + else if (wb_end_rst) + busy_wb <= #1 1'b0; + else if (wb_cyc_o) + busy_wb <= #1 1'b1; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + busy_csff <= #1 1'b0; + busy_tck <= #1 1'b0; + + update_dr_csff <= #1 1'b0; + update_dr_wb <= #1 1'b0; + end + else + begin + busy_csff <= #1 busy_wb; + busy_tck <= #1 busy_csff; + + update_dr_csff <= #1 update_dr_i; + update_dr_wb <= #1 update_dr_csff; + end +end + + +// Detecting WB error +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_error <= #1 1'b0; + else if(wb_err_i) + wb_error <= #1 1'b1; + else if(update_dr_wb) // error remains active until update_dr arrives + wb_error <= #1 1'b0; +end + + +// Detecting overrun when write operation. +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + wb_overrun <= #1 1'b0; + else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o) + wb_overrun <= #1 1'b1; + else if(update_dr_wb) // error remains active until update_dr arrives + wb_overrun <= #1 1'b0; +end + + +// Detecting underrun when read operation +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + underrun_tck <= #1 1'b0; + else if(latch_data && fifo_empty && (!data_cnt_end)) + underrun_tck <= #1 1'b1; + else if(update_dr_i) // error remains active until update_dr arrives + underrun_tck <= #1 1'b0; +end + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + wb_error_csff <= #1 1'b0; + wb_error_tck <= #1 1'b0; + + wb_overrun_csff <= #1 1'b0; + wb_overrun_tck <= #1 1'b0; + end + else + begin + wb_error_csff <= #1 wb_error; + wb_error_tck <= #1 wb_error_csff; + + wb_overrun_csff <= #1 wb_overrun; + wb_overrun_tck <= #1 wb_overrun_csff; + end +end + + + +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + begin + wishbone_ce_csff <= #1 1'b0; + mem_ptr_init <= #1 1'b0; + end + else + begin + wishbone_ce_csff <= #1 wishbone_ce_i; + mem_ptr_init <= #1 ~wishbone_ce_csff; + end +end + + +// Logic for latching data that is read from wishbone +always @ (posedge wb_clk_i or posedge rst_i) +begin + if (rst_i) + mem_ptr_dsff <= #1 3'h0; + else if(mem_ptr_init) + mem_ptr_dsff <= #1 3'h0; + else if (wb_ack_i) + begin + if (acc_type == `DBG_WB_READ8) + mem_ptr_dsff <= #1 mem_ptr_dsff + 1'd1; + else if (acc_type == `DBG_WB_READ16) + mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2; + end +end + + +// Logic for latching data that is read from wishbone +always @ (posedge wb_clk_i) +begin + if (wb_ack_i) + begin + case (wb_sel_dsff) // synthesis parallel_case + 4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; // byte + 4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16]; // byte + 4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; // byte + 4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00]; // byte + + 4'b1100 : // half + begin + mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24]; + mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16]; + end + 4'b0011 : // half + begin + mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08]; + mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00]; + end + 4'b1111 : // long + begin + mem[0] <= #1 wb_dat_i[31:24]; + mem[1] <= #1 wb_dat_i[23:16]; + mem[2] <= #1 wb_dat_i[15:08]; + mem[3] <= #1 wb_dat_i[07:00]; + end + default : // long + begin + mem[0] <= #1 8'hxx; + mem[1] <= #1 8'hxx; + mem[2] <= #1 8'hxx; + mem[3] <= #1 8'hxx; + end + endcase + end +end + + + +assign input_data = {mem[0], mem[1], mem[2], mem[3]}; + + +// Fifo counter and empty/full detection +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + fifo_cnt <= #1 3'h0; + else if (update_dr_i) + fifo_cnt <= #1 3'h0; + else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing + begin + case (acc_type) // synthesis parallel_case + `DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1; + `DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2; + `DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4; + default: fifo_cnt <= #1 3'bxxx; + endcase + end + else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing + begin + case (acc_type) // synthesis parallel_case + `DBG_WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1; + `DBG_WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2; + `DBG_WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4; + default: fifo_cnt <= #1 3'bxxx; + endcase + end +end + + +assign fifo_full = fifo_cnt == 3'h4; +assign fifo_empty = fifo_cnt == 3'h0; + + +// TDO multiplexer +always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or + curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i + or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status + or addr_len_cnt_end or addr_len_cnt_end_q) +begin + if (pause_dr_i) + begin + tdo_o = busy_tck; + end + else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write )) + begin + tdo_o = ~crc_match_i; + end + else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end)) + begin + tdo_o = dr[31]; + end + else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q)) + begin + tdo_o = ~crc_match_reg; + end + else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q)) + begin + tdo_o = ~crc_match_reg; + end + else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end)) + begin + tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1]; + end + else if (status_cnt_en) + begin + tdo_o = status[3]; + end + else + begin + tdo_o = 1'b0; + end +end + +// Status register +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + status <= #1 {`DBG_WB_STATUS_LEN{1'b0}}; + end + else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read))) + begin + status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i}; + end + else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read) + begin + status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg}; + end + else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm) + begin + status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg}; + end + else if (shift_dr_i && (!status_cnt_end)) + begin + status <= #1 {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]}; + end +end +// Following status is shifted out (MSB first): +// 3. bit: 1 if crc is OK, else 0 +// 2. bit: 1'b0 +// 1. bit: 1 if WB error occured, else 0 +// 0. bit: 1 if overrun occured during write (data couldn't be written fast enough) +// or underrun occured during read (data couldn't be read fast enough) + + +endmodule +

verilog/dbg_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/dbg_top.v =================================================================== --- verilog/dbg_top.v (nonexistent) +++ verilog/dbg_top.v (revision 158) @@ -0,0 +1,798 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_top.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.44 2004/03/28 20:27:02 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.43 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.42 2004/01/30 10:24:31 mohor +// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are +// turned on. +// +// Revision 1.41 2004/01/25 14:04:18 mohor +// All flipflops are reset. +// +// Revision 1.40 2004/01/20 14:23:47 mohor +// Define name changed. +// +// Revision 1.39 2004/01/19 07:32:41 simons +// Reset values width added because of FV, a good sentence changed because some tools can not handle it. +// +// Revision 1.38 2004/01/18 09:22:47 simons +// Sensitivity list updated. +// +// Revision 1.37 2004/01/17 17:01:14 mohor +// Almost finished. +// +// Revision 1.36 2004/01/16 14:51:33 mohor +// cpu registers added. +// +// Revision 1.35 2004/01/14 22:59:16 mohor +// Temp version. +// +// Revision 1.34 2003/12/23 15:07:34 mohor +// New directory structure. New version of the debug interface. +// Files that are not needed removed. +// +// Revision 1.33 2003/10/23 16:17:01 mohor +// CRC logic changed. +// +// Revision 1.32 2003/09/18 14:00:47 simons +// Lower two address lines must be always zero. +// +// Revision 1.31 2003/09/17 14:38:57 simons +// WB_CNTL register added, some syncronization fixes. +// +// Revision 1.30 2003/08/28 13:55:22 simons +// Three more chains added for cpu debug access. +// +// Revision 1.29 2003/07/31 12:19:49 simons +// Multiple cpu support added. +// +// Revision 1.28 2002/11/06 14:22:41 mohor +// Trst signal is not inverted here any more. Inverted on higher layer !!!. +// +// Revision 1.27 2002/10/10 02:42:55 mohor +// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). +// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, +// wb_cyc_o is negated. +// +// Revision 1.26 2002/05/07 14:43:59 mohor +// mon_cntl_o signals that controls monitor mux added. +// +// Revision 1.25 2002/04/22 12:54:11 mohor +// Signal names changed to lower case. +// +// Revision 1.24 2002/04/17 13:17:01 mohor +// Intentional error removed. +// +// Revision 1.23 2002/04/17 11:16:33 mohor +// A block for checking possible simulation/synthesis missmatch added. +// +// Revision 1.22 2002/03/12 10:31:53 mohor +// tap_top and dbg_top modules are put into two separate modules. tap_top +// contains only tap state machine and related logic. dbg_top contains all +// logic necessery for debugging. +// +// Revision 1.21 2002/03/08 15:28:16 mohor +// Structure changed. Hooks for jtag chain added. +// +// Revision 1.20 2002/02/06 12:23:09 mohor +// latched_jtag_ir used when muxing TDO instead of JTAG_IR. +// +// Revision 1.19 2002/02/05 13:34:51 mohor +// Stupid bug that was entered by previous update fixed. +// +// Revision 1.18 2002/02/05 12:41:01 mohor +// trst synchronization is not needed and was removed. +// +// Revision 1.17 2002/01/25 07:58:35 mohor +// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in +// not filled-in. Tested in hw. +// +// Revision 1.16 2001/12/20 11:17:26 mohor +// TDO and TDO Enable signal are separated into two signals. +// +// Revision 1.15 2001/12/05 13:28:21 mohor +// trst signal is synchronized to wb_clk_i. +// +// Revision 1.14 2001/11/28 09:36:15 mohor +// Register length fixed. +// +// Revision 1.13 2001/11/27 13:37:43 mohor +// CRC is returned when chain selection data is transmitted. +// +// Revision 1.12 2001/11/26 10:47:09 mohor +// Crc generation is different for read or write commands. Small synthesys fixes. +// +// Revision 1.11 2001/11/14 10:10:41 mohor +// Wishbone data latched on wb_clk_i instead of risc_clk. +// +// Revision 1.10 2001/11/12 01:11:27 mohor +// Reset signals are not combined any more. +// +// Revision 1.9 2001/10/19 11:40:01 mohor +// dbg_timescale.v changed to timescale.v This is done for the simulation of +// few different cores in a single project. +// +// Revision 1.8 2001/10/17 10:39:03 mohor +// bs_chain_o added. +// +// Revision 1.7 2001/10/16 10:09:56 mohor +// Signal names changed to lowercase. +// +// +// Revision 1.6 2001/10/15 09:55:47 mohor +// Wishbone interface added, few fixes for better performance, +// hooks for boundary scan testing added. +// +// Revision 1.5 2001/09/24 14:06:42 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.4 2001/09/20 10:11:25 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.3 2001/09/19 11:55:13 mohor +// Asynchronous set/reset not used in trace any more. +// +// Revision 1.2 2001/09/18 14:13:47 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:00 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:02 mohor +// Initial release +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_defines.v" +`include "dbg_cpu_defines.v" + +// Top module +module dbg_top( + // JTAG signals + tck_i, + tdi_i, + tdo_o, + rst_i, + + // TAP states + shift_dr_i, + pause_dr_i, + update_dr_i, + + // Instructions + debug_select_i + + + `ifdef DBG_WISHBONE_SUPPORTED + // WISHBONE common signals + , + wb_clk_i, + + // WISHBONE master interface + wb_adr_o, + wb_dat_o, + wb_dat_i, + wb_cyc_o, + wb_stb_o, + wb_sel_o, + wb_we_o, + wb_ack_i, + wb_cab_o, + wb_err_i, + wb_cti_o, + wb_bte_o + `endif + + `ifdef DBG_CPU0_SUPPORTED + // CPU signals + , + cpu0_clk_i, + cpu0_addr_o, + cpu0_data_i, + cpu0_data_o, + cpu0_bp_i, + cpu0_stall_o, + cpu0_stb_o, + cpu0_we_o, + cpu0_ack_i, + cpu0_rst_o + `endif + + `ifdef DBG_CPU1_SUPPORTED + // CPU signals + , + cpu1_clk_i, + cpu1_addr_o, + cpu1_data_i, + cpu1_data_o, + cpu1_bp_i, + cpu1_stall_o, + cpu1_stb_o, + cpu1_we_o, + cpu1_ack_i, + cpu1_rst_o + `endif + + ); + + +// JTAG signals +input tck_i; +input tdi_i; +output tdo_o; +input rst_i; + +// TAP states +input shift_dr_i; +input pause_dr_i; +input update_dr_i; + +// Instructions +input debug_select_i; + +`ifdef DBG_WISHBONE_SUPPORTED +input wb_clk_i; +output [31:0] wb_adr_o; +output [31:0] wb_dat_o; +input [31:0] wb_dat_i; +output wb_cyc_o; +output wb_stb_o; +output [3:0] wb_sel_o; +output wb_we_o; +input wb_ack_i; +output wb_cab_o; +input wb_err_i; +output [2:0] wb_cti_o; +output [1:0] wb_bte_o; + +reg wishbone_module; +reg wishbone_ce; +wire tdi_wb; +wire tdo_wb; +wire crc_en_wb; +wire shift_crc_wb; +`else +wire crc_en_wb = 1'b0; +wire shift_crc_wb = 1'b0; +`endif + +`ifdef DBG_CPU0_SUPPORTED +// CPU signals +input cpu0_clk_i; +output [31:0] cpu0_addr_o; +input [31:0] cpu0_data_i; +output [31:0] cpu0_data_o; +input cpu0_bp_i; +output cpu0_stall_o; +output cpu0_stb_o; +output cpu0_we_o; +input cpu0_ack_i; +output cpu0_rst_o; + +reg cpu0_debug_module; +reg cpu0_ce; +wire cpu0_tdi; +wire cpu0_tdo; +wire cpu0_crc_en; +wire cpu0_shift_crc; +`else +wire cpu0_crc_en = 1'b0; +wire cpu0_shift_crc = 1'b0; +`endif + +`ifdef DBG_CPU1_SUPPORTED +input cpu1_clk_i; +output [31:0] cpu1_addr_o; +input [31:0] cpu1_data_i; +output [31:0] cpu1_data_o; +input cpu1_bp_i; +output cpu1_stall_o; +output cpu1_stb_o; +output cpu1_we_o; +input cpu1_ack_i; +output cpu1_rst_o; + +reg cpu1_debug_module; +reg cpu1_ce; +wire cpu1_tdi; +wire cpu1_tdo; +wire cpu1_crc_en; +wire cpu1_shift_crc; +`else +wire cpu1_crc_en = 1'b0; +wire cpu1_shift_crc = 1'b0; +`endif + + +reg [`DBG_TOP_DATA_CNT -1:0] data_cnt; +reg [`DBG_TOP_CRC_CNT -1:0] crc_cnt; +reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0] status_cnt; +reg [`DBG_TOP_MODULE_DATA_LEN -1:0] module_dr; +reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id; + +wire module_latch_en; +wire data_cnt_end; +wire crc_cnt_end; +wire status_cnt_end; +reg crc_cnt_end_q; +reg module_select; +reg module_select_error; +wire crc_out; +wire crc_match; + +wire data_shift_en; +wire selecting_command; + +reg tdo_o; + + + + +wire shift_crc; + +// data counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}}; + else if(shift_dr_i & (~data_cnt_end)) + data_cnt <= #1 data_cnt + 1'b1; + else if (update_dr_i) + data_cnt <= #1 {`DBG_TOP_DATA_CNT{1'b0}}; +end + + +assign data_cnt_end = data_cnt == `DBG_TOP_MODULE_DATA_LEN; + + +// crc counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}}; + else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select) + crc_cnt <= #1 crc_cnt + 1'b1; + else if (update_dr_i) + crc_cnt <= #1 {`DBG_TOP_CRC_CNT{1'b0}}; +end + +assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN; + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_cnt_end_q <= #1 1'b0; + else + crc_cnt_end_q <= #1 crc_cnt_end; +end + + +// status counter +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}}; + else if(shift_dr_i & crc_cnt_end & (~status_cnt_end)) + status_cnt <= #1 status_cnt + 1'b1; + else if (update_dr_i) + status_cnt <= #1 {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}}; +end + +assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN; + + +assign selecting_command = shift_dr_i & (data_cnt == `DBG_TOP_DATA_CNT'h0) & debug_select_i; + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + module_select <= #1 1'b0; + else if(selecting_command & tdi_i) // Chain select + module_select <= #1 1'b1; + else if (update_dr_i) + module_select <= #1 1'b0; +end + + +always @ (module_id) +begin + `ifdef DBG_CPU0_SUPPORTED + cpu0_debug_module <= #1 1'b0; + `endif + `ifdef DBG_CPU1_SUPPORTED + cpu1_debug_module <= #1 1'b0; + `endif + `ifdef DBG_WISHBONE_SUPPORTED + wishbone_module <= #1 1'b0; + `endif + module_select_error <= #1 1'b0; + + case (module_id) /* synthesis parallel_case */ + `ifdef DBG_CPU0_SUPPORTED + `DBG_TOP_CPU0_DEBUG_MODULE : cpu0_debug_module <= #1 1'b1; + `endif + `ifdef DBG_CPU1_SUPPORTED + `DBG_TOP_CPU1_DEBUG_MODULE : cpu1_debug_module <= #1 1'b1; + `endif + `ifdef DBG_WISHBONE_SUPPORTED + `DBG_TOP_WISHBONE_DEBUG_MODULE : wishbone_module <= #1 1'b1; + `endif + default : module_select_error <= #1 1'b1; + endcase +end + + +assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q); + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + module_id <= {`DBG_TOP_MODULE_ID_LENGTH{1'b1}}; + else if(module_latch_en & crc_match) + module_id <= #1 module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0]; +end + + +assign data_shift_en = shift_dr_i & (~data_cnt_end); + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + module_dr <= #1 `DBG_TOP_MODULE_DATA_LEN'h0; + else if (data_shift_en) + module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= #1 {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i}; +end + + +// Calculating crc for input data +dbg_crc32_d1 i_dbg_crc32_d1_in + ( + .data (tdi_i), + .enable (shift_dr_i), + .shift (1'b0), + .rst (rst_i), + .sync_rst (update_dr_i), + .crc_out (), + .clk (tck_i), + .crc_match (crc_match) + ); + + +reg tdo_module_select; +wire crc_en; +wire crc_en_dbg; +reg crc_started; + +assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en; + +assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end); + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + crc_started <= #1 1'b0; + else if (crc_en) + crc_started <= #1 1'b1; + else if (update_dr_i) + crc_started <= #1 1'b0; +end + + +reg tdo_tmp; + + +// Calculating crc for input data +dbg_crc32_d1 i_dbg_crc32_d1_out + ( + .data (tdo_tmp), + .enable (crc_en), // enable has priority +// .shift (1'b0), + .shift (shift_dr_i & crc_started & (~crc_en)), + .rst (rst_i), + .sync_rst (update_dr_i), + .crc_out (crc_out), + .clk (tck_i), + .crc_match () + ); + +// Following status is shifted out: +// 1. bit: 0 if crc is OK, else 1 +// 2. bit: 0 if existing module_id is selected, 1 if non-existing module_id is selected +// 3. bit: 0 (always) +// 4. bit: 0 (always) + + +always @ (status_cnt or crc_match or module_select_error or crc_out) +begin + case (status_cnt) /* synthesis full_case parallel_case */ + `DBG_TOP_STATUS_CNT_WIDTH'd0 : begin + tdo_module_select = ~crc_match; + end + `DBG_TOP_STATUS_CNT_WIDTH'd1 : begin + tdo_module_select = module_select_error; + end + `DBG_TOP_STATUS_CNT_WIDTH'd2 : begin + tdo_module_select = 1'b0; + end + `DBG_TOP_STATUS_CNT_WIDTH'd3 : begin + tdo_module_select = 1'b0; + end + `DBG_TOP_STATUS_CNT_WIDTH'd4 : begin + tdo_module_select = crc_out; + end + endcase +end + + + + +assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc; + +always @ (shift_crc or crc_out or tdo_module_select +`ifdef DBG_WISHBONE_SUPPORTED + or wishbone_ce or tdo_wb +`endif +`ifdef DBG_CPU0_SUPPORTED + or cpu0_ce or cpu0_tdo +`endif +`ifdef DBG_CPU1_SUPPORTED + or cpu1_ce or cpu1_tdo +`endif + ) +begin + if (shift_crc) // shifting crc + tdo_tmp = crc_out; + `ifdef DBG_WISHBONE_SUPPORTED + else if (wishbone_ce) // shifting data from wb + tdo_tmp = tdo_wb; + `endif + `ifdef DBG_CPU0_SUPPORTED + else if (cpu0_ce) // shifting data from cpu + tdo_tmp = cpu0_tdo; + `endif + `ifdef DBG_CPU1_SUPPORTED + else if (cpu1_ce) // shifting data from cpu + tdo_tmp = cpu1_tdo; + `endif + else + tdo_tmp = tdo_module_select; +end + + +always @ (negedge tck_i) +begin + tdo_o <= #1 tdo_tmp; +end + + + + +// Signals for WISHBONE module + + +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + `ifdef DBG_WISHBONE_SUPPORTED + wishbone_ce <= #1 1'b0; + `endif + `ifdef DBG_CPU0_SUPPORTED + cpu0_ce <= #1 1'b0; + `endif + `ifdef DBG_CPU1_SUPPORTED + cpu1_ce <= #1 1'b0; + `endif + end + else if(selecting_command & (~tdi_i)) + begin + `ifdef DBG_WISHBONE_SUPPORTED + if (wishbone_module) // wishbone CE + wishbone_ce <= #1 1'b1; + `endif + `ifdef DBG_CPU0_SUPPORTED + if (cpu0_debug_module) // CPU CE + cpu0_ce <= #1 1'b1; + `endif + `ifdef DBG_CPU1_SUPPORTED + if (cpu1_debug_module) // CPU CE + cpu1_ce <= #1 1'b1; + `endif + end + else if (update_dr_i) + begin + `ifdef DBG_WISHBONE_SUPPORTED + wishbone_ce <= #1 1'b0; + `endif + `ifdef DBG_CPU0_SUPPORTED + cpu0_ce <= #1 1'b0; + `endif + `ifdef DBG_CPU1_SUPPORTED + cpu1_ce <= #1 1'b0; + `endif + end +end + + +`ifdef DBG_WISHBONE_SUPPORTED +assign tdi_wb = wishbone_ce & tdi_i; +`endif + +`ifdef DBG_CPU0_SUPPORTED +assign cpu0_tdi = cpu0_ce & tdi_i; +`endif +`ifdef DBG_CPU1_SUPPORTED +assign cpu1_tdi = cpu1_ce & tdi_i; +`endif + + +`ifdef DBG_WISHBONE_SUPPORTED +// Connecting wishbone module +dbg_wb i_dbg_wb ( + // JTAG signals + .tck_i (tck_i), + .tdi_i (tdi_wb), + .tdo_o (tdo_wb), + + // TAP states + .shift_dr_i (shift_dr_i), + .pause_dr_i (pause_dr_i), + .update_dr_i (update_dr_i), + + .wishbone_ce_i (wishbone_ce), + .crc_match_i (crc_match), + .crc_en_o (crc_en_wb), + .shift_crc_o (shift_crc_wb), + .rst_i (rst_i), + + // WISHBONE common signals + .wb_clk_i (wb_clk_i), + + // WISHBONE master interface + .wb_adr_o (wb_adr_o), + .wb_dat_o (wb_dat_o), + .wb_dat_i (wb_dat_i), + .wb_cyc_o (wb_cyc_o), + .wb_stb_o (wb_stb_o), + .wb_sel_o (wb_sel_o), + .wb_we_o (wb_we_o), + .wb_ack_i (wb_ack_i), + .wb_cab_o (wb_cab_o), + .wb_err_i (wb_err_i), + .wb_cti_o (wb_cti_o), + .wb_bte_o (wb_bte_o) + ); +`endif + + + +`ifdef DBG_CPU0_SUPPORTED +dbg_cpu i_dbg_cpu_or1k ( + // JTAG signals + .tck_i (tck_i), + .tdi_i (cpu0_tdi), + .tdo_o (cpu0_tdo), + + // TAP states + .shift_dr_i (shift_dr_i), + .pause_dr_i (pause_dr_i), + .update_dr_i (update_dr_i), + + .cpu_ce_i (cpu0_ce), + .crc_match_i (crc_match), + .crc_en_o (cpu0_crc_en), + .shift_crc_o (cpu0_shift_crc), + .rst_i (rst_i), + + // CPU signals + .cpu_clk_i (cpu0_clk_i), + .cpu_addr_o (cpu0_addr_o), + .cpu_data_i (cpu0_data_i), + .cpu_data_o (cpu0_data_o), + .cpu_bp_i (cpu0_bp_i), + .cpu_stall_o (cpu0_stall_o), + .cpu_stb_o (cpu0_stb_o), + .cpu_we_o (cpu0_we_o), + .cpu_ack_i (cpu0_ack_i), + .cpu_rst_o (cpu0_rst_o) + ); + +`endif // DBG_CPU0_SUPPORTED + + + +`ifdef DBG_CPU1_SUPPORTED +// Connecting cpu module +dbg_cpu i_dbg_cpu_8051 ( + // JTAG signals + .tck_i (tck_i), + .tdi_i (cpu1_tdi), + .tdo_o (cpu1_tdo), + + // TAP states + .shift_dr_i (shift_dr_i), + .pause_dr_i (pause_dr_i), + .update_dr_i (update_dr_i), + + .cpu_ce_i (cpu1_ce), + .crc_match_i (crc_match), + .crc_en_o (cpu1_crc_en), + .shift_crc_o (cpu1_shift_crc), + .rst_i (rst_i), + + // CPU signals + .cpu_clk_i (cpu1_clk_i), + .cpu_addr_o (cpu1_addr_o), + .cpu_data_i (cpu1_data_i), + .cpu_data_o (cpu1_data_o), + .cpu_bp_i (cpu1_bp_i), + .cpu_stall_o (cpu1_stall_o), + .cpu_stb_o (cpu1_stb_o), + .cpu_we_o (cpu1_we_o), + .cpu_ack_i (cpu1_ack_i), + .cpu_rst_o (cpu1_rst_o) + ); +`endif + + +endmodule Index: verilog/dbg_defines.v =================================================================== --- verilog/dbg_defines.v (nonexistent) +++ verilog/dbg_defines.v (revision 158) @@ -0,0 +1,150 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.19 2004/03/28 20:27:02 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.18 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.17 2004/01/30 10:24:30 mohor +// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are +// turned on. +// +// Revision 1.16 2004/01/20 14:23:45 mohor +// Define name changed. +// +// Revision 1.15 2003/12/23 15:07:34 mohor +// New directory structure. New version of the debug interface. +// Files that are not needed removed. +// +// Revision 1.14 2003/10/23 16:17:00 mohor +// CRC logic changed. +// +// Revision 1.13 2003/10/21 09:48:31 simons +// Mbist support added. +// +// Revision 1.12 2003/09/17 14:38:57 simons +// WB_CNTL register added, some syncronization fixes. +// +// Revision 1.11 2003/08/28 13:55:21 simons +// Three more chains added for cpu debug access. +// +// Revision 1.10 2003/07/31 12:19:49 simons +// Multiple cpu support added. +// +// Revision 1.9 2002/05/07 14:43:59 mohor +// mon_cntl_o signals that controls monitor mux added. +// +// Revision 1.8 2002/01/25 07:58:34 mohor +// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in +// not filled-in. Tested in hw. +// +// Revision 1.7 2001/12/06 10:08:06 mohor +// Warnings from synthesys tools fixed. +// +// Revision 1.6 2001/11/28 09:38:30 mohor +// Trace disabled by default. +// +// Revision 1.5 2001/10/15 09:55:47 mohor +// Wishbone interface added, few fixes for better performance, +// hooks for boundary scan testing added. +// +// Revision 1.4 2001/09/24 14:06:42 mohor +// Changes connected to the OpenRISC access (SPR read, SPR write). +// +// Revision 1.3 2001/09/20 10:11:25 mohor +// Working version. Few bugs fixed, comments added. +// +// Revision 1.2 2001/09/18 14:13:47 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:00 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:08 mohor +// Initial release +// +// + + +// Length of the MODULE ID register +`define DBG_TOP_MODULE_ID_LENGTH 4 + +// Length of data +`define DBG_TOP_MODULE_DATA_LEN `DBG_TOP_MODULE_ID_LENGTH + 1 +`define DBG_TOP_DATA_CNT 3 + +// Length of status +`define DBG_TOP_STATUS_LEN 3'd4 +`define DBG_TOP_STATUS_CNT_WIDTH 3 + +// Length of the CRC +`define DBG_TOP_CRC_LEN 32 +`define DBG_TOP_CRC_CNT 6 + +// Chains +`define DBG_TOP_WISHBONE_DEBUG_MODULE 4'h0 +`define DBG_TOP_CPU0_DEBUG_MODULE 4'h1 +`define DBG_TOP_CPU1_DEBUG_MODULE 4'h2 + +// If WISHBONE sub-module is supported uncomment the folowing line +`define DBG_WISHBONE_SUPPORTED + +// If CPU_0 sub-module is supported uncomment the folowing line +`define DBG_CPU0_SUPPORTED + +// If CPU_1 sub-module is supported uncomment the folowing line +`define DBG_CPU1_SUPPORTED + +// If more debug info is needed, uncomment the follofing line +//`define DBG_MORE_INFO + Index: verilog/dbg_wb_defines.v =================================================================== --- verilog/dbg_wb_defines.v (nonexistent) +++ verilog/dbg_wb_defines.v (revision 158) @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_wb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.6 2004/03/28 20:27:02 igorm +// New release of the debug interface (3rd. release). +// +// Revision 1.5 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.4 2004/01/16 14:51:33 mohor +// cpu registers added. +// +// Revision 1.3 2004/01/08 17:53:36 mohor +// tmp version. +// +// Revision 1.2 2004/01/06 17:15:19 mohor +// temp3 version. +// +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// + +// Defining length of the command +`define DBG_WB_CMD_LEN 3'd4 +`define DBG_WB_CMD_CNT_WIDTH 3 + +// Defining length of the access_type field +`define DBG_WB_ACC_TYPE_LEN 3'd4 + +// Defining length of the address +`define DBG_WB_ADR_LEN 6'd32 + +// Defining length of the length register +`define DBG_WB_LEN_LEN 5'd16 + +// Defining total length of the DR needed +`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN) + +// Defining length of the CRC +`define DBG_WB_CRC_LEN 6'd32 +`define DBG_WB_CRC_CNT_WIDTH 6 + +// Defining length of status +`define DBG_WB_STATUS_LEN 3'd4 +`define DBG_WB_STATUS_CNT_WIDTH 3 + +// Defining length of the data +`define DBG_WB_DATA_CNT_WIDTH (`DBG_WB_LEN_LEN + 3) +`define DBG_WB_DATA_CNT_LIM_WIDTH `DBG_WB_LEN_LEN + +//Defining commands +`define DBG_WB_GO 4'h0 +`define DBG_WB_RD_COMM 4'h1 +`define DBG_WB_WR_COMM 4'h2 + +// Defining access types for wishbone +`define DBG_WB_WRITE8 4'h0 +`define DBG_WB_WRITE16 4'h1 +`define DBG_WB_WRITE32 4'h2 +`define DBG_WB_READ8 4'h4 +`define DBG_WB_READ16 4'h5 +`define DBG_WB_READ32 4'h6 + +

verilog/dbg_wb_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/dbg_crc32_d1.v =================================================================== --- verilog/dbg_crc32_d1.v (nonexistent) +++ verilog/dbg_crc32_d1.v (revision 158) @@ -0,0 +1,148 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_crc32_d1.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// File: CRC32_D1.v +// Date: Thu Nov 27 13:56:49 2003 +// +// Copyright (C) 1999-2003 Easics NV. +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +// +// Purpose: Verilog module containing a synthesizable CRC function +// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32) +// * data width: 1 +// +// Info: janz@easics.be (Jan Zegers) +// http://www.easics.com +/////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2003/12/23 15:26:26 mohor +// Small fix. +// +// Revision 1.1 2003/12/23 15:09:04 mohor +// New directory structure. New version of the debug interface. +// +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match); + +input data; +input enable; +input shift; +input rst; +input sync_rst; +input clk; + + +output crc_out; +output crc_match; + +reg [31:0] crc; + +wire [31:0] new_crc; + + +assign new_crc[0] = data ^ crc[31]; +assign new_crc[1] = data ^ crc[0] ^ crc[31]; +assign new_crc[2] = data ^ crc[1] ^ crc[31]; +assign new_crc[3] = crc[2]; +assign new_crc[4] = data ^ crc[3] ^ crc[31]; +assign new_crc[5] = data ^ crc[4] ^ crc[31]; +assign new_crc[6] = crc[5]; +assign new_crc[7] = data ^ crc[6] ^ crc[31]; +assign new_crc[8] = data ^ crc[7] ^ crc[31]; +assign new_crc[9] = crc[8]; +assign new_crc[10] = data ^ crc[9] ^ crc[31]; +assign new_crc[11] = data ^ crc[10] ^ crc[31]; +assign new_crc[12] = data ^ crc[11] ^ crc[31]; +assign new_crc[13] = crc[12]; +assign new_crc[14] = crc[13]; +assign new_crc[15] = crc[14]; +assign new_crc[16] = data ^ crc[15] ^ crc[31]; +assign new_crc[17] = crc[16]; +assign new_crc[18] = crc[17]; +assign new_crc[19] = crc[18]; +assign new_crc[20] = crc[19]; +assign new_crc[21] = crc[20]; +assign new_crc[22] = data ^ crc[21] ^ crc[31]; +assign new_crc[23] = data ^ crc[22] ^ crc[31]; +assign new_crc[24] = crc[23]; +assign new_crc[25] = crc[24]; +assign new_crc[26] = data ^ crc[25] ^ crc[31]; +assign new_crc[27] = crc[26]; +assign new_crc[28] = crc[27]; +assign new_crc[29] = crc[28]; +assign new_crc[30] = crc[29]; +assign new_crc[31] = crc[30]; + + +always @ (posedge clk or posedge rst) +begin + if(rst) + crc[31:0] <= #1 32'hffffffff; + else if(sync_rst) + crc[31:0] <= #1 32'hffffffff; + else if(enable) + crc[31:0] <= #1 new_crc; + else if (shift) + crc[31:0] <= #1 {crc[30:0], 1'b0}; +end + + +assign crc_match = (crc == 32'h0); +assign crc_out = crc[31]; + +endmodule

verilog/dbg_crc32_d1.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/dbg_register.v =================================================================== --- verilog/dbg_register.v (nonexistent) +++ verilog/dbg_register.v (revision 158) @@ -0,0 +1,92 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_register.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.9 2004/01/25 14:04:18 mohor +// All flipflops are reset. +// +// Revision 1.8 2004/01/16 14:53:33 mohor +// *** empty log message *** +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +module dbg_register ( + data_in, + data_out, + write, + clk, + reset + ); + + +parameter WIDTH = 8; // default parameter of the register width +parameter RESET_VALUE = 0; + + +input [WIDTH-1:0] data_in; +input write; +input clk; +input reset; + +output [WIDTH-1:0] data_out; +reg [WIDTH-1:0] data_out; + + + +always @ (posedge clk or posedge reset) +begin + if(reset) + data_out[WIDTH-1:0] <= #1 RESET_VALUE; + else if(write) + data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0]; +end + + +endmodule // Register + Index: verilog/dbg_cpu_registers.v =================================================================== --- verilog/dbg_cpu_registers.v (nonexistent) +++ verilog/dbg_cpu_registers.v (revision 158) @@ -0,0 +1,193 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_cpu_registers.v //// +//// //// +//// //// +//// This file is part of the SoC Debug Interface. //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2004 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.5 2004/03/22 16:35:46 igorm +// Temp version before changing dbg interface. +// +// Revision 1.4 2004/01/25 14:04:18 mohor +// All flipflops are reset. +// +// Revision 1.3 2004/01/22 10:16:08 mohor +// cpu_stall_o activated as soon as bp occurs. +// +// Revision 1.2 2004/01/17 17:01:14 mohor +// Almost finished. +// +// Revision 1.1 2004/01/16 14:53:33 mohor +// *** empty log message *** +// +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "dbg_cpu_defines.v" + +module dbg_cpu_registers ( + data_i, + we_i, + tck_i, + bp_i, + rst_i, + cpu_clk_i, + ctrl_reg_o, + cpu_stall_o, + cpu_rst_o + ); + + +input [`DBG_CPU_CTRL_LEN -1:0] data_i; +input we_i; +input tck_i; +input bp_i; +input rst_i; +input cpu_clk_i; + +output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o; +output cpu_stall_o; +output cpu_rst_o; + +reg cpu_reset; +wire [2:1] cpu_op_out; + +reg stall_bp, stall_bp_csff, stall_bp_tck; +reg stall_reg, stall_reg_csff, stall_reg_cpu; +reg cpu_reset_csff; +reg cpu_rst_o; + + + +// Breakpoint is latched and synchronized. Stall is set and latched. +always @ (posedge cpu_clk_i or posedge rst_i) +begin + if(rst_i) + stall_bp <= #1 1'b0; + else if(bp_i) + stall_bp <= #1 1'b1; + else if(stall_reg_cpu) + stall_bp <= #1 1'b0; +end + + +// Synchronizing +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + begin + stall_bp_csff <= #1 1'b0; + stall_bp_tck <= #1 1'b0; + end + else + begin + stall_bp_csff <= #1 stall_bp; + stall_bp_tck <= #1 stall_bp_csff; + end +end + + +always @ (posedge cpu_clk_i or posedge rst_i) +begin + if (rst_i) + begin + stall_reg_csff <= #1 1'b0; + stall_reg_cpu <= #1 1'b0; + end + else + begin + stall_reg_csff <= #1 stall_reg; + stall_reg_cpu <= #1 stall_reg_csff; + end +end + + +assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu; + + +// Writing data to the control registers (stall) +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + stall_reg <= #1 1'b0; + else if (stall_bp_tck) + stall_reg <= #1 1'b1; + else if (we_i) + stall_reg <= #1 data_i[0]; +end + + +// Writing data to the control registers (reset) +always @ (posedge tck_i or posedge rst_i) +begin + if (rst_i) + cpu_reset <= #1 1'b0; + else if(we_i) + cpu_reset <= #1 data_i[1]; +end + + +// Synchronizing signals from registers +always @ (posedge cpu_clk_i or posedge rst_i) +begin + if (rst_i) + begin + cpu_reset_csff <= #1 1'b0; + cpu_rst_o <= #1 1'b0; + end + else + begin + cpu_reset_csff <= #1 cpu_reset; + cpu_rst_o <= #1 cpu_reset_csff; + end +end + + + +// Value for read back +assign ctrl_reg_o = {cpu_reset, stall_reg}; + + +endmodule + Index: README.txt =================================================================== --- README.txt (nonexistent) +++ README.txt (revision 158) @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// README.txt //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/cores/DebugInterface/ //// +//// //// +//// //// +//// Author(s): //// +//// Igor Mohor //// +//// igorm@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in this README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000,2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.2 2001/06/01 22:22:35 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.1 2001/05/18 13:12:09 mohor +// Header changed. All additional information is now avaliable in this README.txt file. +// +// + + + +PROJECT: +SoC/OpenRISC Development (debug) Interface + + +PROJECT AND DOCUMENTATION ON THE WEB: + +The project that this files are part of is avaliable on the opencores +web page: + +http://www.opencores.org/cores/DebugInterface/ + +Documentation can also be found there. For direct download of the +documentation go to: + +http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf + + + + +OVERVIEW (main Features): + +Development Interface is used for development purposes +(Boundary Scan testing and debugging). It is an interface +between the RISC, peripheral cores and any commercial +debugger/emulator or BS testing device. The external +debugger or BS tester connects to the core via JTAG port. +The Development Port also contains a trace and support for +tracing the program flow, execution coverage and profiling +the code. + +dbg_tb.v is a testbench file. +file_communication.v is used for simulating the whole design together with the + debugger through two files that make a JTAG interface +dbg_top.v is top level module of the development interface design + + + +COMPATIBILITY: + +- WISHBONE rev B.1 +- IEEE 1149.1 (JTAG) + + + +KNOWN PROBLEMS (limits): +- RISC changes Watchpoints and breakpoints on rising edge of the +Mclk clock signal. Simulation should do the same. + + + +TO DO: +- Add a WISHBONE master support if needed +- Add support for boundary scan (This is already done, but not yet incorporated in the design) +