URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/dbg_interface/tags/highland_ver1/rtl
- from Rev 133 to Rev 158
- ↔ Reverse comparison
Rev 133 → Rev 158
/verilog/dbg_top.v
0,0 → 1,701
////////////////////////////////////////////////////////////////////// |
//// //// |
//// dbg_top.v //// |
//// //// |
//// //// |
//// This file is part of the SoC/OpenRISC Development Interface //// |
//// http://www.opencores.org/projects/DebugInterface/ //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2003 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.41 2004/01/25 14:04:18 mohor |
// All flipflops are reset. |
// |
// Revision 1.40 2004/01/20 14:23:47 mohor |
// Define name changed. |
// |
// Revision 1.39 2004/01/19 07:32:41 simons |
// Reset values width added because of FV, a good sentence changed because some tools can not handle it. |
// |
// Revision 1.38 2004/01/18 09:22:47 simons |
// Sensitivity list updated. |
// |
// Revision 1.37 2004/01/17 17:01:14 mohor |
// Almost finished. |
// |
// Revision 1.36 2004/01/16 14:51:33 mohor |
// cpu registers added. |
// |
// Revision 1.35 2004/01/14 22:59:16 mohor |
// Temp version. |
// |
// Revision 1.34 2003/12/23 15:07:34 mohor |
// New directory structure. New version of the debug interface. |
// Files that are not needed removed. |
// |
// Revision 1.33 2003/10/23 16:17:01 mohor |
// CRC logic changed. |
// |
// Revision 1.32 2003/09/18 14:00:47 simons |
// Lower two address lines must be always zero. |
// |
// Revision 1.31 2003/09/17 14:38:57 simons |
// WB_CNTL register added, some syncronization fixes. |
// |
// Revision 1.30 2003/08/28 13:55:22 simons |
// Three more chains added for cpu debug access. |
// |
// Revision 1.29 2003/07/31 12:19:49 simons |
// Multiple cpu support added. |
// |
// Revision 1.28 2002/11/06 14:22:41 mohor |
// Trst signal is not inverted here any more. Inverted on higher layer !!!. |
// |
// Revision 1.27 2002/10/10 02:42:55 mohor |
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). |
// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, |
// wb_cyc_o is negated. |
// |
// Revision 1.26 2002/05/07 14:43:59 mohor |
// mon_cntl_o signals that controls monitor mux added. |
// |
// Revision 1.25 2002/04/22 12:54:11 mohor |
// Signal names changed to lower case. |
// |
// Revision 1.24 2002/04/17 13:17:01 mohor |
// Intentional error removed. |
// |
// Revision 1.23 2002/04/17 11:16:33 mohor |
// A block for checking possible simulation/synthesis missmatch added. |
// |
// Revision 1.22 2002/03/12 10:31:53 mohor |
// tap_top and dbg_top modules are put into two separate modules. tap_top |
// contains only tap state machine and related logic. dbg_top contains all |
// logic necessery for debugging. |
// |
// Revision 1.21 2002/03/08 15:28:16 mohor |
// Structure changed. Hooks for jtag chain added. |
// |
// Revision 1.20 2002/02/06 12:23:09 mohor |
// latched_jtag_ir used when muxing TDO instead of JTAG_IR. |
// |
// Revision 1.19 2002/02/05 13:34:51 mohor |
// Stupid bug that was entered by previous update fixed. |
// |
// Revision 1.18 2002/02/05 12:41:01 mohor |
// trst synchronization is not needed and was removed. |
// |
// Revision 1.17 2002/01/25 07:58:35 mohor |
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in |
// not filled-in. Tested in hw. |
// |
// Revision 1.16 2001/12/20 11:17:26 mohor |
// TDO and TDO Enable signal are separated into two signals. |
// |
// Revision 1.15 2001/12/05 13:28:21 mohor |
// trst signal is synchronized to wb_clk_i. |
// |
// Revision 1.14 2001/11/28 09:36:15 mohor |
// Register length fixed. |
// |
// Revision 1.13 2001/11/27 13:37:43 mohor |
// CRC is returned when chain selection data is transmitted. |
// |
// Revision 1.12 2001/11/26 10:47:09 mohor |
// Crc generation is different for read or write commands. Small synthesys fixes. |
// |
// Revision 1.11 2001/11/14 10:10:41 mohor |
// Wishbone data latched on wb_clk_i instead of risc_clk. |
// |
// Revision 1.10 2001/11/12 01:11:27 mohor |
// Reset signals are not combined any more. |
// |
// Revision 1.9 2001/10/19 11:40:01 mohor |
// dbg_timescale.v changed to timescale.v This is done for the simulation of |
// few different cores in a single project. |
// |
// Revision 1.8 2001/10/17 10:39:03 mohor |
// bs_chain_o added. |
// |
// Revision 1.7 2001/10/16 10:09:56 mohor |
// Signal names changed to lowercase. |
// |
// |
// Revision 1.6 2001/10/15 09:55:47 mohor |
// Wishbone interface added, few fixes for better performance, |
// hooks for boundary scan testing added. |
// |
// Revision 1.5 2001/09/24 14:06:42 mohor |
// Changes connected to the OpenRISC access (SPR read, SPR write). |
// |
// Revision 1.4 2001/09/20 10:11:25 mohor |
// Working version. Few bugs fixed, comments added. |
// |
// Revision 1.3 2001/09/19 11:55:13 mohor |
// Asynchronous set/reset not used in trace any more. |
// |
// Revision 1.2 2001/09/18 14:13:47 mohor |
// Trace fixed. Some registers changed, trace simplified. |
// |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
// Revision 1.3 2001/06/01 22:22:35 mohor |
// This is a backup. It is not a fully working version. Not for use, yet. |
// |
// Revision 1.2 2001/05/18 13:10:00 mohor |
// Headers changed. All additional information is now avaliable in the README.txt file. |
// |
// Revision 1.1.1.1 2001/05/18 06:35:02 mohor |
// Initial release |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "dbg_defines.v" |
`include "dbg_cpu_defines.v" |
|
// Top module |
module dbg_top( |
// JTAG signals |
tck_i, |
tdi_i, |
tdo_o, |
rst_i, |
|
// TAP states |
shift_dr_i, |
pause_dr_i, |
update_dr_i, |
|
// Instructions |
debug_select_i |
|
|
`ifdef WISHBONE_SUPPORTED |
// WISHBONE common signals |
, |
wb_clk_i, |
|
// WISHBONE master interface |
wb_adr_o, |
wb_dat_o, |
wb_dat_i, |
wb_cyc_o, |
wb_stb_o, |
wb_sel_o, |
wb_we_o, |
wb_ack_i, |
wb_cab_o, |
wb_err_i, |
wb_cti_o, |
wb_bte_o |
`endif |
|
`ifdef CPU_SUPPORTED |
// CPU signals |
, |
cpu_clk_i, |
cpu_addr_o, |
cpu_data_i, |
cpu_data_o, |
cpu_bp_i, |
cpu_stall_o, |
cpu_stall_all_o, |
cpu_stb_o, |
cpu_sel_o, |
cpu_we_o, |
cpu_ack_i, |
cpu_rst_o |
`endif |
); |
|
|
// JTAG signals |
input tck_i; |
input tdi_i; |
output tdo_o; |
input rst_i; |
|
// TAP states |
input shift_dr_i; |
input pause_dr_i; |
input update_dr_i; |
|
// Instructions |
input debug_select_i; |
|
`ifdef WISHBONE_SUPPORTED |
input wb_clk_i; |
output [31:0] wb_adr_o; |
output [31:0] wb_dat_o; |
input [31:0] wb_dat_i; |
output wb_cyc_o; |
output wb_stb_o; |
output [3:0] wb_sel_o; |
output wb_we_o; |
input wb_ack_i; |
output wb_cab_o; |
input wb_err_i; |
output [2:0] wb_cti_o; |
output [1:0] wb_bte_o; |
|
reg wishbone_scan_chain; |
reg wishbone_ce; |
wire tdi_wb; |
wire tdo_wb; |
wire crc_en_wb; |
wire shift_crc_wb; |
`else |
wire crc_en_wb = 1'b0; |
wire shift_crc_wb = 1'b0; |
`endif |
|
`ifdef CPU_SUPPORTED |
// CPU signals |
input cpu_clk_i; |
output [31:0] cpu_addr_o; |
input [31:0] cpu_data_i; |
output [31:0] cpu_data_o; |
input cpu_bp_i; |
output cpu_stall_o; |
output cpu_stall_all_o; |
output cpu_stb_o; |
output [`CPU_NUM -1:0] cpu_sel_o; |
output cpu_we_o; |
input cpu_ack_i; |
output cpu_rst_o; |
|
reg cpu_debug_scan_chain; |
reg cpu_ce; |
wire tdi_cpu; |
wire tdo_cpu; |
wire crc_en_cpu; |
wire shift_crc_cpu; |
`else |
wire crc_en_cpu = 1'b0; |
wire shift_crc_cpu = 1'b0; |
`endif |
|
|
reg [`DATA_CNT -1:0] data_cnt; |
reg [`CRC_CNT -1:0] crc_cnt; |
reg [`STATUS_CNT -1:0] status_cnt; |
reg [`CHAIN_DATA_LEN -1:0] chain_dr; |
reg [`CHAIN_ID_LENGTH -1:0] chain; |
|
wire chain_latch_en; |
wire data_cnt_end; |
wire crc_cnt_end; |
wire status_cnt_end; |
reg crc_cnt_end_q; |
reg chain_select; |
reg chain_select_error; |
wire crc_out; |
wire crc_match; |
|
wire data_shift_en; |
wire selecting_command; |
|
reg tdo_o; |
|
|
|
|
wire shift_crc; |
|
// data counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
data_cnt <= #1 {`DATA_CNT{1'b0}}; |
else if(shift_dr_i & (~data_cnt_end)) |
data_cnt <= #1 data_cnt + 1'b1; |
else if (update_dr_i) |
data_cnt <= #1 {`DATA_CNT{1'b0}}; |
end |
|
|
assign data_cnt_end = data_cnt == `CHAIN_DATA_LEN; |
|
|
// crc counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
crc_cnt <= #1 {`CRC_CNT{1'b0}}; |
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & chain_select) |
crc_cnt <= #1 crc_cnt + 1'b1; |
else if (update_dr_i) |
crc_cnt <= #1 {`CRC_CNT{1'b0}}; |
end |
|
assign crc_cnt_end = crc_cnt == `CRC_LEN; |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
crc_cnt_end_q <= #1 1'b0; |
else |
crc_cnt_end_q <= #1 crc_cnt_end; |
end |
|
|
// status counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
status_cnt <= #1 {`STATUS_CNT{1'b0}}; |
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end)) |
status_cnt <= #1 status_cnt + 1'b1; |
else if (update_dr_i) |
status_cnt <= #1 {`STATUS_CNT{1'b0}}; |
end |
|
assign status_cnt_end = status_cnt == `STATUS_LEN; |
|
|
assign selecting_command = shift_dr_i & (data_cnt == `DATA_CNT'h0) & debug_select_i; |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
chain_select <= #1 1'b0; |
else if(selecting_command & tdi_i) // Chain select |
chain_select <= #1 1'b1; |
else if (update_dr_i) |
chain_select <= #1 1'b0; |
end |
|
|
always @ (chain) |
begin |
`ifdef CPU_SUPPORTED |
cpu_debug_scan_chain <= #1 1'b0; |
`endif |
`ifdef WISHBONE_SUPPORTED |
wishbone_scan_chain <= #1 1'b0; |
`endif |
chain_select_error <= #1 1'b0; |
|
case (chain) /* synthesis parallel_case */ |
`ifdef CPU_SUPPORTED |
`CPU_DEBUG_CHAIN : cpu_debug_scan_chain <= #1 1'b1; |
`endif |
`ifdef WISHBONE_SUPPORTED |
`WISHBONE_DEBUG_CHAIN : wishbone_scan_chain <= #1 1'b1; |
`endif |
default : chain_select_error <= #1 1'b1; |
endcase |
end |
|
|
assign chain_latch_en = chain_select & crc_cnt_end & (~crc_cnt_end_q); |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
chain <= `CHAIN_ID_LENGTH'b111; |
else if(chain_latch_en & crc_match) |
chain <= #1 chain_dr[`CHAIN_DATA_LEN -1:1]; |
end |
|
|
assign data_shift_en = shift_dr_i & (~data_cnt_end); |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
chain_dr <= #1 `CHAIN_DATA_LEN'h0; |
else if (data_shift_en) |
chain_dr[`CHAIN_DATA_LEN -1:0] <= #1 {tdi_i, chain_dr[`CHAIN_DATA_LEN -1:1]}; |
end |
|
|
// Calculating crc for input data |
dbg_crc32_d1 i_dbg_crc32_d1_in |
( |
.data (tdi_i), |
.enable (shift_dr_i), |
.shift (1'b0), |
.rst (rst_i), |
.sync_rst (update_dr_i), |
.crc_out (), |
.clk (tck_i), |
.crc_match (crc_match) |
); |
|
|
reg tdo_chain_select; |
wire crc_en; |
wire crc_en_dbg; |
reg crc_started; |
|
assign crc_en = crc_en_dbg | crc_en_wb | crc_en_cpu; |
|
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end); |
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
crc_started <= #1 1'b0; |
else if (crc_en) |
crc_started <= #1 1'b1; |
else if (update_dr_i) |
crc_started <= #1 1'b0; |
end |
|
|
reg tdo_tmp; |
|
|
// Calculating crc for input data |
dbg_crc32_d1 i_dbg_crc32_d1_out |
( |
.data (tdo_tmp), |
.enable (crc_en), // enable has priority |
// .shift (1'b0), |
.shift (shift_dr_i & crc_started & (~crc_en)), |
.rst (rst_i), |
.sync_rst (update_dr_i), |
.crc_out (crc_out), |
.clk (tck_i), |
.crc_match () |
); |
|
// Following status is shifted out: |
// 1. bit: 1 if crc is OK, else 0 |
// 2. bit: 1 if command is "chain select", else 0 |
// 3. bit: 1 if non-existing chain is selected else 0 |
// 4. bit: always 1 |
|
reg [799:0] current_on_tdo; |
|
always @ (status_cnt or chain_select or crc_match or chain_select_error or crc_out) |
begin |
case (status_cnt) /* synthesis full_case parallel_case */ |
`STATUS_CNT'd0 : begin |
tdo_chain_select = crc_match; |
current_on_tdo = "crc_match"; |
end |
`STATUS_CNT'd1 : begin |
tdo_chain_select = chain_select; |
current_on_tdo = "chain_select"; |
end |
`STATUS_CNT'd2 : begin |
tdo_chain_select = chain_select_error; |
current_on_tdo = "chain_select_error"; |
end |
`STATUS_CNT'd3 : begin |
tdo_chain_select = 1'b1; |
current_on_tdo = "one 1"; |
end |
`STATUS_CNT'd4 : begin |
tdo_chain_select = crc_out; |
// tdo_chain_select = 1'hz; |
current_on_tdo = "crc_out"; |
end |
endcase |
end |
|
|
|
|
assign shift_crc = shift_crc_wb | shift_crc_cpu; |
|
always @ (shift_crc or crc_out or tdo_chain_select |
`ifdef WISHBONE_SUPPORTED |
or wishbone_ce or tdo_wb |
`endif |
`ifdef CPU_SUPPORTED |
or cpu_ce or tdo_cpu |
`endif |
) |
begin |
if (shift_crc) // shifting crc |
tdo_tmp = crc_out; |
`ifdef WISHBONE_SUPPORTED |
else if (wishbone_ce) // shifting data from wb |
tdo_tmp = tdo_wb; |
`endif |
`ifdef CPU_SUPPORTED |
else if (cpu_ce) // shifting data from cpu |
tdo_tmp = tdo_cpu; |
`endif |
else |
tdo_tmp = tdo_chain_select; |
end |
|
|
always @ (negedge tck_i) |
begin |
tdo_o <= #1 tdo_tmp; |
end |
|
|
|
|
// Signals for WISHBONE module |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
`ifdef WISHBONE_SUPPORTED |
wishbone_ce <= #1 1'b0; |
`endif |
`ifdef CPU_SUPPORTED |
cpu_ce <= #1 1'b0; |
`endif |
end |
else if(selecting_command & (~tdi_i)) |
begin |
`ifdef WISHBONE_SUPPORTED |
if (wishbone_scan_chain) // wishbone CE |
wishbone_ce <= #1 1'b1; |
`endif |
`ifdef CPU_SUPPORTED |
if (cpu_debug_scan_chain) // CPU CE |
cpu_ce <= #1 1'b1; |
`endif |
end |
else if (update_dr_i) // igor !!! This needs to be changed? |
begin |
`ifdef WISHBONE_SUPPORTED |
wishbone_ce <= #1 1'b0; |
`endif |
`ifdef CPU_SUPPORTED |
cpu_ce <= #1 1'b0; |
`endif |
end |
end |
|
|
`ifdef WISHBONE_SUPPORTED |
assign tdi_wb = wishbone_ce & tdi_i; |
`endif |
|
`ifdef CPU_SUPPORTED |
assign tdi_cpu = cpu_ce & tdi_i; |
`endif |
|
|
`ifdef WISHBONE_SUPPORTED |
// Connecting wishbone module |
dbg_wb i_dbg_wb ( |
// JTAG signals |
.tck_i (tck_i), |
.tdi_i (tdi_wb), |
.tdo_o (tdo_wb), |
|
// TAP states |
.shift_dr_i (shift_dr_i), |
.pause_dr_i (pause_dr_i), |
.update_dr_i (update_dr_i), |
|
.wishbone_ce_i (wishbone_ce), |
.crc_match_i (crc_match), |
.crc_en_o (crc_en_wb), |
.shift_crc_o (shift_crc_wb), |
.rst_i (rst_i), |
|
// WISHBONE common signals |
.wb_clk_i (wb_clk_i), |
|
// WISHBONE master interface |
.wb_adr_o (wb_adr_o), |
.wb_dat_o (wb_dat_o), |
.wb_dat_i (wb_dat_i), |
.wb_cyc_o (wb_cyc_o), |
.wb_stb_o (wb_stb_o), |
.wb_sel_o (wb_sel_o), |
.wb_we_o (wb_we_o), |
.wb_ack_i (wb_ack_i), |
.wb_cab_o (wb_cab_o), |
.wb_err_i (wb_err_i), |
.wb_cti_o (wb_cti_o), |
.wb_bte_o (wb_bte_o) |
); |
`endif |
|
|
`ifdef CPU_SUPPORTED |
// Connecting cpu module |
dbg_cpu i_dbg_cpu ( |
// JTAG signals |
.tck_i (tck_i), |
.tdi_i (tdi_cpu), |
.tdo_o (tdo_cpu), |
|
// TAP states |
.shift_dr_i (shift_dr_i), |
.pause_dr_i (pause_dr_i), |
.update_dr_i (update_dr_i), |
|
.cpu_ce_i (cpu_ce), |
.crc_match_i (crc_match), |
.crc_en_o (crc_en_cpu), |
.shift_crc_o (shift_crc_cpu), |
.rst_i (rst_i), |
|
// CPU signals |
.cpu_clk_i (cpu_clk_i), |
.cpu_addr_o (cpu_addr_o), |
.cpu_data_i (cpu_data_i), |
.cpu_data_o (cpu_data_o), |
.cpu_bp_i (cpu_bp_i), |
.cpu_stall_o (cpu_stall_o), |
.cpu_stall_all_o (cpu_stall_all_o), |
.cpu_stb_o (cpu_stb_o), |
.cpu_sel_o (cpu_sel_o), |
.cpu_we_o (cpu_we_o), |
.cpu_ack_i (cpu_ack_i), |
.cpu_rst_o (cpu_rst_o) |
); |
`endif // CPU_SUPPORTED |
|
|
|
endmodule |
/verilog/dbg_defines.v
0,0 → 1,133
////////////////////////////////////////////////////////////////////// |
//// //// |
//// dbg_defines.v //// |
//// //// |
//// //// |
//// This file is part of the SoC/OpenRISC Development Interface //// |
//// http://www.opencores.org/projects/DebugInterface/ //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2003 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2004/01/20 14:23:45 mohor |
// Define name changed. |
// |
// Revision 1.15 2003/12/23 15:07:34 mohor |
// New directory structure. New version of the debug interface. |
// Files that are not needed removed. |
// |
// Revision 1.14 2003/10/23 16:17:00 mohor |
// CRC logic changed. |
// |
// Revision 1.13 2003/10/21 09:48:31 simons |
// Mbist support added. |
// |
// Revision 1.12 2003/09/17 14:38:57 simons |
// WB_CNTL register added, some syncronization fixes. |
// |
// Revision 1.11 2003/08/28 13:55:21 simons |
// Three more chains added for cpu debug access. |
// |
// Revision 1.10 2003/07/31 12:19:49 simons |
// Multiple cpu support added. |
// |
// Revision 1.9 2002/05/07 14:43:59 mohor |
// mon_cntl_o signals that controls monitor mux added. |
// |
// Revision 1.8 2002/01/25 07:58:34 mohor |
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in |
// not filled-in. Tested in hw. |
// |
// Revision 1.7 2001/12/06 10:08:06 mohor |
// Warnings from synthesys tools fixed. |
// |
// Revision 1.6 2001/11/28 09:38:30 mohor |
// Trace disabled by default. |
// |
// Revision 1.5 2001/10/15 09:55:47 mohor |
// Wishbone interface added, few fixes for better performance, |
// hooks for boundary scan testing added. |
// |
// Revision 1.4 2001/09/24 14:06:42 mohor |
// Changes connected to the OpenRISC access (SPR read, SPR write). |
// |
// Revision 1.3 2001/09/20 10:11:25 mohor |
// Working version. Few bugs fixed, comments added. |
// |
// Revision 1.2 2001/09/18 14:13:47 mohor |
// Trace fixed. Some registers changed, trace simplified. |
// |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
// Revision 1.3 2001/06/01 22:22:35 mohor |
// This is a backup. It is not a fully working version. Not for use, yet. |
// |
// Revision 1.2 2001/05/18 13:10:00 mohor |
// Headers changed. All additional information is now avaliable in the README.txt file. |
// |
// Revision 1.1.1.1 2001/05/18 06:35:08 mohor |
// Initial release |
// |
// |
|
|
// Length of the CHAIN ID register |
`define CHAIN_ID_LENGTH 3 |
|
// Length of data |
`define CHAIN_DATA_LEN `CHAIN_ID_LENGTH + 1 |
`define DATA_CNT 3 |
|
// Length of status |
`define STATUS_LEN 4 |
`define STATUS_CNT 3 |
|
// Length of the CRC |
`define CRC_LEN 32 |
`define CRC_CNT 6 |
|
// Chains |
`define CPU_DEBUG_CHAIN 3'b000 |
`define WISHBONE_DEBUG_CHAIN 3'b001 |
|
// If WISHBONE debugging is supported uncomment the folowing line |
`define WISHBONE_SUPPORTED |
|
// If CPU_DEBUG is supported uncomment the folowing line |
`define CPU_SUPPORTED |
|
/verilog/dbg_register.v
0,0 → 1,89
////////////////////////////////////////////////////////////////////// |
//// //// |
//// dbg_register.v //// |
//// //// |
//// //// |
//// This file is part of the SoC/OpenRISC Development Interface //// |
//// http://www.opencores.org/projects/DebugInterface/ //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2004/01/16 14:53:33 mohor |
// *** empty log message *** |
// |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
|
module dbg_register ( |
data_in, |
data_out, |
write, |
clk, |
reset |
); |
|
|
parameter WIDTH = 8; // default parameter of the register width |
parameter RESET_VALUE = 0; |
|
|
input [WIDTH-1:0] data_in; |
input write; |
input clk; |
input reset; |
|
output [WIDTH-1:0] data_out; |
reg [WIDTH-1:0] data_out; |
|
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
data_out[WIDTH-1:0] <= #1 RESET_VALUE; |
else if(write) |
data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0]; |
end |
|
|
endmodule // Register |
|
/verilog/dbg_cpu.v
0,0 → 1,693
////////////////////////////////////////////////////////////////////// |
//// //// |
//// dbg_cpu.v //// |
//// //// |
//// //// |
//// This file is part of the SoC/OpenRISC Development Interface //// |
//// http://www.opencores.org/projects/DebugInterface/ //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor (igorm@opencores.org) //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 - 2004 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2004/01/22 13:58:53 mohor |
// Port signals are all set to zero after reset. |
// |
// Revision 1.5 2004/01/19 07:32:41 simons |
// Reset values width added because of FV, a good sentence changed because some tools can not handle it. |
// |
// Revision 1.4 2004/01/17 18:38:11 mohor |
// cpu_tall_o is set with cpu_stb_o or register. |
// |
// Revision 1.3 2004/01/17 18:01:24 mohor |
// New version. |
// |
// Revision 1.2 2004/01/17 17:01:14 mohor |
// Almost finished. |
// |
// Revision 1.1 2004/01/16 14:53:31 mohor |
// *** empty log message *** |
// |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
// synopsys translate_on |
`include "dbg_cpu_defines.v" |
|
// Top module |
module dbg_cpu( |
// JTAG signals |
tck_i, |
tdi_i, |
tdo_o, |
|
// TAP states |
shift_dr_i, |
pause_dr_i, |
update_dr_i, |
|
cpu_ce_i, |
crc_match_i, |
crc_en_o, |
shift_crc_o, |
rst_i, |
|
// CPU signals |
cpu_clk_i, |
cpu_addr_o, |
cpu_data_i, |
cpu_data_o, |
cpu_bp_i, |
cpu_stall_o, |
cpu_stall_all_o, |
cpu_stb_o, |
cpu_sel_o, // Not synchronized |
cpu_we_o, |
cpu_ack_i, |
cpu_rst_o |
|
|
); |
|
// JTAG signals |
input tck_i; |
input tdi_i; |
output tdo_o; |
|
// TAP states |
input shift_dr_i; |
input pause_dr_i; |
input update_dr_i; |
|
input cpu_ce_i; |
input crc_match_i; |
output crc_en_o; |
output shift_crc_o; |
input rst_i; |
|
|
// CPU signals |
input cpu_clk_i; |
output [31:0] cpu_addr_o; |
input [31:0] cpu_data_i; |
output [31:0] cpu_data_o; |
input cpu_bp_i; |
output cpu_stall_o; |
output cpu_stall_all_o; |
output cpu_stb_o; |
output [`CPU_NUM -1:0] cpu_sel_o; |
output cpu_we_o; |
input cpu_ack_i; |
output cpu_rst_o; |
|
|
|
reg tdo_o; |
|
wire cmd_cnt_en; |
reg [1:0] cmd_cnt; |
wire cmd_cnt_end; |
reg cmd_cnt_end_q; |
wire addr_cnt_en; |
reg [5:0] addr_cnt; |
reg [5:0] addr_cnt_limit; |
wire addr_cnt_end; |
wire crc_cnt_en; |
reg [5:0] crc_cnt; |
wire crc_cnt_end; |
reg crc_cnt_end_q; |
wire data_cnt_en; |
reg [5:0] data_cnt; |
reg [5:0] data_cnt_limit; |
wire data_cnt_end; |
reg data_cnt_end_q; |
wire status_cnt_end; |
reg status_cnt1, status_cnt2, status_cnt3, status_cnt4; |
reg [3:0] status; |
|
reg crc_match_reg; |
wire enable; |
|
reg read_cycle_reg; |
reg read_cycle_reg_q; |
reg read_cycle_cpu; |
reg read_cycle_cpu_q; |
reg write_cycle_reg; |
reg write_cycle_cpu; |
wire read_cycle; |
wire write_cycle; |
|
reg [31:0] dr; |
wire [7:0] reg_data_out; |
|
wire dr_read_reg; |
wire dr_write_reg; |
wire dr_read_cpu8; |
wire dr_read_cpu32; |
wire dr_write_cpu8; |
wire dr_write_cpu32; |
wire dr_go; |
|
reg dr_read_reg_latched; |
reg dr_write_reg_latched; |
reg dr_read_cpu8_latched; |
reg dr_read_cpu32_latched; |
reg dr_write_cpu8_latched; |
reg dr_write_cpu32_latched; |
reg dr_go_latched; |
|
reg cmd_read_reg; |
reg cmd_read_cpu; |
reg cmd_write_reg; |
reg cmd_write_cpu; |
reg cycle_32_bit; |
reg reg_access; |
|
reg [31:0] adr; |
reg cpu_ack_sync; |
reg cpu_ack_tck; |
reg cpu_ack_tck_q; |
reg cpu_stb; |
reg cpu_stb_sync; |
reg cpu_stb_o; |
wire cpu_stall_tmp; |
|
wire go_prelim; |
wire crc_cnt_31; |
|
|
|
assign enable = cpu_ce_i & shift_dr_i; |
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end); |
assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC |
|
|
assign cmd_cnt_en = enable & (~cmd_cnt_end); |
|
|
// Command counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
cmd_cnt <= #1 2'h0; |
else if (update_dr_i) |
cmd_cnt <= #1 2'h0; |
else if (cmd_cnt_en) |
cmd_cnt <= #1 cmd_cnt + 1'b1; |
end |
|
|
assign addr_cnt_en = enable & cmd_cnt_end & (~addr_cnt_end); |
|
|
// Address/length counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
addr_cnt <= #1 6'h0; |
else if (update_dr_i) |
addr_cnt <= #1 6'h0; |
else if (addr_cnt_en) |
addr_cnt <= #1 addr_cnt + 1'b1; |
end |
|
|
assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle); |
|
|
// Data counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
data_cnt <= #1 6'h0; |
else if (update_dr_i) |
data_cnt <= #1 6'h0; |
else if (data_cnt_en) |
data_cnt <= #1 data_cnt + 1'b1; |
end |
|
|
assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle)); |
|
|
// crc counter |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
crc_cnt <= #1 6'h0; |
else if(crc_cnt_en) |
crc_cnt <= #1 crc_cnt + 1'b1; |
else if (update_dr_i) |
crc_cnt <= #1 6'h0; |
end |
|
|
// Upper limit. Address/length counter counts until this value is reached |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
addr_cnt_limit = 6'd0; |
else if (cmd_cnt == 2'h2) |
begin |
if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO) |
addr_cnt_limit = 6'd0; |
else // (current command is WB_WRITEx or WB_READx) |
addr_cnt_limit = 6'd32; |
end |
end |
|
|
assign cmd_cnt_end = cmd_cnt == 2'h3; |
assign addr_cnt_end = addr_cnt == addr_cnt_limit; |
assign crc_cnt_end = crc_cnt == 6'd32; |
assign crc_cnt_31 = crc_cnt == 6'd31; |
assign data_cnt_end = (data_cnt == data_cnt_limit); |
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
crc_cnt_end_q <= #1 1'b0; |
cmd_cnt_end_q <= #1 1'b0; |
data_cnt_end_q <= #1 1'b0; |
end |
else |
begin |
crc_cnt_end_q <= #1 crc_cnt_end; |
cmd_cnt_end_q <= #1 cmd_cnt_end; |
data_cnt_end_q <= #1 data_cnt_end; |
end |
end |
|
|
// Status counter is made of 4 serialy connected registers |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
status_cnt1 <= #1 1'b0; |
else if (update_dr_i) |
status_cnt1 <= #1 1'b0; |
else if (data_cnt_end & read_cycle | |
crc_cnt_end & (~read_cycle) |
) |
status_cnt1 <= #1 1'b1; |
end |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
status_cnt2 <= #1 1'b0; |
status_cnt3 <= #1 1'b0; |
status_cnt4 <= #1 1'b0; |
end |
else if (update_dr_i) |
begin |
status_cnt2 <= #1 1'b0; |
status_cnt3 <= #1 1'b0; |
status_cnt4 <= #1 1'b0; |
end |
else |
begin |
status_cnt2 <= #1 status_cnt1; |
status_cnt3 <= #1 status_cnt2; |
status_cnt4 <= #1 status_cnt3; |
end |
end |
|
|
assign status_cnt_end = status_cnt4; |
|
|
|
|
// Latching address |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
adr <= #1 32'h0; |
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched)) |
adr <= #1 dr[31:0]; |
end |
|
|
assign cpu_addr_o = adr; |
|
|
// Shift register for shifting in and out the data |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
dr <= #1 32'h0; |
else if (reg_access) |
dr[31:24] <= #1 reg_data_out; |
else if (cpu_ack_tck & (~cpu_ack_tck_q) & read_cycle_cpu) |
begin |
if (cycle_32_bit) |
dr[31:0] <= #1 cpu_data_i; |
else |
dr[31:24] <= #1 cpu_data_i[7:0]; |
end |
else if (enable & ((~addr_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle) | (crc_cnt_end & (~data_cnt_end) & read_cycle))) |
begin |
dr <= #1 {dr[30:0], tdi_i}; |
end |
end |
|
|
assign dr_read_reg = dr[2:0] == `CPU_READ_REG; |
assign dr_write_reg = dr[2:0] == `CPU_WRITE_REG; |
assign dr_read_cpu8 = dr[2:0] == `CPU_READ8; |
assign dr_read_cpu32 = dr[2:0] == `CPU_READ32; |
assign dr_write_cpu8 = dr[2:0] == `CPU_WRITE8; |
assign dr_write_cpu32 = dr[2:0] == `CPU_WRITE32; |
assign dr_go = dr[2:0] == `CPU_GO; |
|
|
// Latching instruction |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
dr_read_reg_latched <= #1 1'b0; |
dr_read_cpu8_latched <= #1 1'b0; |
dr_read_cpu32_latched <= #1 1'b0; |
dr_write_reg_latched <= #1 1'b0; |
dr_write_cpu8_latched <= #1 1'b0; |
dr_write_cpu32_latched <= #1 1'b0; |
dr_go_latched <= #1 1'b0; |
end |
else if (update_dr_i) |
begin |
dr_read_reg_latched <= #1 1'b0; |
dr_read_cpu8_latched <= #1 1'b0; |
dr_read_cpu32_latched <= #1 1'b0; |
dr_write_reg_latched <= #1 1'b0; |
dr_write_cpu8_latched <= #1 1'b0; |
dr_write_cpu32_latched <= #1 1'b0; |
dr_go_latched <= #1 1'b0; |
end |
else if (cmd_cnt_end & (~cmd_cnt_end_q)) |
begin |
dr_read_reg_latched <= #1 dr_read_reg; |
dr_read_cpu8_latched <= #1 dr_read_cpu8; |
dr_read_cpu32_latched <= #1 dr_read_cpu32; |
dr_write_reg_latched <= #1 dr_write_reg; |
dr_write_cpu8_latched <= #1 dr_write_cpu8; |
dr_write_cpu32_latched <= #1 dr_write_cpu32; |
dr_go_latched <= #1 dr_go; |
end |
end |
|
// Latching instruction |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
cmd_read_reg <= #1 1'b0; |
cmd_read_cpu <= #1 1'b0; |
cmd_write_reg <= #1 1'b0; |
cmd_write_cpu <= #1 1'b0; |
cycle_32_bit <= #1 1'b0; |
end |
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i) |
begin |
cmd_read_reg <= #1 dr_read_reg_latched; |
cmd_read_cpu <= #1 dr_read_cpu8_latched | dr_read_cpu32_latched; |
cmd_write_reg <= #1 dr_write_reg_latched; |
cmd_write_cpu <= #1 dr_write_cpu8_latched | dr_write_cpu32_latched; |
cycle_32_bit <= #1 dr_read_cpu32_latched | dr_write_cpu32_latched; |
end |
end |
|
|
// Upper limit. Data counter counts until this value is reached. |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
data_cnt_limit <= #1 6'h0; |
else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (~dr_go_latched)) |
begin |
if (dr_read_cpu32_latched | dr_write_cpu32_latched) |
data_cnt_limit <= #1 6'd32; |
else |
data_cnt_limit <= #1 6'd8; |
end |
end |
|
|
assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i); |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
read_cycle_reg <= #1 1'b0; |
else if (update_dr_i) |
read_cycle_reg <= #1 1'b0; |
else if (cmd_read_reg & go_prelim) |
read_cycle_reg <= #1 1'b1; |
end |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
read_cycle_cpu <= #1 1'b0; |
else if (update_dr_i) |
read_cycle_cpu <= #1 1'b0; |
else if (cmd_read_cpu & go_prelim) |
read_cycle_cpu <= #1 1'b1; |
end |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
read_cycle_reg_q <= #1 1'b0; |
read_cycle_cpu_q <= #1 1'b0; |
end |
else |
begin |
read_cycle_reg_q <= #1 read_cycle_reg; |
read_cycle_cpu_q <= #1 read_cycle_cpu; |
end |
end |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
write_cycle_reg <= #1 1'b0; |
else if (update_dr_i) |
write_cycle_reg <= #1 1'b0; |
else if (cmd_write_reg & go_prelim) |
write_cycle_reg <= #1 1'b1; |
end |
|
|
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
write_cycle_cpu <= #1 1'b0; |
else if (update_dr_i) |
write_cycle_cpu <= #1 1'b0; |
else if (cmd_write_cpu & go_prelim) |
write_cycle_cpu <= #1 1'b1; |
end |
|
|
assign read_cycle = read_cycle_reg | read_cycle_cpu; |
assign write_cycle = write_cycle_reg | write_cycle_cpu; |
|
|
|
// Start register access cycle |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
reg_access <= #1 1'b0; |
else if (write_cycle_reg & data_cnt_end & (~data_cnt_end_q) | read_cycle_reg & (~read_cycle_reg_q)) |
reg_access <= #1 1'b1; |
else |
reg_access <= #1 1'b0; |
end |
|
|
|
// Connecting dbg_cpu_registers |
dbg_cpu_registers i_dbg_cpu_registers |
( |
.data_i (dr[7:0]), |
.data_o (reg_data_out), |
.addr_i (adr[1:0]), |
.we_i (write_cycle_reg), |
.en_i (reg_access), |
.clk_i (tck_i), |
.bp_i (cpu_bp_i), |
.rst_i (rst_i), |
.cpu_clk_i (cpu_clk_i), |
.cpu_stall_o (cpu_stall_tmp), |
.cpu_stall_all_o (cpu_stall_all_o), |
.cpu_sel_o (cpu_sel_o), |
.cpu_rst_o (cpu_rst_o) |
); |
|
|
|
assign cpu_we_o = write_cycle_cpu; |
assign cpu_data_o = dr[31:0]; |
assign cpu_stall_o = cpu_stb_o | cpu_stall_tmp; |
|
|
|
// Synchronizing ack signal from cpu |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
cpu_ack_sync <= #1 1'b0; |
cpu_ack_tck <= #1 1'b0; |
cpu_ack_tck_q <= #1 1'b0; |
end |
else |
begin |
cpu_ack_sync <= #1 cpu_ack_i; |
cpu_ack_tck <= #1 cpu_ack_sync; |
cpu_ack_tck_q <= #1 cpu_ack_tck; |
end |
end |
|
|
|
// Start cpu access cycle |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
cpu_stb <= #1 1'b0; |
else if (update_dr_i | cpu_ack_tck) |
cpu_stb <= #1 1'b0; |
else if (write_cycle_cpu & data_cnt_end & (~data_cnt_end_q) | read_cycle_cpu & (~read_cycle_cpu_q)) |
cpu_stb <= #1 1'b1; |
end |
|
|
|
// Synchronizing cpu_stb to cpu_clk_i clock |
always @ (posedge cpu_clk_i or posedge rst_i) |
begin |
if (rst_i) |
begin |
cpu_stb_sync <= #1 1'b0; |
cpu_stb_o <= #1 1'b0; |
end |
else |
begin |
cpu_stb_sync <= #1 cpu_stb; |
cpu_stb_o <= #1 cpu_stb_sync; |
end |
end |
|
|
// Latching crc |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
crc_match_reg <= #1 1'b0; |
else if(crc_cnt_end & (~crc_cnt_end_q)) |
crc_match_reg <= #1 crc_match_i; |
end |
|
|
|
// Status register |
always @ (posedge tck_i or posedge rst_i) |
begin |
if (rst_i) |
status <= #1 4'h0; |
else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle)) |
status <= #1 {crc_match_i, 1'b0, 1'b1, 1'b0}; |
else if (data_cnt_end & (~data_cnt_end_q) & read_cycle) |
status <= #1 {crc_match_reg, 1'b0, 1'b1, 1'b0}; |
else if (shift_dr_i & (~status_cnt_end)) |
status <= #1 {status[0], status[3:1]}; |
end |
// Following status is shifted out: |
// 1. bit: 1 if crc is OK, else 0 |
// 2. bit: 1'b0 |
// 3. bit: 1'b1 |
// 4. bit: 1'b0 |
|
|
|
// TDO multiplexer |
always @ (crc_cnt_end or crc_cnt_end_q or crc_match_i or data_cnt_end or data_cnt_end_q or |
read_cycle or crc_match_reg or status or dr) |
begin |
if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle))) |
begin |
tdo_o = crc_match_i; |
end |
else if (read_cycle & crc_cnt_end & (~data_cnt_end)) |
begin |
tdo_o = dr[31]; |
end |
else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated |
begin |
tdo_o = crc_match_reg; |
end |
else if (crc_cnt_end) |
begin |
tdo_o = status[0]; |
end |
else |
begin |
tdo_o = 1'b0; |
end |
end |
|
|
|
|
|
|
|
endmodule |
|
verilog/dbg_cpu.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/dbg_wb.v
===================================================================
--- verilog/dbg_wb.v (nonexistent)
+++ verilog/dbg_wb.v (revision 158)
@@ -0,0 +1,1147 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_wb.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.17 2004/01/22 13:58:53 mohor
+// Port signals are all set to zero after reset.
+//
+// Revision 1.16 2004/01/19 07:32:41 simons
+// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
+//
+// Revision 1.15 2004/01/17 18:01:24 mohor
+// New version.
+//
+// Revision 1.14 2004/01/16 14:51:33 mohor
+// cpu registers added.
+//
+// Revision 1.13 2004/01/15 12:09:43 mohor
+// Working.
+//
+// Revision 1.12 2004/01/14 22:59:18 mohor
+// Temp version.
+//
+// Revision 1.11 2004/01/14 12:29:40 mohor
+// temp version. Resets will be changed in next version.
+//
+// Revision 1.10 2004/01/13 11:28:14 mohor
+// tmp version.
+//
+// Revision 1.9 2004/01/10 07:50:24 mohor
+// temp version.
+//
+// Revision 1.8 2004/01/09 12:48:44 mohor
+// tmp version.
+//
+// Revision 1.7 2004/01/08 17:53:36 mohor
+// tmp version.
+//
+// Revision 1.6 2004/01/07 11:58:56 mohor
+// temp4 version.
+//
+// Revision 1.5 2004/01/06 17:15:19 mohor
+// temp3 version.
+//
+// Revision 1.4 2004/01/05 12:16:00 mohor
+// tmp2 version.
+//
+// Revision 1.3 2003/12/23 16:22:46 mohor
+// Tmp version.
+//
+// Revision 1.2 2003/12/23 15:26:26 mohor
+// Small fix.
+//
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_wb_defines.v"
+
+// Top module
+module dbg_wb(
+ // JTAG signals
+ tck_i,
+ tdi_i,
+ tdo_o,
+
+ // TAP states
+ shift_dr_i,
+ pause_dr_i,
+ update_dr_i,
+
+ wishbone_ce_i,
+ crc_match_i,
+ crc_en_o,
+ shift_crc_o,
+ rst_i,
+
+ // WISHBONE common signals
+ wb_clk_i,
+
+ // WISHBONE master interface
+ wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
+ wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
+
+ );
+
+// JTAG signals
+input tck_i;
+input tdi_i;
+output tdo_o;
+
+// TAP states
+input shift_dr_i;
+input pause_dr_i;
+input update_dr_i;
+
+input wishbone_ce_i;
+input crc_match_i;
+output crc_en_o;
+output shift_crc_o;
+input rst_i;
+// WISHBONE common signals
+input wb_clk_i;
+
+// WISHBONE master interface
+output [31:0] wb_adr_o;
+output [31:0] wb_dat_o;
+input [31:0] wb_dat_i;
+output wb_cyc_o;
+output wb_stb_o;
+output [3:0] wb_sel_o;
+output wb_we_o;
+input wb_ack_i;
+output wb_cab_o;
+input wb_err_i;
+output [2:0] wb_cti_o;
+output [1:0] wb_bte_o;
+
+reg wb_cyc_o;
+reg [31:0] wb_adr_o;
+reg [31:0] wb_dat_o;
+reg [3:0] wb_sel_o;
+
+reg tdo_o;
+
+reg [50:0] dr;
+wire enable;
+wire cmd_cnt_en;
+reg [1:0] cmd_cnt;
+wire cmd_cnt_end;
+reg cmd_cnt_end_q;
+wire addr_len_cnt_en;
+reg [5:0] addr_len_cnt;
+reg [5:0] addr_len_cnt_limit;
+wire addr_len_cnt_end;
+wire crc_cnt_en;
+reg [5:0] crc_cnt;
+wire crc_cnt_end;
+reg crc_cnt_end_q;
+wire data_cnt_en;
+reg [18:0] data_cnt;
+reg [18:0] data_cnt_limit;
+wire data_cnt_end;
+reg data_cnt_end_q;
+reg status_reset_en;
+
+reg crc_match_reg;
+
+reg [2:0] cmd, cmd_old, dr_cmd_latched;
+reg [31:0] adr;
+reg [15:0] len;
+reg start_rd_tck;
+reg rd_tck_started;
+reg start_rd_sync1;
+reg start_wb_rd;
+reg start_wb_rd_q;
+reg start_wr_tck;
+reg start_wr_sync1;
+reg start_wb_wr;
+reg start_wb_wr_q;
+
+wire dr_read;
+wire dr_write;
+wire dr_go;
+
+reg dr_write_latched;
+reg dr_read_latched;
+reg dr_go_latched;
+
+wire status_cnt_end;
+
+wire byte, half, long;
+reg byte_q, half_q, long_q;
+reg byte_q2, half_q2, long_q2;
+reg cmd_read;
+reg cmd_write;
+reg cmd_go;
+
+reg status_cnt1, status_cnt2, status_cnt3, status_cnt4;
+
+reg [`STATUS_LEN -1:0] status;
+
+reg wb_error, wb_error_sync, wb_error_tck;
+reg wb_overrun, wb_overrun_sync, wb_overrun_tck;
+reg underrun_tck;
+
+reg busy_wb;
+reg busy_tck;
+reg wb_end;
+reg wb_end_rst;
+reg wb_end_rst_sync;
+reg wb_end_sync;
+reg wb_end_tck, wb_end_tck_q;
+reg busy_sync;
+reg latch_data;
+
+reg set_addr, set_addr_sync, set_addr_wb, set_addr_wb_q;
+reg read_cycle;
+reg write_cycle;
+reg [2:0] rw_type;
+wire [31:0] input_data;
+
+wire len_eq_0;
+wire crc_cnt_31;
+
+reg [1:0] ptr;
+reg [2:0] fifo_cnt;
+wire fifo_full;
+wire fifo_empty;
+reg [7:0] mem [0:3];
+reg [2:0] mem_ptr;
+reg wishbone_ce_sync;
+reg wishbone_ce_rst;
+wire go_prelim;
+
+
+
+assign enable = wishbone_ce_i & shift_dr_i;
+assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
+assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC
+
+
+// Selecting where to take the data from
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ ptr <= #1 2'h0;
+ else if (update_dr_i)
+ ptr <= #1 2'h0;
+ else if (read_cycle & crc_cnt_31) // first latch
+ ptr <= #1 ptr + 1'b1;
+ else if (read_cycle & byte & (~byte_q))
+ ptr <= ptr + 1'd1;
+end
+
+
+// Shift register for shifting in and out the data
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ dr <= #1 51'h0;
+ latch_data <= #1 1'b0;
+ end
+ else if (read_cycle & crc_cnt_31)
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else if (read_cycle & crc_cnt_end)
+ begin
+ case (rw_type) // synthesis parallel_case full_case
+ `WB_READ8 : begin
+ if(byte & (~byte_q))
+ begin
+ case (ptr) // synthesis parallel_case
+ 2'b00 : dr[31:24] <= #1 input_data[31:24];
+ 2'b01 : dr[31:24] <= #1 input_data[23:16];
+ 2'b10 : dr[31:24] <= #1 input_data[15:8];
+ 2'b11 : dr[31:24] <= #1 input_data[7:0];
+ endcase
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:24] <= #1 {dr[30:24], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ `WB_READ16: begin
+ if(half & (~half_q))
+ begin
+ if (ptr[1])
+ dr[31:16] <= #1 input_data[15:0];
+ else
+ dr[31:16] <= #1 input_data[31:16];
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:16] <= #1 {dr[30:16], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ `WB_READ32: begin
+ if(long & (~long_q))
+ begin
+ dr[31:0] <= #1 input_data[31:0];
+ latch_data <= #1 1'b1;
+ end
+ else
+ begin
+ dr[31:0] <= #1 {dr[30:0], 1'b0};
+ latch_data <= #1 1'b0;
+ end
+ end
+ endcase
+ end
+ else if (enable & ((~addr_len_cnt_end) | (~cmd_cnt_end) | ((~data_cnt_end) & write_cycle)))
+ begin
+ dr <= #1 {dr[49:0], tdi_i};
+ latch_data <= #1 1'b0;
+ end
+end
+
+
+assign cmd_cnt_en = enable & (~cmd_cnt_end);
+
+
+// Command counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ cmd_cnt <= #1 2'h0;
+ else if (update_dr_i)
+ cmd_cnt <= #1 2'h0;
+ else if (cmd_cnt_en)
+ cmd_cnt <= #1 cmd_cnt + 1'b1;
+end
+
+
+assign addr_len_cnt_en = enable & cmd_cnt_end & (~addr_len_cnt_end);
+
+
+// Address/length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (update_dr_i)
+ addr_len_cnt <= #1 6'h0;
+ else if (addr_len_cnt_en)
+ addr_len_cnt <= #1 addr_len_cnt + 1'b1;
+end
+
+
+assign data_cnt_en = enable & (~data_cnt_end) & (cmd_cnt_end & write_cycle | crc_cnt_end & read_cycle);
+
+
+// Data counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt <= #1 19'h0;
+ else if (update_dr_i)
+ data_cnt <= #1 19'h0;
+ else if (data_cnt_en)
+ data_cnt <= #1 data_cnt + 1'b1;
+end
+
+
+
+assign byte = data_cnt[2:0] == 3'd7;
+assign half = data_cnt[3:0] == 4'd15;
+assign long = data_cnt[4:0] == 5'd31;
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ byte_q <= #1 1'b0;
+ half_q <= #1 1'b0;
+ long_q <= #1 1'b0;
+ byte_q2 <= #1 1'b0;
+ half_q2 <= #1 1'b0;
+ long_q2 <= #1 1'b0;
+ end
+ else
+ begin
+ byte_q <= #1 byte;
+ half_q <= #1 half;
+ long_q <= #1 long;
+ byte_q2 <= #1 byte_q;
+ half_q2 <= #1 half_q;
+ long_q2 <= #1 long_q;
+ end
+end
+
+
+assign dr_read = (dr[2:0] == `WB_READ8) || (dr[2:0] == `WB_READ16) || (dr[2:0] == `WB_READ32);
+assign dr_write = (dr[2:0] == `WB_WRITE8) || (dr[2:0] == `WB_WRITE16) || (dr[2:0] == `WB_WRITE32);
+assign dr_go = dr[2:0] == `WB_GO;
+
+
+// Latching instruction
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ dr_cmd_latched <= #1 3'h0;
+ dr_read_latched <= #1 1'b0;
+ dr_write_latched <= #1 1'b0;
+ dr_go_latched <= #1 1'b0;
+ end
+ else if (update_dr_i)
+ begin
+ dr_cmd_latched <= #1 3'h0;
+ dr_read_latched <= #1 1'b0;
+ dr_write_latched <= #1 1'b0;
+ dr_go_latched <= #1 1'b0;
+ end
+ else if (cmd_cnt_end & (~cmd_cnt_end_q))
+ begin
+ dr_cmd_latched <= #1 dr[2:0];
+ dr_read_latched <= #1 dr_read;
+ dr_write_latched <= #1 dr_write;
+ dr_go_latched <= #1 dr_go;
+ end
+end
+
+
+// Upper limit. Address/length counter counts until this value is reached
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ addr_len_cnt_limit <= #1 6'd0;
+ else if (cmd_cnt == 2'h2)
+ begin
+ if ((~dr[0]) & (~tdi_i)) // (current command is WB_STATUS or WB_GO)
+ addr_len_cnt_limit <= #1 6'd0;
+ else // (current command is WB_WRITEx or WB_READx)
+ addr_len_cnt_limit <= #1 6'd48;
+ end
+end
+
+
+assign go_prelim = (cmd_cnt == 2'h2) & dr[1] & (~dr[0]) & (~tdi_i);
+
+
+// Upper limit. Data counter counts until this value is reached.
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_cnt_limit <= #1 19'h0;
+ else if (update_dr_i)
+ data_cnt_limit <= #1 {len, 3'b000};
+end
+
+
+assign crc_cnt_en = enable & (~crc_cnt_end) & (cmd_cnt_end & addr_len_cnt_end & (~write_cycle) | (data_cnt_end & write_cycle));
+
+
+// crc counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_cnt <= #1 6'h0;
+ else if(crc_cnt_en)
+ crc_cnt <= #1 crc_cnt + 1'b1;
+ else if (update_dr_i)
+ crc_cnt <= #1 6'h0;
+end
+
+assign cmd_cnt_end = cmd_cnt == 2'h3;
+assign addr_len_cnt_end = addr_len_cnt == addr_len_cnt_limit;
+assign crc_cnt_end = crc_cnt == 6'd32;
+assign crc_cnt_31 = crc_cnt == 6'd31;
+assign data_cnt_end = (data_cnt == data_cnt_limit);
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ crc_cnt_end_q <= #1 1'b0;
+ cmd_cnt_end_q <= #1 1'b0;
+ data_cnt_end_q <= #1 1'b0;
+ end
+ else
+ begin
+ crc_cnt_end_q <= #1 crc_cnt_end;
+ cmd_cnt_end_q <= #1 cmd_cnt_end;
+ data_cnt_end_q <= #1 data_cnt_end;
+ end
+end
+
+
+// Status counter is made of 4 serialy connected registers
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ status_cnt1 <= #1 1'b0;
+ else if (update_dr_i)
+ status_cnt1 <= #1 1'b0;
+ else if (data_cnt_end & read_cycle |
+ crc_cnt_end & (~read_cycle)
+ )
+ status_cnt1 <= #1 1'b1;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ status_cnt2 <= #1 1'b0;
+ status_cnt3 <= #1 1'b0;
+ status_cnt4 <= #1 1'b0;
+ end
+ else if (update_dr_i)
+ begin
+ status_cnt2 <= #1 1'b0;
+ status_cnt3 <= #1 1'b0;
+ status_cnt4 <= #1 1'b0;
+ end
+ else
+ begin
+ status_cnt2 <= #1 status_cnt1;
+ status_cnt3 <= #1 status_cnt2;
+ status_cnt4 <= #1 status_cnt3;
+ end
+end
+
+
+assign status_cnt_end = status_cnt4;
+
+
+// Status register
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ status <= #1 {`STATUS_LEN{1'b0}};
+ end
+ else if(crc_cnt_end & (~crc_cnt_end_q) & (~read_cycle))
+ begin
+ status <= #1 {crc_match_i, wb_error_tck, wb_overrun_tck, busy_tck};
+ end
+ else if (data_cnt_end & (~data_cnt_end_q) & read_cycle)
+ begin
+ status <= #1 {crc_match_reg, wb_error_tck, underrun_tck, busy_tck};
+ end
+ else if (shift_dr_i & (~status_cnt_end))
+ begin
+ status <= #1 {status[0], status[`STATUS_LEN -1:1]};
+ end
+end
+// Following status is shifted out:
+// 1. bit: 1 if crc is OK, else 0
+// 2. bit: 1 while WB access is in progress (busy_tck), else 0
+// 3. bit: 1 if overrun occured during write (data couldn't be written fast enough)
+// or underrun occured during read (data couldn't be read fast enough)
+// 4. bit: 1 if WB error occured, else 0
+
+
+// TDO multiplexer
+always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or crc_match_i or
+ data_cnt_end or data_cnt_end_q or read_cycle or crc_match_reg or status or dr)
+begin
+ if (pause_dr_i)
+ begin
+ tdo_o = busy_tck;
+ end
+ else if (crc_cnt_end & (~crc_cnt_end_q) & (~(read_cycle)))
+ begin
+ tdo_o = crc_match_i;
+ end
+ else if (read_cycle & crc_cnt_end & (~data_cnt_end))
+ begin
+ tdo_o = dr[31];
+ end
+ else if (read_cycle & data_cnt_end & (~data_cnt_end_q)) // cmd is already updated
+ begin
+ tdo_o = crc_match_reg;
+ end
+ else if (crc_cnt_end & data_cnt_end) // cmd is already updated
+ begin
+ tdo_o = status[0];
+ end
+ else
+ begin
+ tdo_o = 1'b0;
+ end
+end
+
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ crc_match_reg <= #1 1'b0;
+ else if(crc_cnt_end & (~crc_cnt_end_q))
+ crc_match_reg <= #1 crc_match_i;
+end
+
+
+// Latching instruction
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cmd <= #1 3'h0;
+ cmd_old <= #1 3'h0;
+ cmd_read <= #1 1'b0;
+ cmd_write <= #1 1'b0;
+ cmd_go <= #1 1'b0;
+ end
+ else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
+ begin
+ cmd <= #1 dr_cmd_latched;
+ cmd_old <= #1 cmd;
+ cmd_read <= #1 dr_read_latched;
+ cmd_write <= #1 dr_write_latched;
+ cmd_go <= #1 dr_go_latched;
+ end
+end
+
+
+// Latching address
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ adr <= #1 32'h0;
+ set_addr <= #1 1'b0;
+ end
+ else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i)
+ begin
+ if (dr_write_latched | dr_read_latched)
+ begin
+ adr <= #1 dr[47:16];
+ set_addr <= #1 1'b1;
+ end
+ end
+ else
+ set_addr <= #1 1'b0;
+end
+
+
+// Length counter
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ len <= #1 16'h0;
+ else if(crc_cnt_end & (~crc_cnt_end_q) & crc_match_i & (dr_write_latched | dr_read_latched))
+ len <= #1 dr[15:0];
+ else if (start_rd_tck)
+ begin
+ case (rw_type) // synthesis parallel_case full_case
+ `WB_READ8 : len <= #1 len - 1'd1;
+ `WB_READ16: len <= #1 len - 2'd2;
+ `WB_READ32: len <= #1 len - 3'd4;
+ endcase
+ end
+end
+
+
+assign len_eq_0 = len == 16'h0;
+
+
+// Start wishbone read cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ start_rd_tck <= #1 1'b0;
+ else if (read_cycle & (~dr_go_latched) & (~len_eq_0)) // First read after cmd is entered
+ start_rd_tck <= #1 1'b1;
+ else if ((~start_rd_tck) & read_cycle & (~len_eq_0) & (~fifo_full) & (~rd_tck_started))
+ start_rd_tck <= #1 1'b1;
+ else
+ start_rd_tck <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ rd_tck_started <= #1 1'b0;
+ else if (update_dr_i)
+ rd_tck_started <= #1 1'b0;
+ else if (start_rd_tck)
+ rd_tck_started <= #1 1'b1;
+ else if (wb_end_tck & (~wb_end_tck_q))
+ rd_tck_started <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ read_cycle <= #1 1'b0;
+ else if (update_dr_i)
+ read_cycle <= #1 1'b0;
+ else if (cmd_read & go_prelim)
+ read_cycle <= #1 1'b1;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ rw_type <= #1 3'h0;
+ else if ((cmd_read | cmd_write) & go_prelim)
+ rw_type <= #1 cmd;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ write_cycle <= #1 1'b0;
+ else if (update_dr_i)
+ write_cycle <= #1 1'b0;
+ else if (cmd_write & go_prelim)
+ write_cycle <= #1 1'b1;
+end
+
+
+// Start wishbone write cycle
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_wr_tck <= #1 1'b0;
+ wb_dat_o <= #1 32'h0;
+ end
+ else if (write_cycle)
+ begin
+ case (rw_type) // synthesis parallel_case full_case
+ `WB_WRITE8 : begin
+ if (byte_q & (~byte_q2))
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_o <= #1 {4{dr[7:0]}};
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ `WB_WRITE16 : begin
+ if (half_q & (~half_q2))
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_o <= #1 {2{dr[15:0]}};
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ `WB_WRITE32 : begin
+ if (long_q & (~long_q2))
+ begin
+ start_wr_tck <= #1 1'b1;
+ wb_dat_o <= #1 dr[31:0];
+ end
+ else
+ begin
+ start_wr_tck <= #1 1'b0;
+ end
+ end
+ endcase
+ end
+ else
+ start_wr_tck <= #1 1'b0;
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ start_rd_sync1 <= #1 1'b0;
+ start_wb_rd <= #1 1'b0;
+ start_wb_rd_q <= #1 1'b0;
+
+ start_wr_sync1 <= #1 1'b0;
+ start_wb_wr <= #1 1'b0;
+ start_wb_wr_q <= #1 1'b0;
+
+ set_addr_sync <= #1 1'b0;
+ set_addr_wb <= #1 1'b0;
+ set_addr_wb_q <= #1 1'b0;
+ end
+ else
+ begin
+ start_rd_sync1 <= #1 start_rd_tck;
+ start_wb_rd <= #1 start_rd_sync1;
+ start_wb_rd_q <= #1 start_wb_rd;
+
+ start_wr_sync1 <= #1 start_wr_tck;
+ start_wb_wr <= #1 start_wr_sync1;
+ start_wb_wr_q <= #1 start_wb_wr;
+
+ set_addr_sync <= #1 set_addr;
+ set_addr_wb <= #1 set_addr_sync;
+ set_addr_wb_q <= #1 set_addr_wb;
+ end
+end
+
+
+// wb_cyc_o
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_cyc_o <= #1 1'b0;
+ else if ((start_wb_wr & (~start_wb_wr_q)) | (start_wb_rd & (~start_wb_rd_q)))
+ wb_cyc_o <= #1 1'b1;
+ else if (wb_ack_i | wb_err_i)
+ wb_cyc_o <= #1 1'b0;
+end
+
+
+// wb_adr_o logic
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_adr_o <= #1 32'h0;
+ else if (set_addr_wb & (~set_addr_wb_q)) // Setting starting address
+ wb_adr_o <= #1 adr;
+ else if (wb_ack_i)
+ begin
+ if ((rw_type == `WB_WRITE8) | (rw_type == `WB_READ8))
+ wb_adr_o <= #1 wb_adr_o + 1'd1;
+ else if ((rw_type == `WB_WRITE16) | (rw_type == `WB_READ16))
+ wb_adr_o <= #1 wb_adr_o + 2'd2;
+ else
+ wb_adr_o <= #1 wb_adr_o + 3'd4;
+ end
+end
+
+
+
+// adr byte | short | long
+// 0 1000 1100 1111
+// 1 0100 err err
+// 2 0010 0011 err
+// 3 0001 err err
+// wb_sel_o logic
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_sel_o[3:0] <= #1 4'h0;
+ else
+ begin
+ wb_sel_o[0] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b11) |
+ (rw_type[1:0] == 2'b10) & (wb_adr_o[1:0] == 2'b10);
+ wb_sel_o[1] <= #1 (rw_type[1:0] == 2'b11) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1] ^ rw_type[0]) & (wb_adr_o[1:0] == 2'b10);
+ wb_sel_o[2] <= #1 (rw_type[1]) & (wb_adr_o[1:0] == 2'b00) | (rw_type[1:0] == 2'b01) & (wb_adr_o[1:0] == 2'b01);
+ wb_sel_o[3] <= #1 (wb_adr_o[1:0] == 2'b00);
+ end
+end
+
+
+assign wb_we_o = write_cycle;
+assign wb_cab_o = 1'b0;
+assign wb_stb_o = wb_cyc_o;
+assign wb_cti_o = 3'h0; // always performing single access
+assign wb_bte_o = 2'h0; // always performing single access
+
+
+// Logic for detecting end of transaction
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_end <= #1 1'b0;
+ else if (wb_ack_i | wb_err_i)
+ wb_end <= #1 1'b1;
+ else if (wb_end_rst)
+ wb_end <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_end_sync <= #1 1'b0;
+ wb_end_tck <= #1 1'b0;
+ wb_end_tck_q<= #1 1'b0;
+ end
+ else
+ begin
+ wb_end_sync <= #1 wb_end;
+ wb_end_tck <= #1 wb_end_sync;
+ wb_end_tck_q<= #1 wb_end_tck;
+ end
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ busy_wb <= #1 1'b0;
+ else if (wb_end_rst)
+ busy_wb <= #1 1'b0;
+ else if (wb_cyc_o)
+ busy_wb <= #1 1'b1;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ busy_sync <= #1 1'b0;
+ busy_tck <= #1 1'b0;
+ end
+ else
+ begin
+ busy_sync <= #1 busy_wb;
+ busy_tck <= #1 busy_sync;
+ end
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_end_rst_sync <= #1 1'b0;
+ wb_end_rst <= #1 1'b0;
+ end
+ else
+ begin
+ wb_end_rst_sync <= #1 wb_end_tck;
+ wb_end_rst <= #1 wb_end_rst_sync;
+ end
+end
+
+
+// Detecting WB error
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_error <= #1 1'b0;
+ else if(wb_err_i)
+ wb_error <= #1 1'b1;
+ else if(wb_ack_i & status_reset_en) // error remains active until STATUS read is performed
+ wb_error <= #1 1'b0;
+end
+
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_error_sync <= #1 1'b0;
+ wb_error_tck <= #1 1'b0;
+ end
+ else
+ begin
+ wb_error_sync <= #1 wb_error;
+ wb_error_tck <= #1 wb_error_sync;
+ end
+end
+
+
+// Detecting overrun when write operation.
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ wb_overrun <= #1 1'b0;
+ else if(start_wb_wr & (~start_wb_wr_q) & wb_cyc_o)
+ wb_overrun <= #1 1'b1;
+ else if((wb_ack_i | wb_err_i) & status_reset_en) // error remains active until STATUS read is performed
+ wb_overrun <= #1 1'b0;
+end
+
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wb_overrun_sync <= #1 1'b0;
+ wb_overrun_tck <= #1 1'b0;
+ end
+ else
+ begin
+ wb_overrun_sync <= #1 wb_overrun;
+ wb_overrun_tck <= #1 wb_overrun_sync;
+ end
+end
+
+
+// Detecting underrun when read operation
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ underrun_tck <= #1 1'b0;
+ else if(latch_data & fifo_empty & (~data_cnt_end))
+ underrun_tck <= #1 1'b1;
+ else if(read_cycle & status_reset_en) // error remains active until STATUS read is performed
+ underrun_tck <= #1 1'b0;
+end
+
+
+
+// wb_error is locked until WB_STATUS is performed
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ status_reset_en <= 1'b0;
+ else if((cmd_old == `WB_STATUS) & (cmd !== `WB_STATUS))
+ status_reset_en <= #1 1'b1;
+ else
+ status_reset_en <= #1 1'b0;
+end
+
+
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ wishbone_ce_sync <= #1 1'b0;
+ wishbone_ce_rst <= #1 1'b0;
+ end
+ else
+ begin
+ wishbone_ce_sync <= #1 wishbone_ce_i;
+ wishbone_ce_rst <= #1 ~wishbone_ce_sync;
+ end
+end
+
+
+// Logic for latching data that is read from wishbone
+always @ (posedge wb_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ mem_ptr <= #1 3'h0;
+ else if(wishbone_ce_rst)
+ mem_ptr <= #1 3'h0;
+ else if (wb_ack_i)
+ begin
+ if (rw_type == `WB_READ8)
+ mem_ptr <= #1 mem_ptr + 1'd1;
+ else if (rw_type == `WB_READ16)
+ mem_ptr <= #1 mem_ptr + 2'd2;
+ end
+end
+
+
+// Logic for latching data that is read from wishbone
+always @ (posedge wb_clk_i)
+begin
+ if (wb_ack_i)
+ begin
+ case (wb_sel_o) // synthesis parallel_case full_case
+ 4'b1000 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24]; // byte
+ 4'b0100 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[23:16]; // byte
+ 4'b0010 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08]; // byte
+ 4'b0001 : mem[mem_ptr[1:0]] <= #1 wb_dat_i[07:00]; // byte
+
+ 4'b1100 : // half
+ begin
+ mem[mem_ptr[1:0]] <= #1 wb_dat_i[31:24];
+ mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[23:16];
+ end
+ 4'b0011 : // half
+ begin
+ mem[mem_ptr[1:0]] <= #1 wb_dat_i[15:08];
+ mem[mem_ptr[1:0]+1'b1] <= #1 wb_dat_i[07:00];
+ end
+ 4'b1111 : // long
+ begin
+ mem[0] <= #1 wb_dat_i[31:24];
+ mem[1] <= #1 wb_dat_i[23:16];
+ mem[2] <= #1 wb_dat_i[15:08];
+ mem[3] <= #1 wb_dat_i[07:00];
+ end
+ endcase
+ end
+end
+
+
+assign input_data = {mem[0], mem[1], mem[2], mem[3]};
+
+
+// Fifo counter and empty/full detection
+always @ (posedge tck_i or posedge rst_i)
+begin
+ if (rst_i)
+ fifo_cnt <= #1 3'h0;
+ else if (update_dr_i)
+ fifo_cnt <= #1 3'h0;
+ else if (wb_end_tck & (~wb_end_tck_q) & (~latch_data)) // incrementing
+ begin
+ case (rw_type) // synthesis parallel_case full_case
+ `WB_READ8 : fifo_cnt <= #1 fifo_cnt + 1'd1;
+ `WB_READ16: fifo_cnt <= #1 fifo_cnt + 2'd2;
+ `WB_READ32: fifo_cnt <= #1 fifo_cnt + 3'd4;
+ endcase
+ end
+ else if (~(wb_end_tck & (~wb_end_tck_q)) & latch_data) // decrementing
+ begin
+ case (rw_type) // synthesis parallel_case full_case
+ `WB_READ8 : fifo_cnt <= #1 fifo_cnt - 1'd1;
+ `WB_READ16: fifo_cnt <= #1 fifo_cnt - 2'd2;
+ `WB_READ32: fifo_cnt <= #1 fifo_cnt - 3'd4;
+ endcase
+ end
+end
+
+
+assign fifo_full = fifo_cnt == 3'h4;
+assign fifo_empty = fifo_cnt == 3'h0;
+
+
+
+
+endmodule
+
verilog/dbg_wb.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/dbg_cpu_registers.v
===================================================================
--- verilog/dbg_cpu_registers.v (nonexistent)
+++ verilog/dbg_cpu_registers.v (revision 158)
@@ -0,0 +1,242 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_cpu_registers.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2004/01/22 10:16:08 mohor
+// cpu_stall_o activated as soon as bp occurs.
+//
+// Revision 1.2 2004/01/17 17:01:14 mohor
+// Almost finished.
+//
+// Revision 1.1 2004/01/16 14:53:33 mohor
+// *** empty log message ***
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_cpu_defines.v"
+
+module dbg_cpu_registers (
+ data_i,
+ data_o,
+ addr_i,
+ we_i,
+ en_i,
+ clk_i,
+ bp_i,
+ rst_i,
+ cpu_clk_i,
+ cpu_stall_o,
+ cpu_stall_all_o,
+ cpu_sel_o,
+ cpu_rst_o
+ );
+
+
+input [7:0] data_i;
+input [1:0] addr_i;
+
+input we_i;
+input en_i;
+input clk_i;
+input bp_i;
+input rst_i;
+input cpu_clk_i;
+
+output [7:0] data_o;
+reg [7:0] data_o;
+
+output cpu_stall_o;
+output cpu_stall_all_o;
+output [`CPU_NUM -1:0] cpu_sel_o;
+output cpu_rst_o;
+
+wire cpu_stall_all;
+wire cpu_reset;
+wire [2:1] cpu_op_out;
+wire [`CPU_NUM -1:0] cpu_sel_out;
+
+wire cpuop_wr;
+wire cpusel_wr;
+
+reg cpusel_wr_sync, cpusel_wr_cpu;
+reg stall_bp, stall_bp_sync, stall_bp_tck;
+reg stall_reg, stall_reg_sync, stall_reg_cpu;
+reg cpu_stall_all_sync;
+reg cpu_stall_all_o;
+reg cpu_reset_sync;
+reg cpu_rst_o;
+
+
+
+assign cpuop_wr = en_i & we_i & (addr_i == `CPU_OP_ADR);
+assign cpusel_wr = en_i & we_i & (addr_i == `CPU_SEL_ADR);
+
+
+// Synchronising we for cpu_sel register that works in cpu_clk clock domain
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpusel_wr_sync <= #1 1'b0;
+ cpusel_wr_cpu <= #1 1'b0;
+ end
+ else
+ begin
+ cpusel_wr_sync <= #1 cpusel_wr;
+ cpusel_wr_cpu <= #1 cpusel_wr_sync;
+ end
+end
+
+
+// Breakpoint is latched and synchronized. Stall is set and latched.
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if(rst_i)
+ stall_bp <= #1 1'b0;
+ else if(bp_i)
+ stall_bp <= #1 1'b1;
+ else if(stall_reg_cpu)
+ stall_bp <= #1 1'b0;
+end
+
+
+// Synchronizing
+always @ (posedge clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ stall_bp_sync <= #1 1'b0;
+ stall_bp_tck <= #1 1'b0;
+ end
+ else
+ begin
+ stall_bp_sync <= #1 stall_bp;
+ stall_bp_tck <= #1 stall_bp_sync;
+ end
+end
+
+
+always @ (posedge clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ stall_reg <= #1 1'b0;
+ else if (stall_bp_tck)
+ stall_reg <= #1 1'b1;
+ else if (cpuop_wr)
+ stall_reg <= #1 data_i[0];
+end
+
+
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ stall_reg_sync <= #1 1'b0;
+ stall_reg_cpu <= #1 1'b0;
+ end
+ else
+ begin
+ stall_reg_sync <= #1 stall_reg;
+ stall_reg_cpu <= #1 stall_reg_sync;
+ end
+end
+
+
+assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
+
+
+
+dbg_register #(2, 0) CPUOP (.data_in(data_i[2:1]), .data_out(cpu_op_out[2:1]), .write(cpuop_wr), .clk(clk_i), .reset(rst_i));
+dbg_register #(`CPU_NUM, 0) CPUSEL (.data_in(data_i[`CPU_NUM-1:0]), .data_out(cpu_sel_out), .write(cpusel_wr_cpu), .clk(cpu_clk_i), .reset(rst_i)); // cpu_cli_i
+
+
+always @ (posedge clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ data_o <= #1 8'h0;
+ else
+ begin
+ case (addr_i) // Synthesis parallel_case
+ `CPU_OP_ADR : data_o <= #1 {5'h0, cpu_op_out[2:1], stall_reg};
+ `CPU_SEL_ADR : data_o <= #1 {{(8-`CPU_NUM){1'b0}}, cpu_sel_out};
+ default : data_o <= #1 8'h0;
+ endcase
+ end
+end
+
+
+assign cpu_stall_all = cpu_op_out[2]; // this signal is used to stall all the cpus except the one that is selected in cpusel register
+assign cpu_sel_o = cpu_sel_out;
+assign cpu_reset = cpu_op_out[1];
+
+
+
+
+// Synchronizing signals from registers
+always @ (posedge cpu_clk_i or posedge rst_i)
+begin
+ if (rst_i)
+ begin
+ cpu_stall_all_sync <= #1 1'b0;
+ cpu_stall_all_o <= #1 1'b0;
+ cpu_reset_sync <= #1 1'b0;
+ cpu_rst_o <= #1 1'b0;
+ end
+ else
+ begin
+ cpu_stall_all_sync <= #1 cpu_stall_all;
+ cpu_stall_all_o <= #1 cpu_stall_all_sync;
+ cpu_reset_sync <= #1 cpu_reset;
+ cpu_rst_o <= #1 cpu_reset_sync;
+ end
+end
+
+
+
+endmodule
+
Index: verilog/dbg_cpu_defines.v
===================================================================
--- verilog/dbg_cpu_defines.v (nonexistent)
+++ verilog/dbg_cpu_defines.v (revision 158)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_cpu_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2004 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2004/01/16 14:53:33 mohor
+// *** empty log message ***
+//
+//
+//
+
+
+// Defining commands for cpu module
+//`define CPU_STATUS 3'h0
+`define CPU_WRITE8 3'h1
+`define CPU_WRITE32 3'h2
+`define CPU_WRITE_REG 3'h3
+`define CPU_GO 3'h4
+`define CPU_READ8 3'h5
+`define CPU_READ32 3'h6
+`define CPU_READ_REG 3'h7
+
+
+
+
+
+// Number of supported cpus
+`define CPU_NUM 2
+
+
+// Registers addresses
+`define CPU_OP_ADR 2'd0
+`define CPU_SEL_ADR 2'd1
+
+
verilog/dbg_cpu_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/dbg_wb_defines.v
===================================================================
--- verilog/dbg_wb_defines.v (nonexistent)
+++ verilog/dbg_wb_defines.v (revision 158)
@@ -0,0 +1,72 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_wb_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2004/01/08 17:53:36 mohor
+// tmp version.
+//
+// Revision 1.2 2004/01/06 17:15:19 mohor
+// temp3 version.
+//
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+
+
+// Defining commands for wishbone
+`define WB_STATUS 3'h0
+`define WB_WRITE8 3'h1
+`define WB_WRITE16 3'h2
+`define WB_WRITE32 3'h3
+`define WB_GO 3'h4
+`define WB_READ8 3'h5
+`define WB_READ16 3'h6
+`define WB_READ32 3'h7
+
+
+// Length of status
+`define STATUS_LEN 4
+
verilog/dbg_wb_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/dbg_crc32_d1.v
===================================================================
--- verilog/dbg_crc32_d1.v (nonexistent)
+++ verilog/dbg_crc32_d1.v (revision 158)
@@ -0,0 +1,145 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbg_crc32_d1.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor (igorm@opencores.org) ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 - 2003 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// File: CRC32_D1.v
+// Date: Thu Nov 27 13:56:49 2003
+//
+// Copyright (C) 1999-2003 Easics NV.
+// This source file may be used and distributed without restriction
+// provided that this copyright statement is not removed from the file
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
+// * data width: 1
+//
+// Info: janz@easics.be (Jan Zegers)
+// http://www.easics.com
+///////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1 2003/12/23 15:09:04 mohor
+// New directory structure. New version of the debug interface.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
+
+input data;
+input enable;
+input shift;
+input rst;
+input sync_rst;
+input clk;
+
+
+output crc_out;
+output crc_match;
+
+reg [31:0] crc;
+
+wire [31:0] new_crc;
+
+
+assign new_crc[0] = data ^ crc[31];
+assign new_crc[1] = data ^ crc[0] ^ crc[31];
+assign new_crc[2] = data ^ crc[1] ^ crc[31];
+assign new_crc[3] = crc[2];
+assign new_crc[4] = data ^ crc[3] ^ crc[31];
+assign new_crc[5] = data ^ crc[4] ^ crc[31];
+assign new_crc[6] = crc[5];
+assign new_crc[7] = data ^ crc[6] ^ crc[31];
+assign new_crc[8] = data ^ crc[7] ^ crc[31];
+assign new_crc[9] = crc[8];
+assign new_crc[10] = data ^ crc[9] ^ crc[31];
+assign new_crc[11] = data ^ crc[10] ^ crc[31];
+assign new_crc[12] = data ^ crc[11] ^ crc[31];
+assign new_crc[13] = crc[12];
+assign new_crc[14] = crc[13];
+assign new_crc[15] = crc[14];
+assign new_crc[16] = data ^ crc[15] ^ crc[31];
+assign new_crc[17] = crc[16];
+assign new_crc[18] = crc[17];
+assign new_crc[19] = crc[18];
+assign new_crc[20] = crc[19];
+assign new_crc[21] = crc[20];
+assign new_crc[22] = data ^ crc[21] ^ crc[31];
+assign new_crc[23] = data ^ crc[22] ^ crc[31];
+assign new_crc[24] = crc[23];
+assign new_crc[25] = crc[24];
+assign new_crc[26] = data ^ crc[25] ^ crc[31];
+assign new_crc[27] = crc[26];
+assign new_crc[28] = crc[27];
+assign new_crc[29] = crc[28];
+assign new_crc[30] = crc[29];
+assign new_crc[31] = crc[30];
+
+
+always @ (posedge clk or posedge rst)
+begin
+ if(rst)
+ crc[31:0] <= #1 32'hffffffff;
+ else if(sync_rst)
+ crc[31:0] <= #1 32'hffffffff;
+ else if(enable)
+ crc[31:0] <= #1 new_crc;
+ else if (shift)
+ crc[31:0] <= #1 {crc[30:0], 1'b0};
+end
+
+
+assign crc_match = (crc == 32'h0);
+assign crc_out = crc[31];
+
+endmodule
verilog/dbg_crc32_d1.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/jtag_chain.v
===================================================================
--- verilog/jtag_chain.v (nonexistent)
+++ verilog/jtag_chain.v (revision 158)
@@ -0,0 +1,75 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// jtag_chain.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/projects/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000, 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "dbg_defines.v"
+
+// Top module
+module jtag_chain ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i,
+ bs_chain_i, bs_chain_o
+ );
+
+parameter Tp = 1;
+
+
+input capture_dr_i;
+input shift_dr_i;
+input update_dr_i;
+input extest_selected_i;
+input bs_chain_i;
+
+output bs_chain_o;
+
+assign bs_chain_o = 0;
+
+endmodule
Index: README.txt
===================================================================
--- README.txt (nonexistent)
+++ README.txt (revision 158)
@@ -0,0 +1,114 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// README.txt ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in this README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.2 2001/06/01 22:22:35 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.1 2001/05/18 13:12:09 mohor
+// Header changed. All additional information is now avaliable in this README.txt file.
+//
+//
+
+
+
+PROJECT:
+SoC/OpenRISC Development (debug) Interface
+
+
+PROJECT AND DOCUMENTATION ON THE WEB:
+
+The project that this files are part of is avaliable on the opencores
+web page:
+
+http://www.opencores.org/cores/DebugInterface/
+
+Documentation can also be found there. For direct download of the
+documentation go to:
+
+http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf
+
+
+
+
+OVERVIEW (main Features):
+
+Development Interface is used for development purposes
+(Boundary Scan testing and debugging). It is an interface
+between the RISC, peripheral cores and any commercial
+debugger/emulator or BS testing device. The external
+debugger or BS tester connects to the core via JTAG port.
+The Development Port also contains a trace and support for
+tracing the program flow, execution coverage and profiling
+the code.
+
+dbg_tb.v is a testbench file.
+file_communication.v is used for simulating the whole design together with the
+ debugger through two files that make a JTAG interface
+dbg_top.v is top level module of the development interface design
+
+
+
+COMPATIBILITY:
+
+- WISHBONE rev B.1
+- IEEE 1149.1 (JTAG)
+
+
+
+KNOWN PROBLEMS (limits):
+- RISC changes Watchpoints and breakpoints on rising edge of the
+Mclk clock signal. Simulation should do the same.
+
+
+
+TO DO:
+- Add a WISHBONE master support if needed
+- Add support for boundary scan (This is already done, but not yet incorporated in the design)
+