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/verilog/dbg_tb.v

/verilog/cpu_behavioral.v

/verilog/timescale.v

verilog/timescale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog/wb_slave_behavioral.v =================================================================== --- verilog/wb_slave_behavioral.v (nonexistent) +++ verilog/wb_slave_behavioral.v (revision 158) @@ -0,0 +1,407 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// wb_slave_behavioral.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Tadej Markovic, tadej@opencores.org //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.1 2003/12/23 14:26:01 mohor +// New version of the debug interface. Not finished, yet. +// +// +// +// + +`include "timescale.v" +`include "wb_model_defines.v" +module wb_slave_behavioral +( + CLK_I, + RST_I, + ACK_O, + ADR_I, + CYC_I, + DAT_O, + DAT_I, + ERR_O, + RTY_O, + SEL_I, + STB_I, + WE_I, + CAB_I +); + +/*------------------------------------------------------------------------------------------------------ +WISHBONE signals +------------------------------------------------------------------------------------------------------*/ +input CLK_I; +input RST_I; +output ACK_O; +input `WB_ADDR_TYPE ADR_I; +input CYC_I; +output `WB_DATA_TYPE DAT_O; +input `WB_DATA_TYPE DAT_I; +output ERR_O; +output RTY_O; +input `WB_SEL_TYPE SEL_I; +input STB_I; +input WE_I; +input CAB_I; + +reg `WB_DATA_TYPE DAT_O; + +/*------------------------------------------------------------------------------------------------------ +Asynchronous dual-port RAM signals for storing and fetching the data +------------------------------------------------------------------------------------------------------*/ +//reg `WB_DATA_TYPE wb_memory [0:16777215]; // WB memory - 24 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE wb_memory [0:1048575]; // WB memory - 20 addresses connected - 2 LSB not used +reg `WB_DATA_TYPE mem_wr_data_out; +reg `WB_DATA_TYPE mem_rd_data_in; + +/*------------------------------------------------------------------------------------------------------ +Maximum values for WAIT and RETRY counters and which response !!! +------------------------------------------------------------------------------------------------------*/ +reg [2:0] a_e_r_resp; // tells with which cycle_termination_signal must wb_slave respond ! +reg [8:0] wait_cyc; +reg [7:0] max_retry; + +// assign registers to default state while in reset +// always@(RST_I) +// begin +// if (RST_I) +// begin +// a_e_r_resp <= 3'b000; // do not respond +// wait_cyc <= 8'b0; // no wait cycles +// max_retry <= 8'h0; // no retries +// end +// end //reset + +task cycle_response; + input [2:0] ack_err_rty_resp; // acknowledge, error or retry response input flags + input [8:0] wait_cycles; // if wait cycles before each data termination cycle (ack, err or rty) + input [7:0] retry_cycles; // noumber of retry cycles before acknowledge cycle +begin + // assign values + a_e_r_resp <= #1 ack_err_rty_resp; + wait_cyc <= #1 wait_cycles; + max_retry <= #1 retry_cycles; +end +endtask // cycle_response + +/*------------------------------------------------------------------------------------------------------ +Tasks for writing and reading to and from memory !!! +------------------------------------------------------------------------------------------------------*/ +reg `WB_ADDR_TYPE task_wr_adr_i; +reg `WB_ADDR_TYPE task_rd_adr_i; +reg `WB_DATA_TYPE task_dat_i; +reg `WB_DATA_TYPE task_dat_o; +reg `WB_SEL_TYPE task_sel_i; +reg task_wr_data; +reg task_data_written; +reg `WB_DATA_TYPE task_mem_wr_data; + +// write to memory +task wr_mem; + input `WB_ADDR_TYPE adr_i; + input `WB_DATA_TYPE dat_i; + input `WB_SEL_TYPE sel_i; +begin + task_data_written = 0; + task_wr_adr_i = adr_i; + task_dat_i = dat_i; + task_sel_i = sel_i; + task_wr_data = 1; + wait(task_data_written); + task_wr_data = 0; +end +endtask + +// read from memory +task rd_mem; + input `WB_ADDR_TYPE adr_i; + output `WB_DATA_TYPE dat_o; + input `WB_SEL_TYPE sel_i; +begin + task_rd_adr_i = adr_i; + task_sel_i = sel_i; + #1; + dat_o = task_dat_o; +end +endtask + +/*------------------------------------------------------------------------------------------------------ +Internal signals and logic +------------------------------------------------------------------------------------------------------*/ +reg calc_ack; +reg calc_err; +reg calc_rty; + +reg [7:0] retry_cnt; +reg [7:0] retry_num; +reg retry_expired; + +// Retry counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + retry_cnt <= #1 8'h00; + else + begin + if (calc_ack || calc_err) + retry_cnt <= #1 8'h00; + else if (calc_rty) + retry_cnt <= #1 retry_num; + end +end + +always@(retry_cnt or max_retry) +begin + if (retry_cnt < max_retry) + begin + retry_num = retry_cnt + 1'b1; + retry_expired = 1'b0; + end + else + begin + retry_num = retry_cnt; + retry_expired = 1'b1; + end +end + +reg [8:0] wait_cnt; +reg [8:0] wait_num; +reg wait_expired; + +// Wait counter +always@(posedge RST_I or posedge CLK_I) +begin + if (RST_I) + wait_cnt <= #1 9'h0; + else + begin + if (wait_expired || ~STB_I) + wait_cnt <= #1 9'h0; + else + wait_cnt <= #1 wait_num; + end +end + +always@(wait_cnt or wait_cyc or STB_I or a_e_r_resp or retry_expired) +begin + if ((wait_cyc > 0) && (STB_I)) + begin + if (wait_cnt < wait_cyc) + begin + wait_num = wait_cnt + 1'b1; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + begin + wait_num = wait_cnt; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else + if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + end + else + if ((wait_cyc == 0) && (STB_I)) + begin + wait_num = 9'h0; + wait_expired = 1'b1; + if (a_e_r_resp == 3'b100) + begin + calc_ack = 1'b1; + calc_err = 1'b0; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b010) + begin + calc_ack = 1'b0; + calc_err = 1'b1; + calc_rty = 1'b0; + end + else if (a_e_r_resp == 3'b001) + begin + calc_err = 1'b0; + if (retry_expired) + begin + calc_ack = 1'b1; + calc_rty = 1'b0; + end + else + begin + calc_ack = 1'b0; + calc_rty = 1'b1; + end + end + else + begin + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end + end + else + begin + wait_num = 9'h0; + wait_expired = 1'b0; + calc_ack = 1'b0; + calc_err = 1'b0; + calc_rty = 1'b0; + end +end + +wire rd_sel = (CYC_I && STB_I && ~WE_I); +wire wr_sel = (CYC_I && STB_I && WE_I); + +// Generate cycle termination signals +assign ACK_O = calc_ack && STB_I; +assign ERR_O = calc_err && STB_I; +assign RTY_O = calc_rty && STB_I; + +// Assign address to asynchronous memory +always@(RST_I or ADR_I) +begin + if (RST_I) // this is added because at start of test bench we need address change in order to get data! + begin + #1 mem_rd_data_in = `WB_DATA_WIDTH'hxxxx_xxxx; + end + else + begin +// #1 mem_rd_data_in = wb_memory[ADR_I[25:2]]; + #1 mem_rd_data_in = wb_memory[ADR_I[21:2]]; + end +end + +// Data input/output interface +always@(rd_sel or mem_rd_data_in or RST_I) +begin + if (RST_I) + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; // assign outputs to unknown state while in reset + else if (rd_sel) + DAT_O <=#1 mem_rd_data_in; + else + DAT_O <=#1 `WB_DATA_WIDTH'hxxxx_xxxx; +end + + +always@(RST_I or task_rd_adr_i) +begin + if (RST_I) + task_dat_o = `WB_DATA_WIDTH'hxxxx_xxxx; + else + task_dat_o = wb_memory[task_rd_adr_i[21:2]]; +end +always@(CLK_I or wr_sel or task_wr_data or ADR_I or task_wr_adr_i or + mem_wr_data_out or DAT_I or task_mem_wr_data or task_dat_i or + SEL_I or task_sel_i) +begin + if (task_wr_data) + begin + task_mem_wr_data = wb_memory[task_wr_adr_i[21:2]]; + + if (task_sel_i[3]) + task_mem_wr_data[31:24] = task_dat_i[31:24]; + if (task_sel_i[2]) + task_mem_wr_data[23:16] = task_dat_i[23:16]; + if (task_sel_i[1]) + task_mem_wr_data[15: 8] = task_dat_i[15: 8]; + if (task_sel_i[0]) + task_mem_wr_data[ 7: 0] = task_dat_i[ 7: 0]; + + wb_memory[task_wr_adr_i[21:2]] = task_mem_wr_data; // write data + task_data_written = 1; + end + else if (wr_sel && CLK_I) + begin +// mem_wr_data_out = wb_memory[ADR_I[25:2]]; // if no SEL_I is active, old value will be written + mem_wr_data_out = wb_memory[ADR_I[21:2]]; // if no SEL_I is active, old value will be written + + if (SEL_I[3]) + mem_wr_data_out[31:24] = DAT_I[31:24]; + if (SEL_I[2]) + mem_wr_data_out[23:16] = DAT_I[23:16]; + if (SEL_I[1]) + mem_wr_data_out[15: 8] = DAT_I[15: 8]; + if (SEL_I[0]) + mem_wr_data_out[ 7: 0] = DAT_I[ 7: 0]; + +// wb_memory[ADR_I[25:2]] <= mem_wr_data_out; // write data + wb_memory[ADR_I[21:2]] = mem_wr_data_out; // write data + end +end + +endmodule Index: verilog/dbg_tb_defines.v =================================================================== --- verilog/dbg_tb_defines.v (nonexistent) +++ verilog/dbg_tb_defines.v (revision 158) @@ -0,0 +1,171 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_tb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// Igor Mohor (igorm@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/09/18 14:12:43 mohor +// Trace fixed. Some registers changed, trace simplified. +// +// Revision 1.1.1.1 2001/09/13 13:49:19 mohor +// Initial official release. +// +// Revision 1.3 2001/06/01 22:23:40 mohor +// This is a backup. It is not a fully working version. Not for use, yet. +// +// Revision 1.2 2001/05/18 13:10:05 mohor +// Headers changed. All additional information is now avaliable in the README.txt file. +// +// Revision 1.1.1.1 2001/05/18 06:35:12 mohor +// Initial release +// +// + +// Following defines are used in the testbench only + + // MODER register + `define ENABLE 32'h00010000 + `define CONTIN 32'h00020000 + + // TSEL register + `define WPTRIG_0 32'h00000001 + `define WPTRIG_1 32'h00000002 + `define WPTRIG_2 32'h00000004 + `define WPTRIG_3 32'h00000008 + `define WPTRIG_4 32'h00000010 + `define WPTRIG_5 32'h00000020 + `define WPTRIG_6 32'h00000040 + `define WPTRIG_7 32'h00000080 + `define WPTRIG_8 32'h00000100 + `define WPTRIG_9 32'h00000200 + `define WPTRIG_10 32'h00000400 + `define WPTRIGVALID 32'h00000800 + + `define BPTRIG 32'h00001000 + `define BPTRIGVALID 32'h00002000 + + `define LSSTRIG_0 32'h00010000 + `define LSSTRIG_1 32'h00020000 + `define LSSTRIG_2 32'h00040000 + `define LSSTRIG_3 32'h00080000 + `define LSSTRIGVALID 32'h00100000 + + `define ISTRIGVALID 32'h00800000 + + `define TRIGOP_AND 32'hc0000000 + `define TRIGOP_OR 32'h80000000 + + // QSEL register + `define WPQUALIF_0 32'h00000001 + `define WPQUALIF_1 32'h00000002 + `define WPQUALIF_2 32'h00000004 + `define WPQUALIF_3 32'h00000008 + `define WPQUALIF_4 32'h00000010 + `define WPQUALIF_5 32'h00000020 + `define WPQUALIF_6 32'h00000040 + `define WPQUALIF_7 32'h00000080 + `define WPQUALIF_8 32'h00000100 + `define WPQUALIF_9 32'h00000200 + `define WPQUALIF_10 32'h00000400 + `define WPQUALIFVALID 32'h00000800 + + `define BPQUALIF 32'h00001000 + `define BPQUALIFVALID 32'h00002000 + + `define LSSQUALIF_0 32'h00010000 + `define LSSQUALIF_1 32'h00020000 + `define LSSQUALIF_2 32'h00040000 + `define LSSQUALIF_3 32'h00080000 + `define LSSQUALIFVALID 32'h00100000 + + `define ISQUALIFVALID 32'h00800000 + + `define QUALIFOP_AND 32'hc0000000 + `define QUALIFOP_OR 32'h80000000 + + + // SSEL register + `define WPSTOP_0 32'h00000001 + `define WPSTOP_1 32'h00000002 + `define WPSTOP_2 32'h00000004 + `define WPSTOP_3 32'h00000008 + `define WPSTOP_4 32'h00000010 + `define WPSTOP_5 32'h00000020 + `define WPSTOP_6 32'h00000040 + `define WPSTOP_7 32'h00000080 + `define WPSTOP_8 32'h00000100 + `define WPSTOP_9 32'h00000200 + `define WPSTOP_10 32'h00000400 + `define WPSTOPVALID 32'h00000800 + + `define BPSTOP 32'h00001000 + `define BPSTOPVALID 32'h00002000 + + `define LSSSTOP_0 32'h00010000 + `define LSSSTOP_1 32'h00020000 + `define LSSSTOP_2 32'h00040000 + `define LSSSTOP_3 32'h00080000 + `define LSSSTOPVALID 32'h00100000 + + `define ISSTOPVALID 32'h00800000 + + `define STOPOP_AND 32'hc0000000 + `define STOPOP_OR 32'h80000000 + + `define IS_NO_FETCH 32'h00000000 + `define IS_FETCH 32'h00200000 + `define IS_BRANCH 32'h00400000 + `define IS_FETCH_DELAY 32'h00600000 + + `define LSS_NO_LOADSTORE 32'h00000000 + `define LSS_LOADBYTE_ZEROEXT 32'h00020000 + `define LSS_LOADBYTE_SIGNEXT 32'h00030000 + `define LSS_LOADHALF_ZEROEXT 32'h00040000 + `define LSS_LOADHALF_SIGNEXT 32'h00050000 + `define LSS_LOADWORD_ZEROEXT 32'h00060000 + `define LSS_LOADWORD_SIGNEXT 32'h00070000 + `define LSS_STORE_BYTE 32'h000A0000 + `define LSS_STORE_HALF 32'h000C0000 + +// End: Following defines are used in the testbench only + + Index: verilog/wb_model_defines.v =================================================================== --- verilog/wb_model_defines.v (nonexistent) +++ verilog/wb_model_defines.v (revision 158) @@ -0,0 +1,148 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// dbg_tb_defines.v //// +//// //// +//// //// +//// This file is part of the SoC/OpenRISC Development Interface //// +//// http://www.opencores.org/projects/DebugInterface/ //// +//// //// +//// Author(s): //// +//// - Miha Dolenc (mihad@opencores.org) //// +//// //// +//// //// +//// All additional information is avaliable in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 - 2003 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// +// + +// WISHBONE frequency in GHz +`define WB_FREQ 0.100 + +// memory frequency in GHz +`define MEM_FREQ 0.100 + +// setup and hold time definitions for WISHBONE - used in BFMs for signal generation +`define Tsetup 4 +`define Thold 1 + +// how many clock cycles should model wait for design's response - integer 32 bit value +`define WAIT_FOR_RESPONSE 1023 + +// maximum number of transactions allowed in single call to block or cab transfer routines +`define MAX_BLK_SIZE 1024 + +// maximum retry terminations allowed for WISHBONE master to repeat an access +`define WB_TB_MAX_RTY 0 + + +// some common types and defines +`define WB_ADDR_WIDTH 32 +`define WB_DATA_WIDTH 32 +`define WB_SEL_WIDTH `WB_DATA_WIDTH/8 +`define WB_TAG_WIDTH 5 +`define WB_ADDR_TYPE [(`WB_ADDR_WIDTH - 1):0] +`define WB_DATA_TYPE [(`WB_DATA_WIDTH - 1):0] +`define WB_SEL_TYPE [(`WB_SEL_WIDTH - 1):0] +`define WB_TAG_TYPE [(`WB_TAG_WIDTH - 1):0] + +// read cycle stimulus - consists of: +// - address field - which address read will be performed from +// - sel field - what byte select value should be +// - tag field - what tag values should be put on the bus +`define READ_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) +`define READ_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define READ_SEL [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH - 1):`WB_ADDR_WIDTH] +`define READ_TAG_STIM [(`WB_ADDR_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_SEL_WIDTH)] + +// read cycle return type consists of: +// - read data field +// - tag field received from WISHBONE +// - wishbone slave response fields - ACK, ERR and RTY +// - test bench error indicator (when testcase has not used wb master model properly) +// - how much data was actually transfered +`define READ_RETURN_TYPE [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):0] +`define READ_DATA [(32 + `WB_DATA_WIDTH + 4 - 1):32 + 4] +`define READ_TAG_RET [(32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1):(`WB_DATA_WIDTH + 32 + 4)] +`define READ_RETURN_LENGTH (32 + 4 + `WB_DATA_WIDTH + `WB_TAG_WIDTH - 1) + +// write cycle stimulus type consists of +// - address field +// - data field +// - sel field +// - tag field +`define WRITE_STIM_TYPE [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):0] +`define WRITE_ADDRESS [(`WB_ADDR_WIDTH - 1):0] +`define WRITE_DATA [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH - 1):`WB_ADDR_WIDTH] +`define WRITE_SEL [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH)] +`define WRITE_TAG_STIM [(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH - 1):(`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH)] + +// length of WRITE_STIMULUS +`define WRITE_STIM_LENGTH (`WB_ADDR_WIDTH + `WB_DATA_WIDTH + `WB_SEL_WIDTH + `WB_TAG_WIDTH) + +// write cycle return type consists of: +// - test bench error indicator (when testcase has not used wb master model properly) +// - wishbone slave response fields - ACK, ERR and RTY +// - tag field received from WISHBONE +// - how much data was actually transfered +`define WRITE_RETURN_TYPE [(32 + 4 + `WB_TAG_WIDTH - 1):0] +`define WRITE_TAG_RET [(32 + 4 + `WB_TAG_WIDTH - 1):32 + 4] + +// this four fields are common to both read and write routines return values +`define TB_ERROR_BIT [0] +`define CYC_ACK [1] +`define CYC_RTY [2] +`define CYC_ERR [3] +`define CYC_RESPONSE [3:1] +`define CYC_ACTUAL_TRANSFER [35:4] + +// block transfer flags +`define WB_TRANSFER_FLAGS [41:0] +// consists of: +// - number of transfer cycles to perform +// - flag that enables retry termination handling - if disabled, block transfer routines will return on any termination other than acknowledge +// - flag indicating CAB transfer is to be performed - ignored by all single transfer routines +// - number of initial wait states to insert +// - number of subsequent wait states to insert +`define WB_TRANSFER_SIZE [41:10] +`define WB_TRANSFER_AUTO_RTY [8] +`define WB_TRANSFER_CAB [9] +`define INIT_WAITS [3:0] +`define SUBSEQ_WAITS [7:4] + +// wb slave response +`define ACK_RESPONSE 3'b100 +`define ERR_RESPONSE 3'b010 +`define RTY_RESPONSE 3'b001 +`define NO_RESPONSE 3'b000