URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/dbg_interface/tags/rel_6/sim
- from Rev 64 to Rev 158
- ↔ Reverse comparison
Rev 64 → Rev 158
/rtl_sim/run/do.do
0,0 → 1,24
#write format wave -window .wave C:/cvsroot/ethernet/sim/rtl_sim/run/wave.do |
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vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/bench/verilog/dbg_tb_defines.v} |
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/timescale.v} |
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_crc8_d1.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_defines.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/tap_top.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/jtag_chain.v} |
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vsim work.dbg_tb |
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add wave -r -hexadecimal /* |
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#do C:/cvsroot/ethernet/sim/rtl_sim/run/wave.do |
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run -all |
.wave.tree zoomfull |
/rtl_sim/run/file.do
0,0 → 1,26
vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_crc8_d1.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_defines.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v} |
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vlog -reportprogress 300 -work work {C:/cvsroot/dbg_interface/bench/verilog/file_communication.v} |
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vsim work.File_communication |
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add wave -r -hexadecimal /* |
.wave.tree zoomfull |
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#vsim work.File_communication |
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run -all |