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Rev 49 → Rev 158

/verilog/dbg_top.v
0,0 → 1,978
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_top.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.25 2002/04/22 12:54:11 mohor
// Signal names changed to lower case.
//
// Revision 1.24 2002/04/17 13:17:01 mohor
// Intentional error removed.
//
// Revision 1.23 2002/04/17 11:16:33 mohor
// A block for checking possible simulation/synthesis missmatch added.
//
// Revision 1.22 2002/03/12 10:31:53 mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.21 2002/03/08 15:28:16 mohor
// Structure changed. Hooks for jtag chain added.
//
// Revision 1.20 2002/02/06 12:23:09 mohor
// LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.
//
// Revision 1.19 2002/02/05 13:34:51 mohor
// Stupid bug that was entered by previous update fixed.
//
// Revision 1.18 2002/02/05 12:41:01 mohor
// trst synchronization is not needed and was removed.
//
// Revision 1.17 2002/01/25 07:58:35 mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.16 2001/12/20 11:17:26 mohor
// TDO and TDO Enable signal are separated into two signals.
//
// Revision 1.15 2001/12/05 13:28:21 mohor
// trst signal is synchronized to wb_clk_i.
//
// Revision 1.14 2001/11/28 09:36:15 mohor
// Register length fixed.
//
// Revision 1.13 2001/11/27 13:37:43 mohor
// CRC is returned when chain selection data is transmitted.
//
// Revision 1.12 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.11 2001/11/14 10:10:41 mohor
// Wishbone data latched on wb_clk_i instead of risc_clk.
//
// Revision 1.10 2001/11/12 01:11:27 mohor
// Reset signals are not combined any more.
//
// Revision 1.9 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.8 2001/10/17 10:39:03 mohor
// bs_chain_o added.
//
// Revision 1.7 2001/10/16 10:09:56 mohor
// Signal names changed to lowercase.
//
//
// Revision 1.6 2001/10/15 09:55:47 mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.5 2001/09/24 14:06:42 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.4 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3 2001/09/19 11:55:13 mohor
// Asynchronous set/reset not used in trace any more.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:02 mohor
// Initial release
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module dbg_top(
// RISC signals
risc_clk_i, risc_addr_o, risc_data_i, risc_data_o, wp_i,
bp_i, opselect_o, lsstatus_i, istatus_i, risc_stall_o, reset_o,
// WISHBONE common signals
wb_rst_i, wb_clk_i,
 
// WISHBONE master interface
wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
wb_we_o, wb_ack_i, wb_cab_o, wb_err_i,
 
// TAP states
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q,
// Instructions
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected,
// TAP signals
trst_in, tck, tdi, TDOData,
BypassRegister,
// Monitor mux control
mon_cntl_o
 
);
 
parameter Tp = 1;
 
 
// RISC signals
input risc_clk_i; // Master clock (RISC clock)
input [31:0] risc_data_i; // RISC data inputs (data that is written to the RISC registers)
input [10:0] wp_i; // Watchpoint inputs
input bp_i; // Breakpoint input
input [3:0] lsstatus_i; // Load/store status inputs
input [1:0] istatus_i; // Instruction status inputs
output [31:0] risc_addr_o; // RISC address output (for adressing registers within RISC)
output [31:0] risc_data_o; // RISC data output (data read from risc registers)
output [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
output risc_stall_o; // Stalls the RISC
output reset_o; // Resets the RISC
 
 
// WISHBONE common signals
input wb_rst_i; // WISHBONE reset
input wb_clk_i; // WISHBONE clock
 
// WISHBONE master interface
output [31:0] wb_adr_o;
output [31:0] wb_dat_o;
input [31:0] wb_dat_i;
output wb_cyc_o;
output wb_stb_o;
output [3:0] wb_sel_o;
output wb_we_o;
input wb_ack_i;
output wb_cab_o;
input wb_err_i;
 
// TAP states
input ShiftDR;
input Exit1DR;
input UpdateDR;
input UpdateDR_q;
 
input trst_in;
input tck;
input tdi;
 
input BypassRegister;
 
output TDOData;
output [3:0] mon_cntl_o;
 
// Defining which instruction is selected
input IDCODESelected;
input CHAIN_SELECTSelected;
input DEBUGSelected;
 
reg wb_cyc_o;
 
reg [31:0] ADDR;
reg [31:0] DataOut;
 
reg [`OPSELECTWIDTH-1:0] opselect_o; // Operation selection (selecting what kind of data is set to the risc_data_i)
 
reg [`CHAIN_ID_LENGTH-1:0] Chain; // Selected chain
reg [31:0] DataReadLatch; // Data when reading register or RISC is latched one risc_clk_i clock after the data is read.
reg RegAccessTck; // Indicates access to the registers (read or write)
reg RISCAccessTck; // Indicates access to the RISC (read or write)
reg [7:0] BitCounter; // Counting bits in the ShiftDR and Exit1DR stages
reg RW; // Read/Write bit
reg CrcMatch; // The crc that is shifted in and the internaly calculated crc are equal
 
reg RegAccess_q; // Delayed signals used for accessing the registers
reg RegAccess_q2; // Delayed signals used for accessing the registers
reg RISCAccess_q; // Delayed signals used for accessing the RISC
reg RISCAccess_q2; // Delayed signals used for accessing the RISC
 
reg wb_AccessTck; // Indicates access to the WISHBONE
reg [31:0] WBReadLatch; // Data latched during WISHBONE read
reg WBErrorLatch; // Error latched during WISHBONE read
 
wire trst;
 
 
wire [31:0] RegDataIn; // Data from registers (read data)
wire [`CRC_LENGTH-1:0] CalculatedCrcOut; // CRC calculated in this module. This CRC is apended at the end of the TDO.
 
wire RiscStall_reg; // RISC is stalled by setting the register bit
wire RiscReset_reg; // RISC is reset by setting the register bit
wire RiscStall_trace; // RISC is stalled by trace module
wire RegisterScanChain; // Register Scan chain selected
wire RiscDebugScanChain; // Risc Debug Scan chain selected
wire WishboneScanChain; // WISHBONE Scan chain selected
 
wire RiscStall_read_access; // Stalling RISC because of the read access (SPR read)
wire RiscStall_write_access; // Stalling RISC because of the write access (SPR write)
wire RiscStall_access; // Stalling RISC because of the read or write access
 
wire BitCounter_Lt4;
wire BitCounter_Eq5;
wire BitCounter_Eq32;
wire BitCounter_Lt38;
wire BitCounter_Lt65;
 
 
 
// This signals are used only when TRACE is used in the design
`ifdef TRACE_ENABLED
wire [39:0] TraceChain; // Chain that comes from trace module
reg ReadBuffer_Tck; // Command for incrementing the trace read pointer (synchr with tck)
wire ReadTraceBuffer; // Command for incrementing the trace read pointer (synchr with MClk)
reg ReadTraceBuffer_q; // Delayed command for incrementing the trace read pointer (synchr with MClk)
wire ReadTraceBufferPulse; // Pulse for reading the trace buffer (valid for only one Mclk command)
 
// Outputs from registers
wire ContinMode; // Trace working in continous mode
wire TraceEnable; // Trace enabled
wire [10:0] WpTrigger; // Watchpoint starts trigger
wire BpTrigger; // Breakpoint starts trigger
wire [3:0] LSSTrigger; // Load/store status starts trigger
wire [1:0] ITrigger; // Instruction status starts trigger
wire [1:0] TriggerOper; // Trigger operation
wire WpTriggerValid; // Watchpoint trigger is valid
wire BpTriggerValid; // Breakpoint trigger is valid
wire LSSTriggerValid; // Load/store status trigger is valid
wire ITriggerValid; // Instruction status trigger is valid
wire [10:0] WpQualif; // Watchpoint starts qualifier
wire BpQualif; // Breakpoint starts qualifier
wire [3:0] LSSQualif; // Load/store status starts qualifier
wire [1:0] IQualif; // Instruction status starts qualifier
wire [1:0] QualifOper; // Qualifier operation
wire WpQualifValid; // Watchpoint qualifier is valid
wire BpQualifValid; // Breakpoint qualifier is valid
wire LSSQualifValid; // Load/store status qualifier is valid
wire IQualifValid; // Instruction status qualifier is valid
wire [10:0] WpStop; // Watchpoint stops recording of the trace
wire BpStop; // Breakpoint stops recording of the trace
wire [3:0] LSSStop; // Load/store status stops recording of the trace
wire [1:0] IStop; // Instruction status stops recording of the trace
wire [1:0] StopOper; // Stop operation
wire WpStopValid; // Watchpoint stop is valid
wire BpStopValid; // Breakpoint stop is valid
wire LSSStopValid; // Load/store status stop is valid
wire IStopValid; // Instruction status stop is valid
wire RecordPC; // Recording program counter
wire RecordLSEA; // Recording load/store effective address
wire RecordLDATA; // Recording load data
wire RecordSDATA; // Recording store data
wire RecordReadSPR; // Recording read SPR
wire RecordWriteSPR; // Recording write SPR
wire RecordINSTR; // Recording instruction
// End: Outputs from registers
 
wire TraceTestScanChain; // Trace Test Scan chain selected
wire [47:0] Trace_Data; // Trace data
 
wire [`OPSELECTWIDTH-1:0]opselect_trace;// Operation selection (trace selecting what kind of
// data is set to the risc_data_i)
wire BitCounter_Lt40;
 
`endif
 
 
assign trst = ~trst_in; // trst_pad_i is active low
 
 
/**********************************************************************************
* *
* JTAG_DR: JTAG Data Register *
* *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
reg TDOData;
 
 
always @ (posedge tck or posedge trst)
begin
if(trst)
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
else
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
begin
if(ShiftDR)
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
else
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
end
else
if(CHAIN_SELECTSelected & ShiftDR)
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
else
if(DEBUGSelected & ShiftDR)
begin
if(RiscDebugScanChain | WishboneScanChain)
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
else
if(RegisterScanChain)
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
end
end
wire [73:0] RISC_Data;
wire [46:0] Register_Data;
wire [73:0] WISHBONE_Data;
wire [12:0] chain_sel_data;
wire wb_Access_wbClk;
 
 
reg select_crc_out;
always @ (posedge tck or posedge trst)
begin
if(trst)
select_crc_out <= 0;
else
if( RegisterScanChain & BitCounter_Eq5 |
RiscDebugScanChain & BitCounter_Eq32 |
WishboneScanChain & BitCounter_Eq32 )
select_crc_out <=#Tp tdi;
else
if(CHAIN_SELECTSelected)
select_crc_out <=#Tp 1;
else
if(UpdateDR)
select_crc_out <=#Tp 0;
end
 
wire [8:0] send_crc;
 
assign send_crc = select_crc_out? {9{BypassRegister}} : // Calculated CRC is returned when read operation is
{CalculatedCrcOut, 1'b0} ; // performed, else received crc is returned (loopback).
 
assign RISC_Data = {send_crc, DataReadLatch, 33'h0};
assign Register_Data = {send_crc, DataReadLatch, 6'h0};
assign WISHBONE_Data = {send_crc, WBReadLatch, 32'h0, WBErrorLatch};
assign chain_sel_data = {send_crc, 4'h0};
`ifdef TRACE_ENABLED
assign Trace_Data = {CalculatedCrcOut, TraceChain};
`endif
 
//TDO is changing on the falling edge of tck
always @ (negedge tck or posedge trst)
begin
if(trst)
begin
TDOData <= #Tp 0;
`ifdef TRACE_ENABLED
ReadBuffer_Tck<=#Tp 0;
`endif
end
else
if(UpdateDR)
begin
TDOData <= #Tp CrcMatch;
`ifdef TRACE_ENABLED
if(DEBUGSelected & TraceTestScanChain & TraceChain[0]) // Sample in the trace buffer is valid
ReadBuffer_Tck<=#Tp 1; // Increment read pointer
`endif
end
else
begin
if(ShiftDR)
begin
if(IDCODESelected)
TDOData <= #Tp JTAG_DR_IN[0]; // IDCODE is shifted out 32-bits, then tdi is bypassed
else
if(CHAIN_SELECTSelected)
TDOData <= #Tp chain_sel_data[BitCounter]; // Received crc is sent back
else
if(DEBUGSelected)
begin
if(RiscDebugScanChain)
TDOData <= #Tp RISC_Data[BitCounter]; // Data read from RISC in the previous cycle is shifted out
else
if(RegisterScanChain)
TDOData <= #Tp Register_Data[BitCounter]; // Data read from register in the previous cycle is shifted out
else
if(WishboneScanChain)
TDOData <= #Tp WISHBONE_Data[BitCounter]; // Data read from the WISHBONE slave
`ifdef TRACE_ENABLED
else
if(TraceTestScanChain)
TDOData <= #Tp Trace_Data[BitCounter]; // Data from the trace buffer is shifted out
`endif
end
end
else
begin
TDOData <= #Tp 0;
`ifdef TRACE_ENABLED
ReadBuffer_Tck<=#Tp 0;
`endif
end
end
end
 
 
//synopsys translate_off
always @ (posedge tck)
begin
if(ShiftDR & CHAIN_SELECTSelected & BitCounter > 12)
begin
$display("\n%m Error: BitCounter is bigger then chain_sel_data bits width[12:0]. BitCounter=%d\n",BitCounter);
$stop;
end
else
if(ShiftDR & DEBUGSelected)
begin
if(RiscDebugScanChain & BitCounter > 73)
begin
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
$stop;
end
else
if(RegisterScanChain & BitCounter > 46)
begin
$display("\n%m Error: BitCounter is bigger then RISC_Data bits width[46:0]. BitCounter=%d\n",BitCounter);
$stop;
end
else
if(WishboneScanChain & BitCounter > 73)
begin
$display("\n%m Error: BitCounter is bigger then WISHBONE_Data bits width[73:0]. BitCounter=%d\n",BitCounter);
$stop;
end
`ifdef TRACE_ENABLED
else
if(TraceTestScanChain & BitCounter > 47)
begin
$display("\n%m Error: BitCounter is bigger then Trace_Data bits width[47:0]. BitCounter=%d\n",BitCounter);
$stop;
end
`endif
end
end
// synopsys translate_on
 
 
 
 
 
 
 
 
/**********************************************************************************
* *
* End: JTAG_DR *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* CHAIN_SELECT logic *
* *
**********************************************************************************/
always @ (posedge tck or posedge trst)
begin
if(trst)
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp `GLOBAL_BS_CHAIN; // Global BS chain is selected after reset
else
if(UpdateDR & CHAIN_SELECTSelected & CrcMatch)
Chain[`CHAIN_ID_LENGTH-1:0]<=#Tp JTAG_DR_IN[3:0]; // New chain is selected
end
 
 
 
/**********************************************************************************
* *
* Register read/write logic *
* RISC registers read/write logic *
* *
**********************************************************************************/
always @ (posedge tck or posedge trst)
begin
if(trst)
begin
ADDR[31:0] <=#Tp 32'h0;
DataOut[31:0] <=#Tp 32'h0;
RW <=#Tp 1'b0;
RegAccessTck <=#Tp 1'b0;
RISCAccessTck <=#Tp 1'b0;
wb_AccessTck <=#Tp 1'h0;
end
else
if(UpdateDR & DEBUGSelected & CrcMatch)
begin
if(RegisterScanChain)
begin
ADDR[4:0] <=#Tp JTAG_DR_IN[4:0]; // Latching address for register access
RW <=#Tp JTAG_DR_IN[5]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[37:6]; // latch data for write
RegAccessTck <=#Tp 1'b1;
end
else
if(RiscDebugScanChain)
begin
ADDR[31:0] <=#Tp JTAG_DR_IN[31:0]; // Latching address for RISC register access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut[31:0] <=#Tp JTAG_DR_IN[64:33]; // latch data for write
RISCAccessTck <=#Tp 1'b1;
end
else
if(WishboneScanChain)
begin
ADDR <=#Tp JTAG_DR_IN[31:0]; // Latching address for WISHBONE slave access
RW <=#Tp JTAG_DR_IN[32]; // latch R/W bit
DataOut <=#Tp JTAG_DR_IN[64:33]; // latch data for write
wb_AccessTck <=#Tp 1'b1; //
end
end
else
begin
RegAccessTck <=#Tp 1'b0; // This signals are valid for one tck clock period only
RISCAccessTck <=#Tp 1'b0;
wb_AccessTck <=#Tp 1'b0;
end
end
 
 
assign wb_adr_o = ADDR;
assign wb_we_o = RW;
assign wb_dat_o = DataOut;
assign wb_sel_o[3:0] = 4'hf;
assign wb_cab_o = 1'b0;
// Synchronizing the RegAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn1 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RegAccessTck), .sync_out(RegAccess)
);
 
// Synchronizing the RISCAccess signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn2 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(RISCAccessTck), .sync_out(RISCAccess)
);
 
 
// Synchronizing the wb_Access signal to wishbone clock
dbg_sync_clk1_clk2 syn3 (.clk1(wb_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(wb_AccessTck), .sync_out(wb_Access_wbClk)
);
 
 
 
 
 
// Delayed signals used for accessing registers and RISC
always @ (posedge risc_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RegAccess_q <=#Tp 1'b0;
RegAccess_q2 <=#Tp 1'b0;
RISCAccess_q <=#Tp 1'b0;
RISCAccess_q2 <=#Tp 1'b0;
end
else
begin
RegAccess_q <=#Tp RegAccess;
RegAccess_q2 <=#Tp RegAccess_q;
RISCAccess_q <=#Tp RISCAccess;
RISCAccess_q2 <=#Tp RISCAccess_q;
end
end
 
// Chip select and read/write signals for accessing RISC
assign RiscStall_write_access = RISCAccess & ~RISCAccess_q & RW;
assign RiscStall_read_access = RISCAccess & ~RISCAccess_q2 & ~RW;
assign RiscStall_access = RiscStall_write_access | RiscStall_read_access;
 
 
reg wb_Access_wbClk_q;
// Delayed signals used for accessing WISHBONE
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
wb_Access_wbClk_q <=#Tp 1'b0;
else
wb_Access_wbClk_q <=#Tp wb_Access_wbClk;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
wb_cyc_o <=#Tp 1'b0;
else
if(wb_Access_wbClk & ~wb_Access_wbClk_q & ~(wb_ack_i | wb_err_i))
wb_cyc_o <=#Tp 1'b1;
else
if(wb_ack_i | wb_err_i)
wb_cyc_o <=#Tp 1'b0;
end
 
assign wb_stb_o = wb_cyc_o;
 
 
// Latching data read from registers
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WBReadLatch[31:0]<=#Tp 32'h0;
else
if(wb_ack_i)
WBReadLatch[31:0]<=#Tp wb_dat_i[31:0];
end
 
// Latching WISHBONE error cycle
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WBErrorLatch<=#Tp 1'b0;
else
if(wb_err_i)
WBErrorLatch<=#Tp 1'b1; // Latching wb_err_i while performing WISHBONE access
else
if(wb_ack_i)
WBErrorLatch<=#Tp 1'b0; // Clearing status
end
 
 
// Whan enabled, TRACE stalls RISC while saving data to the trace buffer.
`ifdef TRACE_ENABLED
assign risc_stall_o = RiscStall_access | RiscStall_reg | RiscStall_trace ;
`else
assign risc_stall_o = RiscStall_access | RiscStall_reg;
`endif
 
assign reset_o = RiscReset_reg;
 
 
`ifdef TRACE_ENABLED
always @ (RiscStall_write_access or RiscStall_read_access or opselect_trace)
`else
always @ (RiscStall_write_access or RiscStall_read_access)
`endif
begin
if(RiscStall_write_access)
opselect_o = `DEBUG_WRITE_SPR; // Write spr
else
if(RiscStall_read_access)
opselect_o = `DEBUG_READ_SPR; // Read spr
else
`ifdef TRACE_ENABLED
opselect_o = opselect_trace;
`else
opselect_o = 3'h0;
`endif
end
 
 
// Latching data read from RISC or registers
always @ (posedge risc_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
DataReadLatch[31:0]<=#Tp 0;
else
if(RISCAccess_q & ~RISCAccess_q2)
DataReadLatch[31:0]<=#Tp risc_data_i[31:0];
else
if(RegAccess_q & ~RegAccess_q2)
DataReadLatch[31:0]<=#Tp RegDataIn[31:0];
end
 
assign risc_addr_o = ADDR;
assign risc_data_o = DataOut;
 
 
 
/**********************************************************************************
* *
* Read Trace buffer logic *
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
 
// Synchronizing the trace read buffer signal to risc_clk_i clock
dbg_sync_clk1_clk2 syn4 (.clk1(risc_clk_i), .clk2(tck), .reset1(wb_rst_i), .reset2(trst),
.set2(ReadBuffer_Tck), .sync_out(ReadTraceBuffer)
);
 
 
 
always @(posedge risc_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
ReadTraceBuffer_q <=#Tp 0;
else
ReadTraceBuffer_q <=#Tp ReadTraceBuffer;
end
 
assign ReadTraceBufferPulse = ReadTraceBuffer & ~ReadTraceBuffer_q;
 
`endif
 
/**********************************************************************************
* *
* End: Read Trace buffer logic *
* *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
* *
* Bit counter *
* *
**********************************************************************************/
 
 
always @ (posedge tck or posedge trst)
begin
if(trst)
BitCounter[7:0]<=#Tp 0;
else
if(ShiftDR)
BitCounter[7:0]<=#Tp BitCounter[7:0]+1;
else
if(UpdateDR)
BitCounter[7:0]<=#Tp 0;
end
 
 
 
/**********************************************************************************
* *
* End: Bit counter *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* Connecting Registers *
* *
**********************************************************************************/
dbg_registers dbgregs(.data_in(DataOut[31:0]), .data_out(RegDataIn[31:0]),
.address(ADDR[4:0]), .rw(RW), .access(RegAccess & ~RegAccess_q), .clk(risc_clk_i),
.bp(bp_i), .reset(wb_rst_i),
`ifdef TRACE_ENABLED
.ContinMode(ContinMode), .TraceEnable(TraceEnable),
.WpTrigger(WpTrigger), .BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger),
.ITrigger(ITrigger), .TriggerOper(TriggerOper), .WpQualif(WpQualif),
.BpQualif(BpQualif), .LSSQualif(LSSQualif), .IQualif(IQualif),
.QualifOper(QualifOper), .RecordPC(RecordPC),
.RecordLSEA(RecordLSEA), .RecordLDATA(RecordLDATA),
.RecordSDATA(RecordSDATA), .RecordReadSPR(RecordReadSPR),
.RecordWriteSPR(RecordWriteSPR), .RecordINSTR(RecordINSTR),
.WpTriggerValid(WpTriggerValid),
.BpTriggerValid(BpTriggerValid), .LSSTriggerValid(LSSTriggerValid),
.ITriggerValid(ITriggerValid), .WpQualifValid(WpQualifValid),
.BpQualifValid(BpQualifValid), .LSSQualifValid(LSSQualifValid),
.IQualifValid(IQualifValid),
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid),
`endif
.risc_stall(RiscStall_reg), .risc_reset(RiscReset_reg), .mon_cntl_o(mon_cntl_o)
 
);
 
/**********************************************************************************
* *
* End: Connecting Registers *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* Connecting CRC module *
* *
**********************************************************************************/
wire AsyncResetCrc = trst;
wire SyncResetCrc = UpdateDR_q;
wire [7:0] CalculatedCrcIn; // crc calculated from the input data (shifted in)
 
assign BitCounter_Lt4 = BitCounter<4;
assign BitCounter_Eq5 = BitCounter==5;
assign BitCounter_Eq32 = BitCounter==32;
assign BitCounter_Lt38 = BitCounter<38;
assign BitCounter_Lt65 = BitCounter<65;
 
`ifdef TRACE_ENABLED
assign BitCounter_Lt40 = BitCounter<40;
`endif
 
 
wire EnableCrcIn = ShiftDR &
( (CHAIN_SELECTSelected & BitCounter_Lt4) |
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
);
 
wire EnableCrcOut= ShiftDR &
(
((DEBUGSelected & RegisterScanChain) & BitCounter_Lt38)|
((DEBUGSelected & RiscDebugScanChain) & BitCounter_Lt65)|
((DEBUGSelected & WishboneScanChain) & BitCounter_Lt65)
`ifdef TRACE_ENABLED
|
((DEBUGSelected & TraceTestScanChain) & BitCounter_Lt40)
`endif
);
 
// Calculating crc for input data
dbg_crc8_d1 crc1 (.data(tdi), .enable_crc(EnableCrcIn), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
.crc_out(CalculatedCrcIn), .clk(tck));
 
// Calculating crc for output data
dbg_crc8_d1 crc2 (.data(TDOData), .enable_crc(EnableCrcOut), .reset(AsyncResetCrc), .sync_rst_crc(SyncResetCrc),
.crc_out(CalculatedCrcOut), .clk(tck));
 
 
// Generating CrcMatch signal
always @ (posedge tck or posedge trst)
begin
if(trst)
CrcMatch <=#Tp 1'b0;
else
if(Exit1DR)
begin
if(CHAIN_SELECTSelected)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[11:4];
else
begin
if(RegisterScanChain)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[45:38];
else
if(RiscDebugScanChain)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
else
if(WishboneScanChain)
CrcMatch <=#Tp CalculatedCrcIn == JTAG_DR_IN[72:65];
end
end
end
 
 
// Active chain
assign RegisterScanChain = Chain == `REGISTER_SCAN_CHAIN;
assign RiscDebugScanChain = Chain == `RISC_DEBUG_CHAIN;
assign WishboneScanChain = Chain == `WISHBONE_SCAN_CHAIN;
 
`ifdef TRACE_ENABLED
assign TraceTestScanChain = Chain == `TRACE_TEST_CHAIN;
`endif
 
/**********************************************************************************
* *
* End: Connecting CRC module *
* *
**********************************************************************************/
 
/**********************************************************************************
* *
* Connecting trace module *
* *
**********************************************************************************/
`ifdef TRACE_ENABLED
dbg_trace dbgTrace1(.Wp(wp_i), .Bp(bp_i), .DataIn(risc_data_i), .OpSelect(opselect_trace),
.LsStatus(lsstatus_i), .IStatus(istatus_i), .RiscStall_O(RiscStall_trace),
.Mclk(risc_clk_i), .Reset(wb_rst_i), .TraceChain(TraceChain),
.ContinMode(ContinMode), .TraceEnable_reg(TraceEnable),
.WpTrigger(WpTrigger),
.BpTrigger(BpTrigger), .LSSTrigger(LSSTrigger), .ITrigger(ITrigger),
.TriggerOper(TriggerOper), .WpQualif(WpQualif), .BpQualif(BpQualif),
.LSSQualif(LSSQualif), .IQualif(IQualif), .QualifOper(QualifOper),
.RecordPC(RecordPC), .RecordLSEA(RecordLSEA),
.RecordLDATA(RecordLDATA), .RecordSDATA(RecordSDATA),
.RecordReadSPR(RecordReadSPR), .RecordWriteSPR(RecordWriteSPR),
.RecordINSTR(RecordINSTR),
.WpTriggerValid(WpTriggerValid), .BpTriggerValid(BpTriggerValid),
.LSSTriggerValid(LSSTriggerValid), .ITriggerValid(ITriggerValid),
.WpQualifValid(WpQualifValid), .BpQualifValid(BpQualifValid),
.LSSQualifValid(LSSQualifValid), .IQualifValid(IQualifValid),
.ReadBuffer(ReadTraceBufferPulse),
.WpStop(WpStop), .BpStop(BpStop), .LSSStop(LSSStop), .IStop(IStop),
.StopOper(StopOper), .WpStopValid(WpStopValid), .BpStopValid(BpStopValid),
.LSSStopValid(LSSStopValid), .IStopValid(IStopValid)
);
`endif
/**********************************************************************************
* *
* End: Connecting trace module *
* *
**********************************************************************************/
 
 
 
endmodule
/verilog/dbg_registers.v
0,0 → 1,312
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_registers.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/04/22 12:54:11 mohor
// Signal names changed to lower case.
//
// Revision 1.5 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.4 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.3 2001/10/15 09:55:47 mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:10 mohor
// Initial release
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
module dbg_registers(data_in, data_out, address, rw, access, clk, bp, reset,
`ifdef TRACE_ENABLED
ContinMode,
TraceEnable, WpTrigger, BpTrigger, LSSTrigger,
ITrigger, TriggerOper, WpQualif, BpQualif, LSSQualif, IQualif,
QualifOper, RecordPC, RecordLSEA, RecordLDATA,
RecordSDATA, RecordReadSPR, RecordWriteSPR, RecordINSTR,
WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid,
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid,
`endif
risc_stall, risc_reset, mon_cntl_o
);
 
parameter Tp = 1;
 
input [31:0] data_in;
input [4:0] address;
 
input rw;
input access;
input clk;
input bp;
input reset;
 
output [31:0] data_out;
reg [31:0] data_out;
 
`ifdef TRACE_ENABLED
output ContinMode;
output TraceEnable;
output [10:0] WpTrigger;
output BpTrigger;
output [3:0] LSSTrigger;
output [1:0] ITrigger;
output [1:0] TriggerOper;
output WpTriggerValid;
output BpTriggerValid;
output LSSTriggerValid;
output ITriggerValid;
output [10:0] WpQualif;
output BpQualif;
output [3:0] LSSQualif;
output [1:0] IQualif;
output [1:0] QualifOper;
output WpQualifValid;
output BpQualifValid;
output LSSQualifValid;
output IQualifValid;
output [10:0] WpStop;
output BpStop;
output [3:0] LSSStop;
output [1:0] IStop;
output [1:0] StopOper;
output WpStopValid;
output BpStopValid;
output LSSStopValid;
output IStopValid;
output RecordPC;
output RecordLSEA;
output RecordLDATA;
output RecordSDATA;
output RecordReadSPR;
output RecordWriteSPR;
output RecordINSTR;
`endif
 
output risc_stall;
output risc_reset;
output [3:0] mon_cntl_o;
 
wire MODER_Acc = (address == `MODER_ADR) & access;
wire RISCOP_Acc = (address == `RISCOP_ADR) & access;
wire MON_CNTL_Acc = (address == `MON_CNTL_ADR) & access;
`ifdef TRACE_ENABLED
wire TSEL_Acc = (address == `TSEL_ADR) & access;
wire QSEL_Acc = (address == `QSEL_ADR) & access;
wire SSEL_Acc = (address == `SSEL_ADR) & access;
wire RECSEL_Acc = (address == `RECSEL_ADR) & access;
`endif
 
wire MODER_Wr = MODER_Acc & rw;
wire RISCOP_Wr = RISCOP_Acc & rw;
wire MON_CNTL_Wr = MON_CNTL_Acc & rw;
`ifdef TRACE_ENABLED
wire TSEL_Wr = TSEL_Acc & rw;
wire QSEL_Wr = QSEL_Acc & rw;
wire SSEL_Wr = SSEL_Acc & rw;
wire RECSEL_Wr = RECSEL_Acc & rw;
`endif
 
 
wire MODER_Rd = MODER_Acc & ~rw;
wire RISCOP_Rd = RISCOP_Acc & ~rw;
wire MON_CNTL_Rd = MON_CNTL_Acc & ~rw;
`ifdef TRACE_ENABLED
wire TSEL_Rd = TSEL_Acc & ~rw;
wire QSEL_Rd = QSEL_Acc & ~rw;
wire SSEL_Rd = SSEL_Acc & ~rw;
wire RECSEL_Rd = RECSEL_Acc & ~rw;
`endif
 
 
wire [31:0] MODEROut;
wire [1:1] RISCOPOut;
wire [3:0] MONCNTLOut;
 
`ifdef TRACE_ENABLED
wire [31:0] TSELOut;
wire [31:0] QSELOut;
wire [31:0] SSELOut;
wire [6:0] RECSELOut;
`endif
 
 
`ifdef TRACE_ENABLED
assign MODEROut[15:0] = 16'h0001;
assign MODEROut[31:18] = 14'h0;
`else
assign MODEROut[31:0] = 32'h0000;
`endif
 
 
reg RiscStallBp;
always @(posedge clk or posedge reset)
begin
if(reset)
RiscStallBp <= 1'b0;
else
if(bp) // Breakpoint sets bit
RiscStallBp <= 1'b1;
else
if(RISCOP_Wr) // Register access can set or clear bit
RiscStallBp <= data_in[0];
end
 
dbg_register #(1) RISCOP (.data_in(data_in[1]), .data_out(RISCOPOut[1]), .write(RISCOP_Wr), .clk(clk), .reset(reset), .defaulty(1'b0));
dbg_register #(4) MONCNTL (.data_in(data_in[3:0]), .data_out(MONCNTLOut[3:0]), .write(MON_CNTL_Wr), .clk(clk), .reset(reset), .defaulty(`MON_CNTL_DEF));
 
 
`ifdef TRACE_ENABLED
dbg_register #(2) MODER (.data_in(data_in[17:16]), .data_out(MODEROut[17:16]), .write(MODER_Wr), .clk(clk), .reset(reset), .defaulty(`MODER_DEF));
dbg_register #(32) TSEL (.data_in(data_in), .data_out(TSELOut), .write(TSEL_Wr), .clk(clk), .reset(reset), .defaulty(`TSEL_DEF));
dbg_register #(32) QSEL (.data_in(data_in), .data_out(QSELOut), .write(QSEL_Wr), .clk(clk), .reset(reset), .defaulty(`QSEL_DEF));
dbg_register #(32) SSEL (.data_in(data_in), .data_out(SSELOut), .write(SSEL_Wr), .clk(clk), .reset(reset), .defaulty(`SSEL_DEF));
dbg_register #(7) RECSEL (.data_in(data_in[6:0]), .data_out(RECSELOut), .write(RECSEL_Wr), .clk(clk), .reset(reset), .defaulty(`RECSEL_DEF));
`endif
 
 
 
always @ (posedge clk)
begin
if(MODER_Rd) data_out<= #Tp MODEROut;
else
if(RISCOP_Rd) data_out<= #Tp {30'h0, RISCOPOut[1], risc_stall};
else
if(MON_CNTL_Rd) data_out<= #Tp {28'h0, MONCNTLOut};
`ifdef TRACE_ENABLED
else
if(TSEL_Rd) data_out<= #Tp TSELOut;
else
if(QSEL_Rd) data_out<= #Tp QSELOut;
else
if(SSEL_Rd) data_out<= #Tp SSELOut;
else
if(RECSEL_Rd) data_out<= #Tp {25'h0, RECSELOut};
`endif
else data_out<= #Tp 'h0;
end
 
`ifdef TRACE_ENABLED
assign TraceEnable = MODEROut[16];
assign ContinMode = MODEROut[17];
assign WpTrigger[10:0] = TSELOut[10:0];
assign WpTriggerValid = TSELOut[11];
assign BpTrigger = TSELOut[12];
assign BpTriggerValid = TSELOut[13];
assign LSSTrigger[3:0] = TSELOut[19:16];
assign LSSTriggerValid = TSELOut[20];
assign ITrigger[1:0] = TSELOut[22:21];
assign ITriggerValid = TSELOut[23];
assign TriggerOper[1:0] = TSELOut[31:30];
assign WpQualif[10:0] = QSELOut[10:0];
assign WpQualifValid = QSELOut[11];
assign BpQualif = QSELOut[12];
assign BpQualifValid = QSELOut[13];
assign LSSQualif[3:0] = QSELOut[19:16];
assign LSSQualifValid = QSELOut[20];
assign IQualif[1:0] = QSELOut[22:21];
assign IQualifValid = QSELOut[23];
assign QualifOper[1:0] = QSELOut[31:30];
assign WpStop[10:0] = SSELOut[10:0];
assign WpStopValid = SSELOut[11];
assign BpStop = SSELOut[12];
assign BpStopValid = SSELOut[13];
assign LSSStop[3:0] = SSELOut[19:16];
assign LSSStopValid = SSELOut[20];
assign IStop[1:0] = SSELOut[22:21];
assign IStopValid = SSELOut[23];
assign StopOper[1:0] = SSELOut[31:30];
assign RecordPC = RECSELOut[0];
assign RecordLSEA = RECSELOut[1];
assign RecordLDATA = RECSELOut[2];
assign RecordSDATA = RECSELOut[3];
assign RecordReadSPR = RECSELOut[4];
assign RecordWriteSPR = RECSELOut[5];
assign RecordINSTR = RECSELOut[6];
`endif
 
assign risc_stall = bp | RiscStallBp; // bp asynchronously sets the risc_stall, then RiscStallBp (from register) holds it active
assign risc_reset = RISCOPOut[1];
assign mon_cntl_o = MONCNTLOut;
 
endmodule
/verilog/dbg_defines.v
0,0 → 1,167
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_defines.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2002/01/25 07:58:34 mohor
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
// not filled-in. Tested in hw.
//
// Revision 1.7 2001/12/06 10:08:06 mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.6 2001/11/28 09:38:30 mohor
// Trace disabled by default.
//
// Revision 1.5 2001/10/15 09:55:47 mohor
// Wishbone interface added, few fixes for better performance,
// hooks for boundary scan testing added.
//
// Revision 1.4 2001/09/24 14:06:42 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.3 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:08 mohor
// Initial release
//
//
 
 
 
// Enable TRACE
//`define TRACE_ENABLED // Uncomment this define to activate the trace
 
 
// Define IDCODE Value
`define IDCODE_VALUE 32'hdeadbeef
 
// Define master clock (RISC clock)
//`define RISC_CLOCK 50 // Half period = 50 ns => MCLK = 10 Mhz
`define RISC_CLOCK 2.5 // Half period = 5 ns => MCLK = 200 Mhz
 
// Length of the Instruction register
`define IR_LENGTH 4
 
// Length of the Data register (must be equal to the longest scan chain for shifting the data in)
`define DR_LENGTH 74
 
// Length of the CHAIN ID register
`define CHAIN_ID_LENGTH 4
 
// Length of the CRC
`define CRC_LENGTH 8
 
// Trace buffer size and counter and write/read pointer width. This can be expanded when more RAM is avaliable
`define TRACECOUNTERWIDTH 5
`define TRACEBUFFERLENGTH 32 // 2^5
 
`define TRACESAMPLEWIDTH 36
 
// OpSelect width
`define OPSELECTWIDTH 3
`define OPSELECTIONCOUNTER 8 //2^3
 
// OpSelect (dbg_op_i) signal meaning
`define DEBUG_READ_PC 0
`define DEBUG_READ_LSEA 1
`define DEBUG_READ_LDATA 2
`define DEBUG_READ_SDATA 3
`define DEBUG_READ_SPR 4
`define DEBUG_WRITE_SPR 5
`define DEBUG_READ_INSTR 6
//`define Reserved 7
 
// Supported Instructions
`define EXTEST 4'b0000
`define SAMPLE_PRELOAD 4'b0001
`define IDCODE 4'b0010
`define CHAIN_SELECT 4'b0011
`define INTEST 4'b0100
`define CLAMP 4'b0101
`define CLAMPZ 4'b0110
`define HIGHZ 4'b0111
`define DEBUG 4'b1000
`define BYPASS 4'b1111
 
// Chains
`define GLOBAL_BS_CHAIN 4'b0000
`define RISC_DEBUG_CHAIN 4'b0001
`define RISC_TEST_CHAIN 4'b0010
`define TRACE_TEST_CHAIN 4'b0011
`define REGISTER_SCAN_CHAIN 4'b0100
`define WISHBONE_SCAN_CHAIN 4'b0101
 
// Registers addresses
`define MODER_ADR 5'h00
`define TSEL_ADR 5'h01
`define QSEL_ADR 5'h02
`define SSEL_ADR 5'h03
`define RISCOP_ADR 5'h04
`define RECSEL_ADR 5'h10
`define MON_CNTL_ADR 5'h11
 
 
// Registers default values (after reset)
`define MODER_DEF 2'h0
`define TSEL_DEF 32'h00000000
`define QSEL_DEF 32'h00000000
`define SSEL_DEF 32'h00000000
`define RISCOP_DEF 2'h0
`define RECSEL_DEF 7'h0
`define MON_CNTL_DEF 4'h0
/verilog/dbg_register.v
0,0 → 1,98
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_register.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/04/22 12:54:11 mohor
// Signal names changed to lower case.
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module dbg_register(data_in, data_out, write, clk, reset, defaulty);
 
parameter WIDTH = 8; // default parameter of the register width
 
input [WIDTH-1:0] data_in;
 
input write;
input clk;
input reset;
input [WIDTH-1:0] defaulty;
 
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
 
always @ (posedge clk or posedge reset)
//always @ (posedge clk)
begin
if(reset)
data_out[WIDTH-1:0]<=#1 defaulty;
else
begin
if(write) // write
data_out[WIDTH-1:0]<=#1 data_in[WIDTH-1:0];
end
end
 
 
endmodule // Register
 
/verilog/tap_top.v
0,0 → 1,593
//////////////////////////////////////////////////////////////////////
//// ////
//// tap_top.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/03/26 14:23:38 mohor
// Signal tdo_padoe_o changed back to tdo_padoen_o.
//
// Revision 1.4 2002/03/25 13:16:15 mohor
// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
// not named correctly.
//
// Revision 1.3 2002/03/12 14:30:05 mohor
// Few outputs for boundary scan chain added.
//
// Revision 1.2 2002/03/12 10:31:53 mohor
// tap_top and dbg_top modules are put into two separate modules. tap_top
// contains only tap state machine and related logic. dbg_top contains all
// logic necessery for debugging.
//
// Revision 1.1 2002/03/08 15:28:16 mohor
// Structure changed. Hooks for jtag chain added.
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module tap_top(
// JTAG pins
tms_pad_i, tck_pad_i, trst_pad_i, tdi_pad_i, tdo_pad_o, tdo_padoe_o,
 
// TAP states
ShiftDR, Exit1DR, UpdateDR, UpdateDR_q, CaptureDR,
// Instructions
IDCODESelected, CHAIN_SELECTSelected, DEBUGSelected, EXTESTSelected,
// TDO from dbg module
TDOData_dbg, BypassRegister,
// From Boundary Scan Chain
bs_chain_i
);
 
parameter Tp = 1;
 
// JTAG pins
input tms_pad_i; // JTAG test mode select pad
input tck_pad_i; // JTAG test clock pad
input trst_pad_i; // JTAG test reset pad
input tdi_pad_i; // JTAG test data input pad
output tdo_pad_o; // JTAG test data output pad
output tdo_padoe_o; // Output enable for JTAG test data output pad
 
// TAP states
output ShiftDR;
output Exit1DR;
output UpdateDR;
output UpdateDR_q;
output CaptureDR;
 
// Instructions
output IDCODESelected;
output CHAIN_SELECTSelected;
output DEBUGSelected;
output EXTESTSelected;
 
input TDOData_dbg;
output BypassRegister;
 
// From Boundary Scan Chain
input bs_chain_i;
 
 
reg tdo_pad_o;
 
// TAP states
reg TestLogicReset;
reg RunTestIdle;
reg SelectDRScan;
reg CaptureDR;
reg ShiftDR;
reg Exit1DR;
reg PauseDR;
reg Exit2DR;
reg UpdateDR;
 
reg SelectIRScan;
reg CaptureIR;
reg ShiftIR;
reg Exit1IR;
reg PauseIR;
reg Exit2IR;
reg UpdateIR;
 
 
// Defining which instruction is selected
reg EXTESTSelected;
reg SAMPLE_PRELOADSelected;
reg IDCODESelected;
reg CHAIN_SELECTSelected;
reg INTESTSelected;
reg CLAMPSelected;
reg CLAMPZSelected;
reg HIGHZSelected;
reg DEBUGSelected;
reg BYPASSSelected;
 
reg BypassRegister; // Bypass register
 
wire trst; // trst is active high while trst_pad_i is active low
wire tck;
wire TMS;
wire tdi;
 
wire RiscDebugScanChain;
wire WishboneScanChain;
wire RegisterScanChain;
 
 
assign trst = ~trst_pad_i; // trst_pad_i is active low
assign tck = tck_pad_i;
assign TMS = tms_pad_i;
assign tdi = tdi_pad_i;
 
 
/**********************************************************************************
* *
* TAP State Machine: Fully JTAG compliant *
* *
**********************************************************************************/
 
// TestLogicReset state
always @ (posedge tck or posedge trst)
begin
if(trst)
TestLogicReset<=#Tp 1;
else
begin
if(TMS & (TestLogicReset | SelectIRScan))
TestLogicReset<=#Tp 1;
else
TestLogicReset<=#Tp 0;
end
end
 
// RunTestIdle state
always @ (posedge tck or posedge trst)
begin
if(trst)
RunTestIdle<=#Tp 0;
else
if(~TMS & (TestLogicReset | RunTestIdle | UpdateDR | UpdateIR))
RunTestIdle<=#Tp 1;
else
RunTestIdle<=#Tp 0;
end
 
// SelectDRScan state
always @ (posedge tck or posedge trst)
begin
if(trst)
SelectDRScan<=#Tp 0;
else
if(TMS & (RunTestIdle | UpdateDR | UpdateIR))
SelectDRScan<=#Tp 1;
else
SelectDRScan<=#Tp 0;
end
 
// CaptureDR state
always @ (posedge tck or posedge trst)
begin
if(trst)
CaptureDR<=#Tp 0;
else
if(~TMS & SelectDRScan)
CaptureDR<=#Tp 1;
else
CaptureDR<=#Tp 0;
end
 
// ShiftDR state
always @ (posedge tck or posedge trst)
begin
if(trst)
ShiftDR<=#Tp 0;
else
if(~TMS & (CaptureDR | ShiftDR | Exit2DR))
ShiftDR<=#Tp 1;
else
ShiftDR<=#Tp 0;
end
 
// Exit1DR state
always @ (posedge tck or posedge trst)
begin
if(trst)
Exit1DR<=#Tp 0;
else
if(TMS & (CaptureDR | ShiftDR))
Exit1DR<=#Tp 1;
else
Exit1DR<=#Tp 0;
end
 
// PauseDR state
always @ (posedge tck or posedge trst)
begin
if(trst)
PauseDR<=#Tp 0;
else
if(~TMS & (Exit1DR | PauseDR))
PauseDR<=#Tp 1;
else
PauseDR<=#Tp 0;
end
 
// Exit2DR state
always @ (posedge tck or posedge trst)
begin
if(trst)
Exit2DR<=#Tp 0;
else
if(TMS & PauseDR)
Exit2DR<=#Tp 1;
else
Exit2DR<=#Tp 0;
end
 
// UpdateDR state
always @ (posedge tck or posedge trst)
begin
if(trst)
UpdateDR<=#Tp 0;
else
if(TMS & (Exit1DR | Exit2DR))
UpdateDR<=#Tp 1;
else
UpdateDR<=#Tp 0;
end
 
// Delayed UpdateDR state
reg UpdateDR_q;
always @ (posedge tck)
begin
UpdateDR_q<=#Tp UpdateDR;
end
 
// SelectIRScan state
always @ (posedge tck or posedge trst)
begin
if(trst)
SelectIRScan<=#Tp 0;
else
if(TMS & SelectDRScan)
SelectIRScan<=#Tp 1;
else
SelectIRScan<=#Tp 0;
end
 
// CaptureIR state
always @ (posedge tck or posedge trst)
begin
if(trst)
CaptureIR<=#Tp 0;
else
if(~TMS & SelectIRScan)
CaptureIR<=#Tp 1;
else
CaptureIR<=#Tp 0;
end
 
// ShiftIR state
always @ (posedge tck or posedge trst)
begin
if(trst)
ShiftIR<=#Tp 0;
else
if(~TMS & (CaptureIR | ShiftIR | Exit2IR))
ShiftIR<=#Tp 1;
else
ShiftIR<=#Tp 0;
end
 
// Exit1IR state
always @ (posedge tck or posedge trst)
begin
if(trst)
Exit1IR<=#Tp 0;
else
if(TMS & (CaptureIR | ShiftIR))
Exit1IR<=#Tp 1;
else
Exit1IR<=#Tp 0;
end
 
// PauseIR state
always @ (posedge tck or posedge trst)
begin
if(trst)
PauseIR<=#Tp 0;
else
if(~TMS & (Exit1IR | PauseIR))
PauseIR<=#Tp 1;
else
PauseIR<=#Tp 0;
end
 
// Exit2IR state
always @ (posedge tck or posedge trst)
begin
if(trst)
Exit2IR<=#Tp 0;
else
if(TMS & PauseIR)
Exit2IR<=#Tp 1;
else
Exit2IR<=#Tp 0;
end
 
// UpdateIR state
always @ (posedge tck or posedge trst)
begin
if(trst)
UpdateIR<=#Tp 0;
else
if(TMS & (Exit1IR | Exit2IR))
UpdateIR<=#Tp 1;
else
UpdateIR<=#Tp 0;
end
 
/**********************************************************************************
* *
* End: TAP State Machine *
* *
**********************************************************************************/
 
 
 
/**********************************************************************************
* *
* JTAG_IR: JTAG Instruction Register *
* *
**********************************************************************************/
wire [1:0]Status = 2'b10; // Holds current chip status. Core should return this status. For now a constant is used.
 
reg [`IR_LENGTH-1:0]JTAG_IR; // Instruction register
reg [`IR_LENGTH-1:0]LatchedJTAG_IR;
 
reg TDOInstruction;
 
always @ (posedge tck or posedge trst)
begin
if(trst)
JTAG_IR[`IR_LENGTH-1:0] <= #Tp 0;
else
if(CaptureIR)
begin
JTAG_IR[1:0] <= #Tp 2'b01; // This value is fixed for easier fault detection
JTAG_IR[3:2] <= #Tp Status[1:0]; // Current status of chip
end
else
if(ShiftIR)
JTAG_IR[`IR_LENGTH-1:0] <= #Tp {tdi, JTAG_IR[`IR_LENGTH-1:1]};
end
 
 
//TDO is changing on the falling edge of tck
always @ (negedge tck)
begin
if(ShiftIR)
TDOInstruction <= #Tp JTAG_IR[0];
end
 
/**********************************************************************************
* *
* End: JTAG_IR *
* *
**********************************************************************************/
 
 
/**********************************************************************************
* *
* JTAG_DR: JTAG Data Register *
* *
**********************************************************************************/
reg [`DR_LENGTH-1:0]JTAG_DR_IN; // Data register
 
 
always @ (posedge tck or posedge trst)
begin
if(trst)
JTAG_DR_IN[`DR_LENGTH-1:0]<=#Tp 0;
else
if(IDCODESelected) // To save space JTAG_DR_IN is also used for shifting out IDCODE
begin
if(ShiftDR)
JTAG_DR_IN[31:0] <= #Tp {tdi, JTAG_DR_IN[31:1]};
else
JTAG_DR_IN[31:0] <= #Tp `IDCODE_VALUE;
end
else
if(CHAIN_SELECTSelected & ShiftDR)
JTAG_DR_IN[12:0] <= #Tp {tdi, JTAG_DR_IN[12:1]};
else
if(DEBUGSelected & ShiftDR)
begin
if(RiscDebugScanChain | WishboneScanChain)
JTAG_DR_IN[73:0] <= #Tp {tdi, JTAG_DR_IN[73:1]};
else
if(RegisterScanChain)
JTAG_DR_IN[46:0] <= #Tp {tdi, JTAG_DR_IN[46:1]};
end
end
 
 
/**********************************************************************************
* *
* End: JTAG_DR *
* *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
* *
* Bypass logic *
* *
**********************************************************************************/
reg TDOBypassed;
 
always @ (posedge tck)
begin
if(ShiftDR)
BypassRegister<=#Tp tdi;
end
 
always @ (negedge tck)
begin
TDOBypassed<=#Tp BypassRegister;
end
/**********************************************************************************
* *
* End: Bypass logic *
* *
**********************************************************************************/
 
 
 
 
 
/**********************************************************************************
* *
* Activating Instructions *
* *
**********************************************************************************/
 
// Updating JTAG_IR (Instruction Register)
always @ (posedge tck or posedge trst)
begin
if(trst)
LatchedJTAG_IR <=#Tp `IDCODE; // IDCODE selected after reset
else
if(UpdateIR)
LatchedJTAG_IR <=#Tp JTAG_IR;
end
 
/**********************************************************************************
* *
* End: Activating Instructions *
* *
**********************************************************************************/
 
 
// Updating JTAG_IR (Instruction Register)
always @ (LatchedJTAG_IR)
begin
EXTESTSelected = 0;
SAMPLE_PRELOADSelected = 0;
IDCODESelected = 0;
CHAIN_SELECTSelected = 0;
INTESTSelected = 0;
CLAMPSelected = 0;
CLAMPZSelected = 0;
HIGHZSelected = 0;
DEBUGSelected = 0;
BYPASSSelected = 0;
 
case(LatchedJTAG_IR)
`EXTEST: EXTESTSelected = 1; // External test
`SAMPLE_PRELOAD: SAMPLE_PRELOADSelected = 1; // Sample preload
`IDCODE: IDCODESelected = 1; // ID Code
`CHAIN_SELECT: CHAIN_SELECTSelected = 1; // Chain select
`INTEST: INTESTSelected = 1; // Internal test
`CLAMP: CLAMPSelected = 1; // Clamp
`CLAMPZ: CLAMPZSelected = 1; // ClampZ
`HIGHZ: HIGHZSelected = 1; // High Z
`DEBUG: DEBUGSelected = 1; // Debug
`BYPASS: BYPASSSelected = 1; // BYPASS
default: BYPASSSelected = 1; // BYPASS
endcase
end
 
 
 
/**********************************************************************************
* *
* Multiplexing TDO data *
* *
**********************************************************************************/
 
// This multiplexer can be expanded with number of user registers
always @ (LatchedJTAG_IR or TDOInstruction or TDOData_dbg or TDOBypassed or bs_chain_i or ShiftIR or Exit1IR)
begin
if(ShiftIR | Exit1IR)
tdo_pad_o <=#Tp TDOInstruction;
else
begin
case(LatchedJTAG_IR)
`IDCODE: tdo_pad_o <=#Tp TDOData_dbg; // Reading ID code
`CHAIN_SELECT: tdo_pad_o <=#Tp TDOData_dbg; // Selecting the chain
`DEBUG: tdo_pad_o <=#Tp TDOData_dbg; // Debug
`SAMPLE_PRELOAD: tdo_pad_o <=#Tp bs_chain_i; // Sampling/Preloading
`EXTEST: tdo_pad_o <=#Tp bs_chain_i; // External test
default: tdo_pad_o <=#Tp TDOBypassed; // BYPASS instruction
endcase
end
end
 
// Tristate control for tdo_pad_o pin
assign tdo_padoe_o = ShiftIR | ShiftDR | Exit1IR | Exit1DR | UpdateDR;
 
/**********************************************************************************
* *
* End: Multiplexing TDO data *
* *
**********************************************************************************/
 
endmodule
/verilog/dbg_crc8_d1.v
0,0 → 1,147
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_crc8_d1 crc1.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2002/04/09 14:19:22 mohor
// Function changed to logic because of some synthesis warnings.
//
// Revision 1.5 2001/12/06 10:01:57 mohor
// Warnings from synthesys tools fixed.
//
// Revision 1.4 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.3 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.2 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:36 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:03 mohor
// Initial release
//
//
///////////////////////////////////////////////////////////////////////
// File: CRC8_D1.v
// Date: Fri Apr 27 20:56:55 2001
//
// Copyright (C) 1999 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 8)
// * data width: 1
//
// Info: jand@easics.be (Jan Decaluwe)
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
 
module dbg_crc8_d1 (data, enable_crc, reset, sync_rst_crc, crc_out, clk);
 
parameter Tp = 1;
 
 
input data;
input enable_crc;
input reset;
input sync_rst_crc;
input clk;
 
 
output [7:0] crc_out;
reg [7:0] crc_out;
 
wire [7:0] NewCRC;
 
assign NewCRC[0] = data ^ crc_out[7];
assign NewCRC[1] = data ^ crc_out[0] ^ crc_out[7];
assign NewCRC[2] = data ^ crc_out[1] ^ crc_out[7];
assign NewCRC[3] = crc_out[2];
assign NewCRC[4] = crc_out[3];
assign NewCRC[5] = crc_out[4];
assign NewCRC[6] = crc_out[5];
assign NewCRC[7] = crc_out[6];
 
 
always @ (posedge clk or posedge reset)
begin
if(reset)
crc_out[7:0] <= #Tp 0;
else
if(sync_rst_crc)
crc_out[7:0] <= #Tp 0;
else
if(enable_crc)
crc_out[7:0] <= #Tp NewCRC;
end
 
 
 
endmodule
/verilog/jtag_chain.v
0,0 → 1,75
//////////////////////////////////////////////////////////////////////
//// ////
//// jtag_chain.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// Top module
module jtag_chain ( capture_dr_i, shift_dr_i, update_dr_i, extest_selected_i,
bs_chain_i, bs_chain_o
);
 
parameter Tp = 1;
 
 
input capture_dr_i;
input shift_dr_i;
input update_dr_i;
input extest_selected_i;
input bs_chain_i;
 
output bs_chain_o;
 
assign bs_chain_o = 0;
 
endmodule
/verilog/dbg_sync_clk1_clk2.v
0,0 → 1,151
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_sync_clk1_clk2.v ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
 
parameter Tp = 1;
 
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
 
output sync_out;
 
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
 
wire z;
 
assign z = set2 | set2_q & ~clear2_q2;
 
 
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q <=#Tp 1'b0;
else
set2_q <=#Tp z;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q2 <=#Tp 1'b0;
else
set2_q2 <=#Tp set2_q;
end
 
 
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q <=#Tp 1'b0;
else
set1_q <=#Tp set2_q2;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q2 <=#Tp 1'b0;
else
set1_q2 <=#Tp set1_q;
end
 
 
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q <=#Tp 1'b0;
else
clear2_q <=#Tp set1_q2;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q2 <=#Tp 1'b0;
else
clear2_q2 <=#Tp clear2_q;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
sync_out <=#Tp 1'b0;
else
sync_out <=#Tp set1_q2;
end
 
endmodule
/verilog/dbg_trace.v
0,0 → 1,470
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_trace.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.4 2001/09/20 10:11:25 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.3 2001/09/19 11:55:13 mohor
// Asynchronous set/reset not used in trace any more.
//
// Revision 1.2 2001/09/18 14:13:47 mohor
// Trace fixed. Some registers changed, trace simplified.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.3 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.2 2001/05/18 13:10:00 mohor
// Headers changed. All additional information is now avaliable in the README.txt file.
//
// Revision 1.1.1.1 2001/05/18 06:35:06 mohor
// Initial release
//
//
 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_defines.v"
 
// module Trace
module dbg_trace (Wp, Bp, DataIn, OpSelect, LsStatus, IStatus, RiscStall_O,
Mclk, Reset, TraceChain, ContinMode, TraceEnable_reg,
WpTrigger, BpTrigger, LSSTrigger, ITrigger, TriggerOper, WpQualif,
BpQualif, LSSQualif, IQualif, QualifOper, RecordPC, RecordLSEA,
RecordLDATA, RecordSDATA, RecordReadSPR, RecordWriteSPR,
RecordINSTR,
WpTriggerValid, BpTriggerValid, LSSTriggerValid, ITriggerValid,
WpQualifValid, BpQualifValid, LSSQualifValid, IQualifValid, ReadBuffer,
WpStop, BpStop, LSSStop, IStop, StopOper, WpStopValid, BpStopValid,
LSSStopValid, IStopValid
);
 
parameter Tp = 1;
 
 
input [10:0] Wp; // Watchpoints
input Bp; // Breakpoint
input [31:0] DataIn; // Data from the RISC
input [3:0] LsStatus; // Load/Store status
input [1:0] IStatus; // Instruction status
 
input Mclk; // Master clock (RISC clock)
input Reset; // Reset
input ReadBuffer; // Instruction for reading a sample from the Buffer
 
// from registers
input ContinMode; // Continous mode of the trace
input TraceEnable_reg; // Trace is enabled (enabled by writing a bit in the register)
 
input [10:0] WpTrigger; // Signals that come from registers to set the trigger
input BpTrigger; // Signals that come from registers to set the trigger
input [3:0] LSSTrigger; // Signals that come from registers to set the trigger
input [1:0] ITrigger; // Signals that come from registers to set the trigger
input [1:0] TriggerOper; // Signals that come from registers to set the trigger
 
input [10:0] WpQualif; // Signals that come from registers to set the qualifier
input BpQualif; // Signals that come from registers to set the qualifier
input [3:0] LSSQualif; // Signals that come from registers to set the qualifier
input [1:0] IQualif; // Signals that come from registers to set the qualifier
input [1:0] QualifOper; // Signals that come from registers to set the qualifier
 
input [10:0] WpStop; // Signals that come from registers to set the stop condition
input BpStop; // Signals that come from registers to set the stop condition
input [3:0] LSSStop; // Signals that come from registers to set the stop condition
input [1:0] IStop; // Signals that come from registers to set the stop condition
input [1:0] StopOper; // Signals that come from registers to set the stop condition
 
input RecordPC; // Signals that come from registers for defining the sample for recording
input RecordLSEA; // Signals that come from registers for defining the sample for recording
input RecordLDATA; // Signals that come from registers for defining the sample for recording
input RecordSDATA; // Signals that come from registers for defining the sample for recording
input RecordReadSPR; // Signals that come from registers for defining the sample for recording
input RecordWriteSPR; // Signals that come from registers for defining the sample for recording
input RecordINSTR; // Signals that come from registers for defining the sample for recording
 
input WpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
input BpTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
input LSSTriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
input ITriggerValid; // Signals that come from registers and indicate which trigger conditions are valid
 
input WpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
input BpQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
input LSSQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
input IQualifValid; // Signals that come from registers and indicate which qualifier conditions are valid
 
input WpStopValid; // Signals that come from registers and indicate which stop conditions are valid
input BpStopValid; // Signals that come from registers and indicate which stop conditions are valid
input LSSStopValid; // Signals that come from registers and indicate which stop conditions are valid
input IStopValid; // Signals that come from registers and indicate which stop conditions are valid
// end: from registers
 
 
output [`OPSELECTWIDTH-1:0] OpSelect; // Operation select (what kind of information is avaliable on the DataIn)
output RiscStall_O; // CPU stall (stalls the RISC)
output [39:0] TraceChain; // Scan shain from the trace module
 
reg TraceEnable_d;
reg TraceEnable;
 
 
 
reg [`TRACECOUNTERWIDTH:0] Counter;
reg [`TRACECOUNTERWIDTH-1:0] WritePointer;
reg [`TRACECOUNTERWIDTH-1:0] ReadPointer;
reg RiscStall;
reg RiscStall_q;
reg [`OPSELECTWIDTH-1:0] StallCounter;
 
reg [`TRACESAMPLEWIDTH-1:0] Buffer[0:`TRACEBUFFERLENGTH-1];
 
reg TriggerLatch;
 
 
/**********************************************************************************
* *
* Generation of the trigger *
* *
**********************************************************************************/
wire TempWpTrigger = |(Wp[10:0] & WpTrigger[10:0]);
wire TempBpTrigger = Bp & BpTrigger;
wire TempLSSTrigger = LsStatus[3:0] == LSSTrigger[3:0];
wire TempITrigger = IStatus[1:0] == ITrigger[1:0];
 
wire TempTriggerAND = ( (TempWpTrigger | ~WpTriggerValid)
& (TempBpTrigger | ~BpTriggerValid)
& (TempLSSTrigger | ~LSSTriggerValid)
& (TempITrigger | ~ITriggerValid)
)
& (WpTriggerValid | BpTriggerValid | LSSTriggerValid | ITriggerValid);
 
wire TempTriggerOR = ( (TempWpTrigger & WpTriggerValid)
| (TempBpTrigger & BpTriggerValid)
| (TempLSSTrigger & LSSTriggerValid)
| (TempITrigger & ITriggerValid)
);
 
wire Trigger = TraceEnable & (~TriggerOper[1]? 1 : // any
TriggerOper[0]? TempTriggerAND : TempTriggerOR // AND : OR
);
 
/**********************************************************************************
* *
* Generation of the qualifier *
* *
**********************************************************************************/
wire TempWpQualifier = |(Wp[10:0] & WpQualif[10:0]);
wire TempBpQualifier = Bp & BpQualif;
wire TempLSSQualifier = LsStatus[3:0] == LSSQualif[3:0];
wire TempIQualifier = IStatus[1:0] == IQualif[1:0];
 
wire TempQualifierAND = ( (TempWpQualifier | ~WpQualifValid)
& (TempBpQualifier | ~BpQualifValid)
& (TempLSSQualifier | ~LSSQualifValid)
& (TempIQualifier | ~IQualifValid)
)
& (WpQualifValid | BpQualifValid | LSSQualifValid | IQualifValid);
 
wire TempQualifierOR = ( (TempWpQualifier & WpQualifValid)
| (TempBpQualifier & BpQualifValid)
| (TempLSSQualifier & LSSQualifValid)
| (TempIQualifier & IQualifValid)
);
 
 
wire Stop;
wire Qualifier = TraceEnable & ~Stop & (~QualifOper[1]? 1 : // any
QualifOper[0]? TempQualifierAND : TempQualifierOR // AND : OR
);
 
/**********************************************************************************
* *
* Generation of the stop signal *
* *
**********************************************************************************/
wire TempWpStop = |(Wp[10:0] & WpStop[10:0]);
wire TempBpStop = Bp & BpStop;
wire TempLSSStop = LsStatus[3:0] == LSSStop[3:0];
wire TempIStop = IStatus[1:0] == IStop[1:0];
 
wire TempStopAND = ( (TempWpStop | ~WpStopValid)
& (TempBpStop | ~BpStopValid)
& (TempLSSStop | ~LSSStopValid)
& (TempIStop | ~IStopValid)
)
& (WpStopValid | BpStopValid | LSSStopValid | IStopValid);
 
wire TempStopOR = ( (TempWpStop & WpStopValid)
| (TempBpStop & BpStopValid)
| (TempLSSStop & LSSStopValid)
| (TempIStop & IStopValid)
);
 
 
assign Stop = TraceEnable & (~StopOper[1]? 0 : // nothing
StopOper[0]? TempStopAND : TempStopOR // AND : OR
);
 
 
 
/**********************************************************************************
* *
* Generation of the TriggerLatch *
* *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
TriggerLatch<=#Tp 0;
else
if(TriggerLatch & ~TraceEnable)
TriggerLatch<=#Tp 0;
else
if(Trigger)
TriggerLatch<=#Tp 1;
end
 
 
 
 
/**********************************************************************************
* *
* TraceEnable Synchronization *
* *
**********************************************************************************/
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
begin
TraceEnable_d<=#Tp 0;
TraceEnable<=#Tp 0;
end
else
begin
TraceEnable_d<=#Tp TraceEnable_reg;
TraceEnable<=#Tp TraceEnable_d;
end
end
 
 
 
 
/**********************************************************************************
* *
* RiscStall, counter and pointers generation *
* *
**********************************************************************************/
reg BufferFullDetected;
wire [`OPSELECTIONCOUNTER-1:0] RecEnable;
 
wire BufferFull = Counter[`TRACECOUNTERWIDTH:0]==`TRACEBUFFERLENGTH;
wire BufferEmpty = Counter[`TRACECOUNTERWIDTH:0]==0;
wire IncrementCounter = RiscStall_q & ~(BufferFull | BufferFullDetected) & Qualifier & RecEnable[StallCounter];
wire IncrementPointer = RiscStall_q & (~BufferFull | ContinMode) & Qualifier & RecEnable[StallCounter];
 
wire WriteSample = IncrementPointer;
 
wire Decrement = ReadBuffer & ~BufferEmpty & (~ContinMode | ContinMode & ~TraceEnable);
wire CounterEn = IncrementCounter ^ Decrement;
 
wire SyncResetCpuStall;
wire ResetStallCounter;
reg BufferFull_q;
reg BufferFull_2q;
 
reg Qualifier_mclk;
 
always @(posedge Mclk)
begin
Qualifier_mclk<=#Tp Qualifier;
BufferFull_q<=#Tp BufferFull;
BufferFull_2q<=#Tp BufferFull_q;
RiscStall_q <=#Tp RiscStall_O;
end
 
 
wire FirstCpuStall = Qualifier & ~Qualifier_mclk & TriggerLatch |
Qualifier_mclk & Trigger & ~TriggerLatch |
Qualifier & Trigger & ~Qualifier_mclk & ~TriggerLatch ;
 
 
//wire SyncSetCpuStall = Qualifier_mclk & TriggerLatch &
 
wire SyncSetCpuStall = RiscStall_O & ~RiscStall_q |
Qualifier_mclk & TriggerLatch &
(
(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
(~ContinMode & ~BufferFull_q & BufferFull_2q & StallCounter==0) |
( ContinMode & StallCounter==`OPSELECTIONCOUNTER-1)
);
 
assign SyncResetCpuStall = (
(~ContinMode & ~BufferFull & ~BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-2) |
(~ContinMode & ~BufferFull & BufferFull_q & StallCounter==`OPSELECTIONCOUNTER-1) |
( ContinMode & StallCounter==`OPSELECTIONCOUNTER-2)
);
 
assign RiscStall_O = FirstCpuStall | RiscStall;
 
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
Counter<=#Tp 0;
else
if(CounterEn)
if(IncrementCounter)
Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] + 1;
else
Counter[`TRACECOUNTERWIDTH:0]<=#Tp Counter[`TRACECOUNTERWIDTH:0] - 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
WritePointer<=#Tp 0;
else
if(IncrementPointer)
WritePointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
ReadPointer<=#Tp 0;
else
if(Decrement & ~ContinMode | Decrement & ContinMode & ~TraceEnable)
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp ReadPointer[`TRACECOUNTERWIDTH-1:0] + 1;
else
if(ContinMode & IncrementPointer & (BufferFull | BufferFullDetected))
ReadPointer[`TRACECOUNTERWIDTH-1:0]<=#Tp WritePointer[`TRACECOUNTERWIDTH-1:0] + 1;
end
 
always @(posedge Mclk)
begin
if(~TraceEnable)
BufferFullDetected<=#Tp 0;
else
if(ContinMode & BufferFull)
BufferFullDetected<=#Tp 1;
end
 
 
always @(posedge Mclk or posedge Reset)
begin
if(Reset)
RiscStall<=#Tp 0;
else
if(SyncResetCpuStall)
RiscStall<=#Tp 0;
else
if(SyncSetCpuStall)
RiscStall<=#Tp 1;
end
 
 
always @(posedge Mclk)
begin
if(ResetStallCounter)
StallCounter<=#Tp 0;
else
if(RiscStall_q & (~BufferFull | ContinMode))
StallCounter<=#Tp StallCounter+1;
end
 
assign ResetStallCounter = StallCounter==(`OPSELECTIONCOUNTER-1) & ~BufferFull | Reset;
 
 
/**********************************************************************************
* *
* Valid status *
* *
**********************************************************************************/
wire Valid = ~BufferEmpty;
 
 
/**********************************************************************************
* *
* Writing and reading the sample to/from the buffer *
* *
**********************************************************************************/
always @ (posedge Mclk)
begin
if(WriteSample)
Buffer[WritePointer[`TRACECOUNTERWIDTH-1:0]]<={DataIn, 1'b0, OpSelect[`OPSELECTWIDTH-1:0]};
end
 
assign TraceChain = {Buffer[ReadPointer], 3'h0, Valid};
 
 
/**********************************************************************************
* *
* Operation select (to select which kind of data appears on the DATAIN lines) *
* *
**********************************************************************************/
assign OpSelect[`OPSELECTWIDTH-1:0] = StallCounter[`OPSELECTWIDTH-1:0];
 
 
 
/**********************************************************************************
* *
* Selecting which parts are going to be recorded as part of the sample *
* *
**********************************************************************************/
assign RecEnable = {1'b0, RecordINSTR, RecordWriteSPR, RecordReadSPR, RecordSDATA, RecordLDATA, RecordLSEA, RecordPC};
 
 
endmodule
/verilog/timescale.v
0,0 → 1,57
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
 
 
`timescale 1ns / 1ns
/README.txt
0,0 → 1,114
//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is avaliable in this README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
// Revision 1.2 2001/06/01 22:22:35 mohor
// This is a backup. It is not a fully working version. Not for use, yet.
//
// Revision 1.1 2001/05/18 13:12:09 mohor
// Header changed. All additional information is now avaliable in this README.txt file.
//
//
 
 
 
PROJECT:
SoC/OpenRISC Development (debug) Interface
 
 
PROJECT AND DOCUMENTATION ON THE WEB:
 
The project that this files are part of is avaliable on the opencores
web page:
 
http://www.opencores.org/cores/DebugInterface/
 
Documentation can also be found there. For direct download of the
documentation go to:
 
http://www.opencores.org/cgi-bin/cvsget.cgi/dbg_interface/doc/DbgSupp.pdf
 
 
 
 
OVERVIEW (main Features):
Development Interface is used for development purposes
(Boundary Scan testing and debugging). It is an interface
between the RISC, peripheral cores and any commercial
debugger/emulator or BS testing device. The external
debugger or BS tester connects to the core via JTAG port.
The Development Port also contains a trace and support for
tracing the program flow, execution coverage and profiling
the code.
 
dbg_tb.v is a testbench file.
file_communication.v is used for simulating the whole design together with the
debugger through two files that make a JTAG interface
dbg_top.v is top level module of the development interface design
 
 
 
COMPATIBILITY:
 
- WISHBONE rev B.1
- IEEE 1149.1 (JTAG)
 
 
 
KNOWN PROBLEMS (limits):
- RISC changes Watchpoints and breakpoints on rising edge of the
Mclk clock signal. Simulation should do the same.
 
 
 
TO DO:
- Add a WISHBONE master support if needed
- Add support for boundary scan (This is already done, but not yet incorporated in the design)
 

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