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URL https://opencores.org/ocsvn/de1_olpcl2294_system/de1_olpcl2294_system/trunk

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    /de1_olpcl2294_system
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Rev 7 → Rev 8

/trunk/src/qaz_system.v
0,0 → 1,126
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module qaz_system(
input [31:0] sys_data_i,
output [31:0] sys_data_o,
input [31:0] sys_addr_i,
input [3:0] sys_sel_i,
input sys_we_i,
input sys_cyc_i,
input sys_stb_i,
output sys_ack_o,
output sys_err_o,
output sys_rty_o,
input async_rst_i,
output [6:0] hex0,
output [6:0] hex1,
output [6:0] hex2,
output [6:0] hex3,
input sys_clk_i,
output sys_rst_o
);
 
//---------------------------------------------------
// register encoder
reg [3:0] register_offset_r;
always @(*)
case( sys_addr_i[19:0] )
20'h0_0000: register_offset_r = 4'h0;
20'h0_0004: register_offset_r = 4'h4;
default: register_offset_r = 4'hf;
endcase
//---------------------------------------------------
// register offset 0x0 -- system control register
reg sys_rst_r;
always @( posedge sys_clk_i )
if( sys_rst_o )
sys_rst_r <= 1'h0;
else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h0) )
sys_rst_r <= sys_data_i[0];
wire [31:0] sys_register_0 = { 31'b0, sys_rst_r };
//---------------------------------------------------
// register offset 0x4 -- hex led display register
reg [31:0] sys_register_4;
always @( posedge sys_clk_i )
if( sys_rst_o )
sys_register_4 <= 32'h0000ffff;
else if( (sys_cyc_i & sys_stb_i & sys_we_i) & (register_offset_r == 4'h4) )
sys_register_4 <= sys_data_i;
//---------------------------------------------------
// register mux
reg [31:0] sys_data_o_r;
always @(*)
case( register_offset_r )
4'h0: sys_data_o_r = sys_register_0;
4'h4: sys_data_o_r = sys_register_4;
4'hf: sys_data_o_r = 32'h1bad_c0de;
default: sys_data_o_r = 32'h1bad_c0de;
endcase
 
//---------------------------------------------------
// sync reset
sync
i_sync_reset(
.async_sig( async_rst_i | sys_rst_r ),
.sync_out(sys_rst_o),
.clk(sys_clk_i)
);
//---------------------------------------------------
// hex led encoders
hex_led_encoder
i_hex0(
.encoder(hex0),
.nibble(sys_register_4[3:0])
);
hex_led_encoder
i_hex1(
.encoder(hex1),
.nibble(sys_register_4[7:4])
);
hex_led_encoder
i_hex2(
.encoder(hex2),
.nibble(sys_register_4[11:8])
);
hex_led_encoder
i_hex3(
.encoder(hex3),
.nibble(sys_register_4[15:12])
);
//---------------------------------------------------
// outputs
assign sys_data_o = sys_data_o_r;
assign sys_ack_o = sys_cyc_i & sys_stb_i;
assign sys_err_o = 1'b0;
assign sys_rty_o = 1'b0;
 
endmodule
 
/trunk/src/top.v
99,15 → 99,15
wire sys_clk = clock_24[0];
//---------------------------------------------------
// sync reset
sync
i_sync_reset(
.async_sig(~key[0]),
.sync_out(sys_rst),
.clk(sys_clk)
);
// //---------------------------------------------------
// // sync reset
// sync
// i_sync_reset(
// .async_sig(~key[0]),
// .sync_out(sys_rst),
// .clk(sys_clk)
// );
//
 
//---------------------------------------------------
// FLED
347,10 → 347,16
.s2_err_i(s2_err_i),
.s2_rty_i(s2_rty_i),
// Slave 3 Interface
.s3_data_i(32'h0000_0000),
.s3_ack_i(1'b0),
.s3_err_i(1'b0),
.s3_rty_i(1'b0),
.s3_data_i(s3_data_i),
.s3_data_o(s3_data_o),
.s3_addr_o(s3_addr_o),
.s3_sel_o(s3_sel_o),
.s3_we_o(s3_we_o),
.s3_cyc_o(s3_cyc_o),
.s3_stb_o(s3_stb_o),
.s3_ack_i(s3_ack_i),
.s3_err_i(s3_err_i),
.s3_rty_i(s3_rty_i),
// Slave 4 Interface
.s4_data_i(32'h0000_0000),
.s4_ack_i(1'b0),
465,7 → 471,7
.wb_clk_i(sys_clk),
.wb_rst_i(sys_rst),
.wb_cyc_i(s1_cyc_o),
.wb_adr_i( {24'b0, s1_addr_o[7:0]} ),
.wb_adr_i( s1_addr_o[7:0] ),
.wb_dat_i(s1_data_o),
.wb_sel_i(s1_sel_o),
.wb_we_i(s1_we_o),
505,7 → 511,7
.wb_clk_i(sys_clk),
.wb_rst_i(sys_rst),
.wb_cyc_i(s2_cyc_o),
.wb_adr_i( {24'b0, s2_addr_o[7:0]} ),
.wb_adr_i( s2_addr_o[7:0] ),
.wb_dat_i(s2_data_o),
.wb_sel_i(s2_sel_o),
.wb_we_i(s2_we_o),
530,6 → 536,32
//---------------------------------------------------
// GPIO b
qaz_system
i_qaz_system(
.sys_data_i(s3_data_o),
.sys_data_o(s3_data_i),
.sys_addr_i(s3_addr_o),
.sys_sel_i(s3_sel_o),
.sys_we_i(s3_we_o),
.sys_cyc_i(s3_cyc_o),
.sys_stb_i(s3_stb_o),
.sys_ack_o(s3_ack_i),
.sys_err_o(s3_err_i),
.sys_rty_o(s3_rty_i),
.async_rst_i(~key[0]),
.hex0(gpio_a_aux_i[6:0]),
.hex1(gpio_a_aux_i[14:8]),
.hex2(gpio_a_aux_i[22:16]),
.hex3(gpio_a_aux_i[30:24]),
.sys_clk_i(sys_clk),
.sys_rst_o(sys_rst)
);
//---------------------------------------------------
// IO pads
genvar i;
580,14 → 612,18
assign hex1 = gpio_a_io_buffer_o[14:8];
assign hex2 = gpio_a_io_buffer_o[22:16];
assign hex3 = gpio_a_io_buffer_o[30:24];
assign gpio_a_aux_i = 32'b0;
assign gpio_a_aux_i[7] = 1'b0;
assign gpio_a_aux_i[15] = 1'b0;
assign gpio_a_aux_i[23] = 1'b0;
assign gpio_a_aux_i[31] = 1'b0;
assign gpio_a_ext_pad_i = 32'b0;
assign ledg = gpio_b_io_buffer_o[7:0];
assign ledr = gpio_b_io_buffer_o[17:8];
assign gpio_b_aux_i = { 24'b0, fled } ;
assign gpio_b_ext_pad_i = { key, sw, 18'b0};
assign gpio_b_ext_pad_i = { key, sw, 18'b0 };
assign gpio_1[35] = ~gpio_b_inta_o;
endmodule
 
/trunk/src/hex_led_encoder.v
0,0 → 1,48
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`include "timescale.v"
 
 
module
hex_led_encoder(
output [6:0] encoder,
input [3:0] nibble
);
 
//---------------------------------------------------
// hex encoder
reg [6:0] hex_led_encoder_r;
always @(*)
case( nibble )
4'b0000: hex_led_encoder_r = 7'h3f;
4'b0001: hex_led_encoder_r = 7'h06;
4'b0010: hex_led_encoder_r = 7'h5b;
4'b0011: hex_led_encoder_r = 7'h4f;
4'b0100: hex_led_encoder_r = 7'h66;
4'b0101: hex_led_encoder_r = 7'h6d;
4'b0110: hex_led_encoder_r = 7'h7d;
4'b0111: hex_led_encoder_r = 7'h07;
4'b1000: hex_led_encoder_r = 7'h7f;
4'b1001: hex_led_encoder_r = 7'h6f;
4'b1010: hex_led_encoder_r = 7'h77;
4'b1011: hex_led_encoder_r = 7'h7c;
4'b1100: hex_led_encoder_r = 7'h39;
4'b1101: hex_led_encoder_r = 7'h5e;
4'b1110: hex_led_encoder_r = 7'h79;
4'b1111: hex_led_encoder_r = 7'h71;
default: hex_led_encoder_r = 7'h7f;
endcase
//---------------------------------------------------
// outputs
assign encoder = ~hex_led_encoder_r;
endmodule
/trunk/src/wb_conmax_defines.v
38,31 → 38,9
 
// CVS Log
//
// $Id: wb_conmax_defines.v,v 1.1 2009/10/15 01:06:17 kenagy Exp $
//
// $Date: 2009/10/15 01:06:17 $
// $Revision: 1.1 $
// $Author: kenagy $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: wb_conmax_defines.v,v $
// Revision 1.1 2009/10/15 01:06:17 kenagy
// no message
//
// Revision 1.1 2009/03/25 22:16:56 kenagy
// no message
//
// Revision 1.1 2009/02/19 23:49:39 kenagy
// no message
//
// Revision 1.1 2009/02/19 20:11:33 kenagy
// no message
//
// Revision 1.1 2008/06/30 20:58:52 kenagy
// no message
//
// Revision 1.2 2002/10/03 05:40:07 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
/trunk/sim/tests/debug/tb_dut.v
2,9 → 2,10
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
`include "timescale.v"
 
 
module tb_dut(
input tb_clk,
input tb_rst
12,6 → 13,229
 
 
// --------------------------------------------------------------------
// wires
wire [3:0] boot_strap = 4'b0010;
 
 
// --------------------------------------------------------------------
// de1 wires
wire [1:0] clock_24;
wire [1:0] clock_27;
wire clock_50;
wire ext_clock;
wire [3:0] key;
wire [9:0] sw;
wire [6:0] hex0;
wire [6:0] hex1;
wire [6:0] hex2;
wire [6:0] hex3;
wire [7:0] ledg;
wire [9:0] ledr;
wire uart_txd;
wire uart_rxd;
wire [15:0] dram_dq;
wire [11:0] dram_addr;
wire dram_ldqm;
wire dram_udqm;
wire dram_we_n;
wire dram_cas_n;
wire dram_ras_n;
wire dram_cs_n;
wire dram_ba_0;
wire dram_ba_1;
wire dram_clk;
wire dram_cke;
wire [7:0] fl_dq;
wire [21:0] fl_addr;
wire fl_we_n;
wire fl_rst_n;
wire fl_oe_n;
wire fl_ce_n;
wire [15:0] sram_dq;
wire [17:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire sd_dat;
wire sd_dat3;
wire sd_cmd;
wire sd_clk;
wire i2c_sdat;
wire i2c_sclk;
wire ps2_dat;
wire ps2_clk;
wire tdi;
wire tck;
wire tcs;
wire tdo;
wire vga_hs;
wire vga_vs;
wire [3:0] vga_r;
wire [3:0] vga_g;
wire [3:0] vga_b;
wire aud_adclrck;
wire aud_adcdat;
wire aud_daclrck;
wire aud_dacdat;
wire aud_bclk;
wire aud_xck;
wire [35:0] gpio_0;
wire [35:0] gpio_1;
 
 
// --------------------------------------------------------------------
// fpga top
assign clock_24 = {1'b0, tb_clk};
assign sw = {6'b000000, boot_strap};
assign key = {3'b000, ~tb_rst};
 
top
i_top(
//////////////////////// Clock Input ////////////////////////
.clock_24( clock_24 ), // 24 MHz
.clock_27(clock_27), // 27 MHz
.clock_50(clock_50), // 50 MHz
.ext_clock(ext_clock), // External Clock
//////////////////////// Push Button ////////////////////////
.key( key ), // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
.sw( sw ), // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
.hex0(hex0), // Seven Segment Digit 0
.hex1(hex1), // Seven Segment Digit 1
.hex2(hex2), // Seven Segment Digit 2
.hex3(hex3), // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
.ledg(ledg), // LED Green[7:0]
.ledr(ledr), // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
.uart_txd(uart_txd), // UART Transmitter
.uart_rxd(uart_rxd), // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
.dram_dq(dram_dq), // SDRAM Data bus 16 Bits
.dram_addr(dram_addr), // SDRAM Address bus 12 Bits
.dram_ldqm(dram_ldqm), // SDRAM Low-byte Data Mask
.dram_udqm(dram_udqm), // SDRAM High-byte Data Mask
.dram_we_n(dram_we_n), // SDRAM Write Enable
.dram_cas_n(dram_cas_n), // SDRAM Column Address Strobe
.dram_ras_n(dram_ras_n), // SDRAM Row Address Strobe
.dram_cs_n(dram_cs_n), // SDRAM Chip Select
.dram_ba_0(dram_ba_0), // SDRAM Bank Address 0
.dram_ba_1(dram_ba_1), // SDRAM Bank Address 0
.dram_clk(dram_clk), // SDRAM Clock
.dram_cke(dram_cke), // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
.fl_dq(fl_dq), // FLASH Data bus 8 Bits
.fl_addr(fl_addr), // FLASH Address bus 22 Bits
.fl_we_n(fl_we_n), // FLASH Write Enable
.fl_rst_n(fl_rst_n), // FLASH Reset
.fl_oe_n(fl_oe_n), // FLASH Output Enable
.fl_ce_n(fl_ce_n), // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
.sram_dq(sram_dq), // SRAM Data bus 16 Bits
.sram_addr(sram_addr), // SRAM Address bus 18 Bits
.sram_ub_n(sram_ub_n), // SRAM High-byte Data Mask
.sram_lb_n(sram_lb_n), // SRAM Low-byte Data Mask
.sram_we_n(sram_we_n), // SRAM Write Enable
.sram_ce_n(sram_ce_n), // SRAM Chip Enable
.sram_oe_n(sram_oe_n), // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
.sd_dat(sd_dat), // SD Card Data
.sd_dat3(sd_dat3), // SD Card Data 3
.sd_cmd(sd_cmd), // SD Card Command Signal
.sd_clk(sd_clk), // SD Card Clock
//////////////////////// I2C ////////////////////////////////
.i2c_sdat(i2c_sdat), // I2C Data
.i2c_sclk(i2c_sclk), // I2C Clock
//////////////////////// PS2 ////////////////////////////////
.ps2_dat(ps2_dat), // PS2 Data
.ps2_clk(ps2_clk), // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
.tdi(tdi), // CPLD -> FPGA (data in)
.tck(tck), // CPLD -> FPGA (clk)
.tcs(tcs), // CPLD -> FPGA (CS)
.tdo(tdo), // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
.vga_hs(vga_hs), // VGA H_SYNC
.vga_vs(vga_vs), // VGA V_SYNC
.vga_r(vga_r), // VGA Red[3:0]
.vga_g(vga_g), // VGA Green[3:0]
.vga_b(vga_b), // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
.aud_adclrck(aud_adclrck), // Audio CODEC ADC LR Clock
.aud_adcdat(aud_adcdat), // Audio CODEC ADC Data
.aud_daclrck(aud_daclrck), // Audio CODEC DAC LR Clock
.aud_dacdat(aud_dacdat), // Audio CODEC DAC Data
.aud_bclk(aud_bclk), // Audio CODEC Bit-Stream Clock
.aud_xck(aud_xck), // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
.gpio_0(gpio_0), // GPIO Connection 0
.gpio_1(gpio_1) // GPIO Connection 1
);
 
 
// --------------------------------------------------------------------
// IS61LV25616
IS61LV25616
i_IS61LV25616 (
.A(sram_addr),
.IO(sram_dq),
.CE_(sram_ce_n),
.OE_(sram_oe_n),
.WE_(sram_we_n),
.LB_(sram_lb_n),
.UB_(sram_ub_n)
);
 
 
// --------------------------------------------------------------------
// s29al032d_00
s29al032d_00
i_s29al032d_00(
.A21(fl_addr[21]),
.A20(fl_addr[20]),
.A19(fl_addr[19]),
.A18(fl_addr[18]),
.A17(fl_addr[17]),
.A16(fl_addr[16]),
.A15(fl_addr[15]),
.A14(fl_addr[14]),
.A13(fl_addr[13]),
.A12(fl_addr[12]),
.A11(fl_addr[11]),
.A10(fl_addr[10]),
.A9(fl_addr[9]),
.A8(fl_addr[8]),
.A7(fl_addr[7]),
.A6(fl_addr[6]),
.A5(fl_addr[5]),
.A4(fl_addr[4]),
.A3(fl_addr[3]),
.A2(fl_addr[2]),
.A1(fl_addr[1]),
.A0(fl_addr[0]),
.DQ7(fl_dq[7]),
.DQ6(fl_dq[6]),
.DQ5(fl_dq[5]),
.DQ4(fl_dq[4]),
.DQ3(fl_dq[3]),
.DQ2(fl_dq[2]),
.DQ1(fl_dq[1]),
.DQ0(fl_dq[0]),
.CENeg(fl_ce_n),
.OENeg(fl_oe_n),
.WENeg(fl_we_n),
.RESETNeg(fl_rst_n),
.ACC(),
.RY()
);
 
 
// --------------------------------------------------------------------
// async_mem_master
wire [31:0] mem_d;
wire [31:0] mem_a;
20,80 → 244,21
wire mem_we_n;
wire mem_cs_n;
async_mem_master
assign gpio_0[23:0] = mem_a[23:0];
async_mem_master #( .ce_setup(10), .op_hold(15) )
async_mem(
.mem_d(mem_d),
.mem_a(mem_a),
.mem_oe_n(mem_oe_n),
.mem_bls_n(mem_bls_n),
.mem_we_n(mem_we_n),
.mem_cs_n(mem_cs_n),
.mem_d( gpio_1[31:0] ),
.mem_a( mem_a ),
.mem_oe_n( gpio_0[30] ),
.mem_bls_n( { gpio_0[26], gpio_0[27], gpio_0[28], gpio_0[29] } ),
.mem_we_n( gpio_0[25] ),
.mem_cs_n( gpio_0[24] ),
 
.tb_clk(tb_clk),
.tb_rst(tb_rst)
);
 
// --------------------------------------------------------------------
// wb_async_mem_bridge
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_o;
wire [3:0] wb_sel_o;
wire wb_we_o;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_ack_i;
wire wb_err_i;
wire wb_rty_i;
wb_async_mem_bridge
i_wb_async_mem_bridge(
.wb_data_i(wb_data_i),
.wb_data_o(wb_data_o),
.wb_addr_o(wb_addr_o),
.wb_sel_o(wb_sel_o),
.wb_we_o(wb_we_o),
.wb_cyc_o(wb_cyc_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.mem_d(mem_d),
.mem_a(mem_a),
.mem_oe_n(mem_oe_n),
.mem_bls_n(mem_bls_n),
.mem_we_n(mem_we_n),
.mem_cs_n(mem_cs_n),
.wb_clk_i(tb_clk),
.wb_rst_i(tb_rst)
);
 
// --------------------------------------------------------------------
// wb_slave_model
wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
i_wb_slave_model(
.clk_i(tb_clk),
.rst_i(tb_rst),
.dat_o(wb_data_i),
.dat_i(wb_data_o),
.adr_i(wb_addr_o),
.cyc_i(wb_cyc_o),
.stb_i(wb_stb_o),
.we_i(wb_we_o),
.sel_i(wb_sel_o),
.ack_o(wb_ack_i),
.err_o(wb_err_i),
.rty_o(wb_rty_i)
);
endmodule
 
 
/trunk/sim/tests/debug/debug.mpf
1,4 → 1,4
; Copyright 1991-2008 Mentor Graphics Corporation
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
15,14 → 15,86
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
mtiAvm = $MODEL_TECH/../avm
mtiOvm = $MODEL_TECH/../ovm
mtiUPF = $MODEL_TECH/../upf_lib
floatfixlib = $MODEL_TECH/../floatfixlib
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
;mvc_lib = $MODEL_TECH/../mvc_lib
 
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
72,12 → 144,6
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Turn off PSL assertion warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
86,12 → 152,6
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Treat as errors:
; case statement static warnings
; warnings caused by aggregates that are not locally static
; Overrides NoCaseStaticError, NoOthersStaticError settings.
; PedanticErrors = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
107,9 → 167,6
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
117,10 → 174,6
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Perform default binding at compile time.
; Default is to do default binding at load time.
; BindAtCompile = 1;
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
129,85 → 182,13
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
; Run the 0-in compiler on the VHDL source files
; Default is off.
; ZeroIn = 1
[vlog]
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Turn on code coverage in VHDL design units. Default is off.
; Coverage = sbceft
 
; Turn off code coverage in VHDL subprograms. Default is on.
; CoverageSub = 0
 
; Automatically exclude VHDL case statement default branches.
; Default is to not exclude.
; CoverExcludeDefault = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
; values on signals in conditions and expressions, and to not automatically
; convert them to '1' and '0'. Default is to not convert.
; CoverRespectHandL = 0
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a VHDL condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
; Use this directory for compiler temporary files instead of "work/_temp"
; CompilerTempDir = /tmp
 
; Add VHDL-AMS declarations to package STANDARD
; Default is not to add
; AmsStandard = 1
 
; Range and length checking will be performed on array indices and discrete
; ranges, and when violations are found within subprograms, errors will be
; reported. Default is to issue warnings for violations, because subprograms
; may not be invoked.
; NoDeferSubpgmCheck = 0
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn on `protect compiler directive processing.
; Default is to ignore `protect directives.
; Protect = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
218,269 → 199,17
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn on bad option warning. Default is off.
; Show_BadOptionWarning = 1
 
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
; vlog95compat = 1
 
; Turn off PSL warning messages. Default is to show warnings.
; Show_PslChecksWarnings = 0
 
; Enable parsing of embedded PSL assertions. Default is enabled.
; EmbeddedPsl = 0
 
; Set the threshold for automatically identifying sparse Verilog memories.
; A memory with depth equal to or more than the sparse memory threshold gets
; marked as sparse automatically, unless specified otherwise in source code
; or by +nosparse commandline option of vlog or vopt.
; The default is 1M. (i.e. memories with depth equal
; to or greater than 1M are marked as sparse)
; SparseMemThreshold = 1048576
 
; Set the maximum number of iterations permitted for a generate loop.
; Restricting this permits the implementation to recognize infinite
; generate loops.
; GenerateLoopIterationMax = 100000
 
; Set the maximum depth permitted for a recursive generate instantiation.
; Restricting this permits the implementation to recognize infinite
; recursions.
; GenerateRecursionDepthMax = 200
 
; Run the 0-in compiler on the Verilog source files
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0-in compiler.
; Default is "".
; ZeroInOptions = ""
 
; Set the option to treat all files specified in a vlog invocation as a
; single compilation unit. The default value is set to 0 which will treat
; each file as a separate compilation unit as specified in the P1800 draft standard.
; MultiFileCompilationUnit = 1
 
; Turn on code coverage in Verilog design units. Default is off.
; Coverage = sbceft
 
; Automatically exclude Verilog case statement default branches.
; Default is to not automatically exclude defaults.
; CoverExcludeDefault = 1
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a Verilog condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
; Enable or disable Focused Expression Coverage analysis for conditions and
; expressions. Focused Expression Coverage data is provided by default when
; expression and/or condition coverage is active.
; CoverageFEC = 0
 
; Enable or disable short circuit evaluation of conditions and expressions when
; condition or expression coverage is active. Short circuit evaluation is enabled
; by default.
; CoverageShortCircuit = 0
 
 
; Turn on code coverage in VLOG `celldefine modules and modules included
; using vlog -v and -y. Default is off.
; CoverCells = 1
 
; Control compiler and VOPT optimizations that are allowed when
; code coverage is on. This is a number from 1 to 4, with the following
; meanings (the default is 3):
; 1 -- Turn off all optimizations that affect coverage reports.
; 2 -- Allow optimizations that allow large performance improvements
; by invoking sequential processes only when the data changes.
; This may make major reductions in coverage counts.
; 3 -- In addition, allow optimizations that may change expressions or
; remove some statements. Allow constant propagation. Allow VHDL
; subprogram inlining.
; 4 -- In addition, allow optimizations that may remove major regions of
; code by changing assignments to built-ins or removing unused
; signals. Change Verilog gates to continuous assignments.
; Allow VHDL FF recognition.
; CoverOpt = 3
 
; Specify the override for the default value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then LRM default
; value of 0 (zero) is used. This is a compile time option.
; SVCrossNumPrintMissingDefault = 0
 
; Setting following to 1 would cause creation of variables which
; would represent the value of Coverpoint expressions. This is used
; in conjunction with "SVCoverpointExprVariablePrefix" option
; in the modelsim.ini
; EnableSVCoverpointExprVariable = 0
 
; Specify the override for the prefix used in forming the variable names
; which represent the Coverpoint expressions. This is used in conjunction with
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
; The default prefix is "expr".
; The variable name is
; variable name => <prefix>_<coverpoint name>
; SVCoverpointExprVariablePrefix = expr
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
; in the [vsim] section can override this value.
; SVCovergroupGoalDefault = 100
 
; Override for the default value of the SystemVerilog covergroup,
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
; NOTE: It does not override specific assignments in SystemVerilog
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
; in the [vsim] section can override this value.
; SVCovergroupTypeGoalDefault = 100
 
; Specify the override for the default value of "strobe" option for the
; Covergroup Type. This is a compile time option which forces "strobe" to
; a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero). NOTE: This can be overriden by a runtime
; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
; SVCovergroupStrobeDefault = 0
 
; Specify the override for the default value of "merge_instances" option for
; the Covergroup Type. This is a compile time option which forces
; "merge_instances" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupMergeInstancesDefault = 0
 
; Specify the override for the default value of "per_instance" option for the
; Covergroup variables. This is a compile time option which forces "per_instance"
; to a user specified default value and supersedes SystemVerilog specified
; default value of '0'(zero).
; SVCovergroupPerInstanceDefault = 0
 
; Specify the override for the default value of "get_inst_coverage" option for the
; Covergroup variables. This is a compile time option which forces
; "get_inst_coverage" to a user specified default value and supersedes
; SystemVerilog specified default value of '0'(zero).
; SVCovergroupGetInstCoverageDefault = 0
 
;
; A space separated list of resource libraries that contain precompiled
; packages. The behavior is identical to using the "-L" switch.
;
; LibrarySearchPath = <path/lib> [<path/lib> ...]
LibrarySearchPath = mtiAvm mtiOvm mtiUPF
 
; The behavior is identical to the "-mixedansiports" switch. Default is off.
; MixedAnsiPorts = 1
 
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
; EnableTypeOf = 1
 
; Only allow lower case pragmas. Default is disabled.
; AcceptLowerCasePragmaOnly = 1
 
; Set the maximum depth permitted for a recursive include file nesting.
; IncludeRecursionDepthMax = 5
 
; Turn on fsm debug flow.
; FsmDebug = 1
 
; Turn off detection of FSMs having single bit current state variable.
; FsmSingle = 0
 
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
; Turn off detections of FSMs having x-assignment.
; FsmXAssign = 0
 
; List of file suffixes which will be read as SystemVerilog. White space
; in extensions can be specified with a back-slash: "\ ". Back-slashes
; can be specified with two consecutive back-slashes: "\\";
; SVFileExtensions = sv svp
 
; This setting is the same as the vlog -sv command line switch.
; Enables SystemVerilog features and keywords when true (1).
; When false (0), the rules of IEEE Std 1364-2001 are followed and
; SystemVerilog keywords are ignored.
; Svlog = 0
 
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
 
; Add C++ compiler options to the sccom command line by using this variable.
; CppOptions = -g
 
; Use custom C++ compiler located at this path rather than the default path.
; The path should point directly at a compiler executable.
; CppPath = /usr/bin/g++
 
; Enable verbose messages from sccom. Default is off.
; SccomVerbose = 1
 
; sccom logfile. Default is no logfile.
; SccomLogfile = sccom.log
 
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
 
; Control compiler optimizations that are allowed when
; code coverage is on. Refer to the comment for this in the [vlog] area.
; CoverOpt = 3
 
; Increase or decrease the maximum number of rows allowed in a UDP table
; implementing a vopt condition coverage or expression coverage expression.
; More rows leads to a longer compile time, but more expressions covered.
; CoverMaxUDPRows = 192
 
; Increase or decrease the maximum number of input patterns that are present
; in FEC table. This leads to a longer compile time with more expressions
; covered with FEC metric.
; CoverMaxFECRows = 192
 
[vsim]
; vopt flow
; Set to turn on automatic optimization of a design.
; Default is on
VoptFlow = 1
 
; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0
 
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; Disable certain code coverage exclusions automatically.
; Assertions and FSM are exluded from the code coverage by default
; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
; Or specify comma or space separated list
;AutoExclusionsDisable = fsm,assertions
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
489,96 → 218,39
UserTimeUnit = default
 
; Default run length
RunLength = 100 ns
RunLength = 10 us
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1
 
; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
; -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1
 
; Directives to license manager can be set either as single value or as
; space separated multi-values:
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license is not available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license (PE ONLY)
; noviewer Disable checkout of msimviewer and vsim-viewer license
; features (PE ONLY)
; noslvhdl Disable checkout of qhsimvh and vsim license features
; noslvlog Disable checkout of qhsimvl and vsimvlog license features
; nomix Disable checkout of msimhdlmix and hdlmix license features
; nolnl Disable checkout of msimhdlsim and hdlsim license features
; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
; features
; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
; hdlmix license features
; Single value:
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Multi-value:
; License = noqueue plus
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
; from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
; level), use MessageFormatBreak;
; - otherwise, use MessageFormat.
; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Error File - alternate file for storing error messages
; ErrorFile = error.log
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
 
 
; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name: # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1
 
; Default radix for all windows and commands.
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
585,12 → 257,6
; VSIM Startup command
; Startup = do startup.do
 
; VSIM Shutdown file
; Filename to save u/i formats and configurations.
; ShutdownFile = restart.do
; To explicitly disable auto save:
; ShutdownFile = --disable-auto-save
 
; File for saving command transcript
TranscriptFile = transcript
 
605,26 → 271,10
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Specify a unique path separator for the Signal Spy set of functions.
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /
 
; Used to control parsing of HDL identifiers input to the tool.
; This includes CLI commands, vsim/vopt/vlog/vcom options,
; string arguments to FLI/VPI/DPI calls, etc.
; If set to 1, accept either Verilog escaped Id syntax or
; VHDL extended id syntax, regardless of source language.
; If set to 0, the syntax of the source language must be used.
; Each identifier in a hierarchical name may need different syntax,
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
; GenerousIdentifierParsing = 1
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
631,12 → 281,6
; IgnoreError = 1
; IgnoreFailure = 1
 
; Disable System Verilog assertion messages
; IgnoreSVAInfo = 1
; IgnoreSVAWarning = 1
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
663,10 → 307,6
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
690,45 → 330,18
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
; The term "out-of-the-blue" refers to SystemVerilog export function calls
; made from C functions that don't have the proper context setup
; (as is the case when running under "DPI-C" import functions).
; When this is enabled, one can call a DPI export function
; (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Which default VPI object model should the tool conform to?
; The 1364 modes are Verilog-only, for backwards compatibility with older
; libraries, and SystemVerilog objects are not available in these modes.
;
; In the absence of a user-specified default, the tool default is the
; latest available LRM behavior.
; Options for PliCompatDefault are:
; VPI_COMPATIBILITY_VERSION_1364v1995
; VPI_COMPATIBILITY_VERSION_1364v2001
; VPI_COMPATIBILITY_VERSION_1364v2005
; VPI_COMPATIBILITY_VERSION_1800v2005
; VPI_COMPATIBILITY_VERSION_1800v2008
;
; Synonyms for each string are also recognized:
; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
 
 
; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
757,413 → 370,13
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Specify whether or not a WLF file should be optimized during
; simulation. If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
 
; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf
 
; Specify the WLF reader cache size limit for each open WLF file.
; The size is giving in megabytes. A value of 0 turns off the
; WLF cache.
; WLFSimCacheSize allows a different cache size to be set for
; simulation WLF file independent of post-simulation WLF file
; viewing. If WLFSimCacheSize is not set it defaults to the
; WLFCacheSize setting.
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
; WLFCacheSize = 2000
; WLFSimCacheSize = 500
 
; Specify the WLF file event collapse mode.
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
; 1 = Only record values of logged objects at the end of a simulator iteration.
; (same as -wlfcollapsedelta)
; 2 = Only record values of logged objects at the end of a simulator time step.
; (same as -wlfcollapsetime)
; The default is 1.
; WLFCollapseMode = 0
 
; Specify whether WLF file logging can use threads on multi-processor machines
; if 0, no threads will be used, if 1, threads will be used if the system has
; more than one processor
; WLFUseThreads = 1
 
; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0
 
; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1
 
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
; ScShowIeeeDeprecationWarnings = 1
 
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
; ScEnableScSignalWriteCheck = 1
 
; Set SystemC default time unit.
; Set to fs, ps, ns, us, ms, or sec with optional
; prefix of 1, 10, or 100. The default is 1 ns.
; The ScTimeUnit value is honored if it is coarser than Resolution.
; If ScTimeUnit is finer than Resolution, it is set to the value
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
; then the default time unit will be 1 ns. However if Resolution
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
ScTimeUnit = ns
 
; Set SystemC sc_main stack size. The stack size is set as an integer
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
; on the amount of data on the sc_main() stack and the memory required
; to succesfully execute the longest function call chain of sc_main().
ScMainStackSize = 10 Mb
 
; Turn on/off execution of remainder of sc_main upon quitting the current
; simulation session. If the cumulative length of sc_main() in terms of
; simulation time units is less than the length of the current simulation
; run upon quit or restart, sc_main() will be in the middle of execution.
; This switch gives the option to execute the remainder of sc_main upon
; quitting simulation. The drawback of not running sc_main till the end
; is memory leaks for objects created by sc_main. If on, the remainder of
; sc_main will be executed ignoring all delays. This may cause the simulator
; to crash if the code in sc_main is dependent on some simulation state.
; Default is on.
ScMainFinishOnQuit = 1
 
; Set the SCV relationship name that will be used to identify phase
; relations. If the name given to a transactor relation matches this
; name, the transactions involved will be treated as phase transactions
ScvPhaseRelationName = mti_phase
 
; Customize the vsim kernel shutdown behavior at the end of the simulation.
; Some common causes of the end of simulation are $finish (implicit or explicit),
; sc_stop(), tf_dofinish(), and assertion failures.
; This should be set to "ask", "exit", or "stop". The default is "ask".
; "ask" -- In batch mode, the vsim kernel will abruptly exit.
; In GUI mode, a dialog box will pop up and ask for user confirmation
; whether or not to quit the simulation.
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
; post-simulation tasks easier.
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
; Note: these ini variables can be overriden by the vsim command
; line switch "-onfinish <ask|stop|exit>".
OnFinish = ask
 
; Print "simstats" result at the end of simulation before shutdown.
; If this is enabled, the simstats result will be printed out before shutdown.
; The default is off.
; PrintSimStats = 1
 
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log
 
; Run simulator in assertion debug mode. Default is off.
; AssertionDebug = 1
 
; Turn on/off PSL/SVA concurrent assertion pass enable.
; For SVA, Default is on when the assertion has a pass action block, or
; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
; For PSL, Default is on only when vsim switch "-assertdebug" is used
; and the vopt "+acc=a" flag is active.
; AssertionPassEnable = 0
 
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
; AssertionFailEnable = 0
 
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = 1
 
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = 1
 
; Turn on/off PSL concurrent assertion pass log. Default is off.
; The flag does not affect SVA
; AssertionPassLog = 1
 
; Turn on/off PSL concurrent assertion fail log. Default is on.
; The flag does not affect SVA
; AssertionFailLog = 0
 
; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
; AssertionFailLocalVarLog = 0
 
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
; 0 = Continue 1 = Break 2 = Exit
; AssertionFailAction = 1
 
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
; AssertionActiveThreadMonitor = 1
 
; Control how many waveform rows will be used for displaying the active threads. Default is 5.
; AssertionActiveThreadMonitorLimit = 5
 
; Control how many thread start times will be preserved for ATV viewing for a given assertion
; instance. Default is -1 (ALL).
; ATVStartTimeKeepCount = -1
 
; Turn on/off code coverage
; CodeCoverage = 0
 
; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1
 
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
; is to include them.
; ToggleNoIntegers = 1
 
; Set the maximum number of values that are collected for toggle coverage of
; VHDL integers. Default is 100;
; ToggleMaxIntValues = 100
 
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
; for enumeration types. Default is to not include them.
; ToggleVlogIntegers = 1
 
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
; For unlimited width, set to 0.
; ToggleWidthLimit = 128
 
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
; reached this count, further activity on the bit is ignored. Default is 1.
; For unlimited counts, set to 0.
; ToggleCountLimit = 1
 
; Turn on/off all PSL/SVA cover directive enables. Default is on.
; CoverEnable = 0
 
; Turn on/off PSL/SVA cover log. Default is off.
; CoverLog = 1
 
; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
; CoverAtLeast = 2
 
; Set "limit" value for all PSL/SVA cover directives. Default is -1.
; Any positive integer, -1 for infinity.
; CoverLimit = 1
 
; Specify the coverage database filename.
; Default is "" (i.e. database is NOT automatically saved on close).
; UCDBFilename = vsim.ucdb
 
; Specify the maximum limit for the number of Cross (bin) products reported
; in XML and UCDB report against a Cross. A warning is issued if the limit
; is crossed.
; MaxReportRhsSVCrossProducts = 1000
 
; Specify the override for the "auto_bin_max" option for the Covergroups.
; If not specified then value from Covergroup "option" is used.
; SVCoverpointAutoBinMax = 64
 
; Specify the override for the value of "cross_num_print_missing"
; option for the Cross in Covergroups. If not specified then value
; specified in the "option.cross_num_print_missing" is used. This
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
; value specified by user in source file and any SVCrossNumPrintMissingDefault
; specified in modelsim.ini.
; SVCrossNumPrintMissing = 0
 
; Specify whether to use the value of "cross_num_print_missing"
; option in report and GUI for the Cross in Covergroups. If not specified then
; cross_num_print_missing is ignored for creating reports and displaying
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
; UseSVCrossNumPrintMissing = 0
 
; Specify the override for the value of "strobe" option for the
; Covergroup Type. If not specified then value in "type_option.strobe"
; will be used. This is runtime option which forces "strobe" to
; user specified value and supersedes user specified values in the
; SystemVerilog Code. NOTE: This also overrides the compile time
; default value override specified using "SVCovergroupStrobeDefault"
; SVCovergroupStrobe = 0
 
; Override for explicit assignments in source code to "option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
; SVCovergroupGoal = 100
 
; Override for explicit assignments in source code to "type_option.goal" of
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
; SVCovergroupTypeGoal = 100
 
; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
; builtin functions, and report. This setting changes the default values of
; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
; behavior if explicit assignments are not made on option.get_inst_coverage and
; type_option.merge_instances by the user. There are two vsim command line
; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
; The default value of this variable is 1
; SVCovergroup63Compatibility = 1
 
; Enable or disable generation of more detailed information about the sampling
; of covergroup, cross, and coverpoints. It provides the details of the number
; of times the covergroup instance and type were sampled, as well as details
; about why covergroup, cross and coverpoint were not covered. A non-zero value
; is to enable this feature. 0 is to disable this feature. Default is 0
; SVCovergroupSampleInfo = 0
 
; Specify the maximum number of Coverpoint bins in whole design for
; all Covergroups.
; MaxSVCoverpointBinsDesign = 2147483648
 
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
; MaxSVCoverpointBinsInst = 2147483648
 
; Specify the maximum number of Cross bins in whole design for
; all Covergroups.
; MaxSVCrossBinsDesign = 2147483648
 
; Specify maximum number of Cross bins in any instance of a Covergroup
; MaxSVCrossBinsInst = 2147483648
 
; Set weight for all PSL/SVA cover directives. Default is 1.
; CoverWeight = 2
 
; Check vsim plusargs. Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1
 
; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects. The list of shared objects should
; be whitespace delimited. This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so
 
; Run the 0in tools from within the simulator.
; Default is off.
; ZeroIn = 1
 
; Set the options to be passed to the 0in runtime tool.
; Default value set to "".
; ZeroInOptions = ""
 
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
; Sv_Seed = 0
 
; Maximum size of dynamic arrays that are resized during randomize().
; The default is 1000. A value of 0 indicates no limit.
; SolveArrayResizeMax = 1000
 
; Error message severity when randomize() failure is detected (SystemVerilog).
; The default is 0 (no error).
; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
; SolveFailSeverity = 0
 
; Enable/disable debug information for randomize() failures (SystemVerilog).
; The default is 0 (disabled). Set to 1 to enable.
; SolveFailDebug = 0
 
; When SolveFailDebug is enabled, this value specifies the algorithm used to
; discover conflicts between constraints for randomize() failures.
; The default is "many".
;
; Valid schemes are:
; "many" = best for determining conflicts due to many related constraints
; "few" = best for determining conflicts due to few related constraints
;
; SolveFailDebugScheme = many
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum number of constraint subsets that will be tested for
; conflicts.
; The default is 0 (no limit).
; SolveFailDebugLimit = 0
 
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
; specifies the maximum size of constraint subsets that will be tested for
; conflicts.
; The default value is 0 (no limit).
; SolveFailDebugMaxSet = 0
 
; Maximum size of the solution graph that may be generated during randomize().
; This value can be used to force randomize() to abort if the complexity of
; the constraint scenario (both in memory and time spent during evaluation)
; exceeds the specified limit. This value is specified in 1000s of nodes.
; The default is 10000. A value of 0 indicates no limit.
; SolveGraphMaxSize = 10000
 
; Use SolveFlags to specify options that will guide the behavior of the
; constraint solver. These options may improve the performance of the
; constraint solver for some testcases, and decrease the performance of
; the constraint solver for others.
; The default value is "" (no options).
;
; Valid flags are:
; c = interleave bits of concatenation operands
; i = disable bit interleaving for >, >=, <, <= constraints
; n = disable bit interleaving for all constraints
; r = reverse bit interleaving
;
; SolveFlags =
 
; Specify random sequence compatiblity with a prior letter release. This
; option is used to get the same random sequences during simulation as
; as a prior letter release. Only prior letter releases (of the current
; number release) are allowed.
; Note: To achieve the same random sequences, solver optimizations and/or
; bug fixes introduced since the specified release may be disabled -
; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev =
 
; Environment variable expansion of command line arguments has been depricated
; in favor shell level expansion. Universal environment variable expansion
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this
; deprecated behavior. The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0
 
; Turn on/off collapsing of bus ports in VCD dumpports output
DumpportsCollapse = 1
 
; Location of Multi-Level Verification Component (MVC) installation.
; The default location is the product installation directory.
; MvcHome = $MODEL_TECH/...
 
[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
 
; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
; Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
; Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
1176,75 → 389,74
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of Verilog display system task messages and
; PLI/FLI print function call messages. The system tasks include
; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
; also include the analogous file I/O tasks that write to STDOUT
; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
; is to have messages appear only in the transcript. The other
; settings are to send messages to the wlf file only (messages that
; are recorded in the wlf file can be viewed in the MsgViewer) or
; to both the transcript and the wlf file. The valid values are
; tran {transcript only (default)}
; wlf {wlf file only}
; both {transcript and wlf file}
; displaymsgmode = tran
 
; Control transcripting of elaboration/runtime messages not
; addressed by the displaymsgmode setting. The default is to
; have messages appear in the transcript and recorded in the wlf
; file (messages that are recorded in the wlf file can be viewed
; in the MsgViewer). The other settings are to send messages
; only to the transcript or only to the wlf file. The valid
; values are
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 19
Project_Files_Count = 24
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync_edge_detect.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1254874408 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1255479331 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/tests/debug/tb_top.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1255537697 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1267555947 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/wb_async_mem_bridge.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1255560532 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/IS61LV25616AL.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1219274280 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/tests/debug/tb_dut.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1255481763 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/async_mem_master.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1255539623 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/top.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1255567218 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 1 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1033623607 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1251997300 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237927188 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/s29al032d_00.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1118235516 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/wb_slave_model.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1255480557 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/wb_async_mem_sm.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1258674946 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/hex_led_encoder.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1267549142 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/wb_async_mem_bridge.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1258674945 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/qaz_system.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1267555711 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/gpio/rtl/verilog/gpio_top.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1236702934 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1265047382 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/IS61LV25616AL.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1255568776 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/sim/models/async_mem_master.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1267472139 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/tests/debug/tb_dut.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1267553685 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/src/top.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1267550758 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = C:/qaz/_CVS_WORK/units/wb_async_mem_bridge/src/sync.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1254853079 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_20 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1033623609 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1265047382 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_22 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/s29al032d_00.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1255568776 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/models/wb_slave_model.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1255568776 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
1251,8 → 463,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
1280,6 → 490,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/qaz/_CVS_WORK/units/de1_olpcl2294_system/sim/tests/debug/tb_top.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/trunk/sim/tests/debug/tb_top.v
39,10 → 39,13
repeat(2) @(posedge tb_clk);
//
$display("\n^^^- \n");
dut.async_mem.async_mem_write( 32'h83300000, 32'h00000001, 4'b0000 );
repeat(6) @(posedge tb_clk);
dut.async_mem.async_mem_write( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(2) @(posedge tb_clk);
49,7 → 52,22
dut.async_mem.async_mem_cmp( 32'h83000000, 32'habbabeef, 4'b0000 );
repeat(4) @(posedge tb_clk);
dut.async_mem.async_mem_cmp( 32'h83300fff, 32'h1bad_c0de, 4'b0000 );
repeat(2) @(posedge tb_clk);
dut.async_mem.async_mem_write( 32'h83300004, 32'hcafe1a7e, 4'b0000 );
repeat(2) @(posedge tb_clk);
dut.async_mem.async_mem_cmp( 32'h83300004, 32'hcafe1a7e, 4'b0000 );
repeat(4) @(posedge tb_clk);
dut.async_mem.async_mem_write( 32'h83300000, 32'h00000001, 4'b0000 );
repeat(6) @(posedge tb_clk);
dut.async_mem.async_mem_cmp( 32'h83300004, 32'h0000ffff, 4'b0000 );
repeat(4) @(posedge tb_clk);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
/trunk/sw/ecos/diff_exclude.txt
0,0 → 1,3
CVS
eCos.hhc
eCos.hhp
/trunk/sw/ecos/ROM_slow/ROM_slow.ecm
51,10 → 51,6
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 0
};
102,3 → 98,27
cdl_option CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL {
user_value 2
};
 
 
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
# cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
# user_value 0
# };
 
# cdl_option CYGBLD_BUILD_GDB_STUBS {
# user_value 0
# };
 
# cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
# user_value 0
# };
 
# cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
# user_value 0
# };
 
 
/trunk/sw/ecos/debug/oc_gpio.c
0,0 → 1,69
//
//
//
 
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
 
#include <cyg/kernel/kapi.h>
 
#include "LPC22xx.h"
#include "lib_dbg_sh.h"
#include "oc_gpio.h"
 
 
cyg_mutex_t hex_led_lock;
 
 
void
hex_led_init( unsigned int data)
{
OC_GPIO_A_RGPIO_OE = 0x7f7f7f7f;
OC_GPIO_A_RGPIO_AUX = 0x7f7f7f7f;
 
cyg_mutex_init(&hex_led_lock);
*((unsigned int *)0x83300004) = data;
}
 
unsigned int
hex_led_command( unsigned int command, unsigned int data)
{
unsigned int ret_data = 0;
cyg_mutex_lock(&hex_led_lock);
switch (command) {
case DE1_HEX_LED_WRITE:
*((unsigned int *)0x83300004) = data;
break;
 
case DE1_HEX_LED_READ:
ret_data = *((unsigned int *)0x83300004);
break;
 
case DE1_HEX_LED_INCREMENT:
*((unsigned int *)0x83300004) += 1;
break;
 
default:
break;
}
cyg_mutex_unlock(&hex_led_lock);
return( ret_data );
}
 
 
void
fled_init( unsigned int data)
{
OC_GPIO_B_RGPIO_OE = 0x0003ffff;
OC_GPIO_B_RGPIO_OUT = data;
}
 
/trunk/sw/ecos/debug/main.c
10,10 → 10,57
 
#include "LPC22xx.h"
#include "lib_dbg_sh.h"
#include "oc_gpio.h"
 
extern void dbg_sh(void);
 
static cyg_interrupt int1;
static cyg_handle_t int1_handle;
 
 
//
// Interrupt service routine for interrupt 1.
//
cyg_uint32 interrupt_1_isr(
cyg_vector_t vector,
cyg_addrword_t data)
{
// Block this interrupt from occurring until
// the DSR completes.
cyg_interrupt_mask( vector );
// disable and clear gpio b intr
OC_GPIO_B_RGPIO_INTE &= 0x7fffffff;
OC_GPIO_B_RGPIO_INTS &= 0x7fffffff;
 
 
// Tell the processor that we have received
// the interrupt.
cyg_interrupt_acknowledge( vector );
 
// Tell the kernel that chained interrupt processing
// is done and the DSR needs to be executed next.
return( CYG_ISR_HANDLED | CYG_ISR_CALL_DSR );
}
 
//
// Deferred service routine for interrupt 1.
//
void interrupt_1_dsr(
cyg_vector_t vector,
cyg_ucount32 count,
cyg_addrword_t data)
{
hex_led_command( DE1_HEX_LED_INCREMENT, 0);
OC_GPIO_B_RGPIO_INTE |= 0x80000000;
// Allow this interrupt to occur again.
cyg_interrupt_unmask( vector );
}
 
 
/* now declare (and allocate space for) some kernel objects,
like the two threads we will use */
cyg_thread thread_s[2]; /* space for two thread objects */
27,31 → 74,27
cyg_thread_entry_t dbg_shell;
cyg_thread_entry_t simple_program;
 
/* and now a mutex to protect calls to the C library */
cyg_mutex_t cliblock;
 
/* we install our own startup routine which sets up threads */
void cyg_user_start(void)
{
// printf("Entering twothreads' cyg_user_start() function\n");
{
// enable cs3
PINSEL2 = 0x0f814924;
// configure BCFG3
*((unsigned int *)0xFFE0000C) = 0x20007de7;
// reset FPGA
*((unsigned int *)0x83300000) = 0x00000001;
cyg_thread_delay(10);
 
// configure gpio
*((unsigned int *)0x83200008) = 0x0003ffff;
*((unsigned int *)0x83200008) = 0x00000003;
*((unsigned int *)0x83200008) ^= 0x00000002;
fled_init(0x00000003);
hex_led_init(0x00);
 
cyg_mutex_init(&cliblock);
 
cyg_thread_create(4, dbg_shell, (cyg_addrword_t) 0,
"DBG Shell", (void *) stack[0], 4096,
&dbg_shell_thread, &thread_s[0]);
cyg_thread_create(4, simple_program, (cyg_addrword_t) 1,
"Thread B", (void *) stack[1], 4096,
&simple_threadB, &thread_s[1]);
58,6 → 101,39
 
cyg_thread_resume(dbg_shell_thread);
cyg_thread_resume(simple_threadB);
cyg_vector_t int1_vector = CYGNUM_HAL_INTERRUPT_EINT3;
// cyg_priority_t int1_priority = CYGNUM_HAL_PRI_HIGH;
cyg_priority_t int1_priority = 0;
 
//
// Create interrupt 1.
//
cyg_interrupt_create(
int1_vector,
int1_priority,
0,
&interrupt_1_isr,
&interrupt_1_dsr,
&int1_handle,
&int1);
 
// Attach the interrupt created to the vector.
cyg_interrupt_attach( int1_handle );
// configure gpio b
OC_GPIO_B_RGPIO_INTS &= 0x7fffffff;
OC_GPIO_B_RGPIO_INTE = 0x80000000;
OC_GPIO_B_RGPIO_CTRL = 0x00000001;
// configure eint3
*((unsigned int *)0xE002C004) |= 0x20000000;
 
// Unmask the interrupt we just configured.
cyg_interrupt_unmask( int1_vector );
}
 
/* this is a simple program which runs in a thread */
64,7 → 140,6
void dbg_shell(cyg_addrword_t data)
{
int message = (int) data;
int delay;
 
printf("Beginning execution; thread data is %d\n", message);
78,10 → 153,12
 
for (;;) {
 
*((unsigned int *)0x83200008) ^= 0x00000001;
OC_GPIO_B_RGPIO_OUT ^= 0x00000001;
// hex_led_command( DE1_HEX_LED_INCREMENT, 0);
cyg_thread_delay(200);
cyg_thread_delay(100);
}
}
 
 
/trunk/sw/ecos/debug/oc_gpio.h
0,0 → 1,61
//
//
//
 
#ifndef __OC_GPIO_H
#define __OC_GPIO_H
 
 
// opencore gpio register offesets
#define OC_GPIO_RGPIO_IN 0x00
#define OC_GPIO_RGPIO_OUT 0x04
#define OC_GPIO_RGPIO_OE 0x08
#define OC_GPIO_RGPIO_INTE 0x0c
#define OC_GPIO_RGPIO_PTRIG 0x10
#define OC_GPIO_RGPIO_AUX 0x14
#define OC_GPIO_RGPIO_CTRL 0x18
#define OC_GPIO_RGPIO_INTS 0x1c
#define OC_GPIO_RGPIO_ECLK 0x20
#define OC_GPIO_RGPIO_NEC 0x24
 
// GPIO A
#define OC_GPIO_A_BASE 0x83100000
#define OC_GPIO_A_RGPIO_IN (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_IN) ))
#define OC_GPIO_A_RGPIO_OUT (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_OUT) ))
#define OC_GPIO_A_RGPIO_OE (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_OE) ))
#define OC_GPIO_A_RGPIO_INTE (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_INTE) ))
#define OC_GPIO_A_RGPIO_PTRIG (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_PTRIG) ))
#define OC_GPIO_A_RGPIO_AUX (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_AUX) ))
#define OC_GPIO_A_RGPIO_CTRL (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_CTRL) ))
#define OC_GPIO_A_RGPIO_INTS (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_INTS) ))
#define OC_GPIO_A_RGPIO_ECLK (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_ECLK) ))
#define OC_GPIO_A_RGPIO_NEC (*( (volatile unsigned int *) (OC_GPIO_A_BASE + OC_GPIO_RGPIO_NEC) ))
 
// GPIO B
#define OC_GPIO_B_BASE 0x83200000
#define OC_GPIO_B_RGPIO_IN (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_IN) ))
#define OC_GPIO_B_RGPIO_OUT (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_OUT) ))
#define OC_GPIO_B_RGPIO_OE (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_OE) ))
#define OC_GPIO_B_RGPIO_INTE (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_INTE) ))
#define OC_GPIO_B_RGPIO_PTRIG (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_PTRIG) ))
#define OC_GPIO_B_RGPIO_AUX (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_AUX) ))
#define OC_GPIO_B_RGPIO_CTRL (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_CTRL) ))
#define OC_GPIO_B_RGPIO_INTS (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_INTS) ))
#define OC_GPIO_B_RGPIO_ECLK (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_ECLK) ))
#define OC_GPIO_B_RGPIO_NEC (*( (volatile unsigned int *) (OC_GPIO_B_BASE + OC_GPIO_RGPIO_NEC) ))
 
 
// DE1 hex led display commands
#define DE1_HEX_LED_WRITE 1
#define DE1_HEX_LED_READ 2
#define DE1_HEX_LED_INCREMENT 3
 
 
//functions
extern void fled_init( unsigned int data);
extern void hex_led_init( unsigned int data);
extern unsigned int hex_led_command( unsigned int command, unsigned int data);
 
 
 
#endif // __OC_GPIO_H
/trunk/sw/ecos/debug/Makefile
6,10 → 6,11
 
# INSTALL_DIR=$$(INSTALL_DIR) # override on make command line
# INSTALL_DIR = ../ROM_slow/install
INSTALL_DIR = ../LPC2294_ram/LPC2294_ram_install
# INSTALL_DIR = ../LPC2294_ram/LPC2294_ram_install
INSTALL_DIR = ../LPC2294_ram/install
 
OBJECT_FILES = main.o
HEADER_FILES = lpc22xx.h lib_dbg_sh.h
OBJECT_FILES = main.o oc_gpio.o
HEADER_FILES = lpc22xx.h lib_dbg_sh.h oc_gpio.h
 
 
include $(INSTALL_DIR)/include/pkgconf/ecos.mak
/trunk/sw/ecos/ecos-3.0_diff.txt
0,0 → 1,1533
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/cdl/flash_de1_olpcx2294.cdl ./ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/cdl/flash_de1_olpcx2294.cdl
--- /opt/ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/cdl/flash_de1_olpcx2294.cdl 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/cdl/flash_de1_olpcx2294.cdl 2009-12-04 17:20:22.000000000 -0800
@@ -0,0 +1,74 @@
+# ====================================================================
+#
+# flash_olpcx2294.cdl
+#
+# FLASH memory - Hardware support on Olimex LPC-X2294 boards
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Sergei Gavrikov
+# Contributors: Sergei Gavrikov
+# Date: 2008-11-28
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_FLASH_ARM_DE1_OLPCX2294_V2 {
+ display "Support for FLASH memory parts on OLPC-X2294 boards."
+
+ compile -library=libextras.a arm_olpcx2294_flash.c
+
+ parent CYGPKG_IO_FLASH
+ active_if CYGPKG_IO_FLASH
+
+ requires (CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294 || \
+ CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294 || \
+ CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 || \
+ CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294)
+
+ requires CYGPKG_DEVS_FLASH_STRATA_V2
+
+ implements CYGHWR_IO_FLASH_BLOCK_LOCKING
+
+ description "
+ Olimex LPC-X2294 boards all have strata family 28FxxxC3 flash
+ memory parts. These parts have boot blocks. There is no buffered
+ write capability. Individual blocks can be locked and unlocked
+ in software"
+
+}
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/src/arm_olpcx2294_flash.c ./ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/src/arm_olpcx2294_flash.c
--- /opt/ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/src/arm_olpcx2294_flash.c 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/devs/flash/arm/de1_olpcx2294/v3_0/src/arm_olpcx2294_flash.c 2009-12-04 17:20:22.000000000 -0800
@@ -0,0 +1,114 @@
+//==========================================================================
+//
+// arm_olpcx2294_flash.c
+//
+// Flash programming for Intel FlashFile devices on Olimex LPC-X2294
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Sergei Gavrikov
+// Contributors: Sergei Gavrikov
+// Date: 2008-11-28
+// Purpose:
+// Description:
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/system.h>
+
+#if !defined(CYGPKG_HAL_ARM_LPC2XXX_OLPCE2294) && \
+ !defined(CYGPKG_HAL_ARM_LPC2XXX_OLPCH2294) && \
+ !defined(CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294) && \
+ !defined(CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294)
+# error Unsupported target
+#endif
+
+#ifdef CYGPKG_DEVS_FLASH_STRATA_V2
+
+#include <cyg/io/flash.h>
+#include <cyg/io/strata_dev.h>
+
+// Olimex LPC-E2294 development board and Olimex LPC-H2294 header board both
+// have 28F320C3-B flash memory part, Olimex LPC-L2294-1M development board has
+// 28F160C3-B flash memory part. All boards have 16-bit access to it's flash
+// devices.
+static const CYG_FLASH_FUNS(hal_olpcx2294_flash_strata_funs,
+ &cyg_strata_init_check_devid_16,
+ &cyg_flash_devfn_query_nop,
+ &cyg_strata_erase_16,
+ &cyg_strata_program_16,
+ (int (*)(struct cyg_flash_dev*, const cyg_flashaddr_t, void*, size_t))0,
+ &cyg_strata_lock_k3_16,
+ &cyg_strata_unlock_k3_16);
+
+static const cyg_strata_dev hal_olpcx2294_flash_priv = {
+ .manufacturer_code = CYG_FLASH_STRATA_MANUFACTURER_INTEL,
+#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
+ .device_code = 0x88c3, /* 16-Mbit x 16-B, 28F160C3-B */
+#else
+ .device_code = 0x88c5, /* 32-Mbit x 16-B, 28F320C3-B */
+#endif
+ .bufsize = 1,
+ .block_info = {
+#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
+ { 0x00002000, 8 },/* boot bottom 8 x 8K blocks */
+ { 0x00010000, 31 } /* 31 x 64K blocks */
+#else
+ { 0x00002000, 8 },/* boot bottom 8 x 8K blocks */
+ { 0x00010000, 63 } /* 63 x 64K blocks */
+#endif
+ }
+};
+
+CYG_FLASH_DRIVER(hal_olpcx2294_flash,
+ &hal_olpcx2294_flash_strata_funs,
+ 0,
+ 0x80000000,
+#ifdef CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294
+ 0x801fffff,
+#else
+ 0x803fffff,
+#endif
+ 2,
+ hal_olpcx2294_flash_priv.block_info,
+ &hal_olpcx2294_flash_priv
+);
+
+#endif//CYGPKG_DEVS_FLASH_STRATA_V2
+// ------------------------------------------------------------------------
+// EOF arm_olpcx2294_flash.c
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/ecos.db ./ecos-3.0/packages/ecos.db
--- /opt/ecos-3.0/packages/ecos.db 2009-03-27 01:58:47.000000000 -0700
+++ ./ecos-3.0/packages/ecos.db 2010-02-22 16:59:23.924394200 -0800
@@ -6690,3 +6690,60 @@
to run eCos on the STM3210E EVAL board."
}
+
+# --------------------
+#
+# --------------------
+
+
+package CYGPKG_DEVS_FLASH_ARM_DE1_OLPCX2294_V2 {
+ alias { "External Flash memory support for OLPCE2294, OLPCH2294, OLPCL2294" flash_olpcx2294_v2 }
+ directory devs/flash/arm/de1_olpcx2294
+ script flash_de1_olpcx2294.cdl
+ hardware
+ description "
+ The flash_olpcx2294_v2 provides hardware support for external
+ flash memory parts on the Olimex LPC-E2294, LPC-H2294,
+ and LPC-L2294-1M boards. It uses eCos Flash v2 API."
+}
+
+
+# package CYGPKG_IO_SERIAL_ARM_LPC2XXX {
+# alias { "ARM LPC2XXX serial device drivers"
+# devs_serial_arm_lpc2xxx lpc2xxx_serial_driver }
+# hardware
+# directory devs/serial/arm/lpc2xxx
+# script ser_arm_lpc2xxx.cdl
+# description "ARM LPC2XXX serial device drivers"
+# }
+
+
+package CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294 {
+ alias { "Olimex LPC-L2294-1MB development and Terasic DE1 boards" hal_de1_olpcl2294_arm }
+ directory hal/arm/lpc2xxx/de1_olpcl2294
+ script hal_arm_lpc2xxx_de1_olpcl2294.cdl
+ hardware
+ description "
+ The olpcl2294 HAL package provides the support needed to run
+ eCos on Olimex LPC-L2294-1MB development and Terasic DE1 boards."
+}
+
+
+target de1_olpcl2294 {
+ alias { "Olimex LPC-L2294-1MB development and Terasic DE1 boards" }
+ packages { CYGPKG_HAL_ARM
+ CYGPKG_HAL_ARM_LPC2XXX
+ CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294
+ CYGPKG_DEVS_FLASH_STRATA_V2
+ CYGPKG_DEVS_FLASH_ARM_DE1_OLPCX2294_V2
+ CYGPKG_DEVS_ETH_CL_CS8900A
+ CYGPKG_DEVS_ETH_ARM_OLPCL2294
+ CYGPKG_IO_SERIAL_GENERIC_16X5X
+ CYGPKG_IO_SERIAL_ARM_LPC2XXX
+ CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX
+ }
+ description "
+ The olpcl2294 target provides the packages needed to run
+ eCos on Olimex LPC-L2294-1MB development and Terasic DE1 boards."
+}
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/cdl/hal_arm_lpc2xxx_de1_olpcl2294.cdl ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/cdl/hal_arm_lpc2xxx_de1_olpcl2294.cdl
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/cdl/hal_arm_lpc2xxx_de1_olpcl2294.cdl 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/cdl/hal_arm_lpc2xxx_de1_olpcl2294.cdl 2009-12-04 17:20:22.000000000 -0800
@@ -0,0 +1,297 @@
+# ====================================================================
+#
+# hal_arm_lpc2xxx_de1_olpcl2294.cdl
+#
+# ARM LPC2XXX OLPCL2294 development board package configuration
+# data
+#
+# ====================================================================
+## ####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later
+## version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with eCos; if not, write to the Free Software Foundation, Inc.,
+## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+##
+## As a special exception, if other files instantiate templates or use
+## macros or inline functions from this file, or you compile this file
+## and link it with other works to produce a work based on this file,
+## this file does not by itself cause the resulting work to be covered by
+## the GNU General Public License. However the source code for this file
+## must still be made available in accordance with section (3) of the GNU
+## General Public License v2.
+##
+## This exception does not invalidate any other reasons why a work based
+## on this file might be covered by the GNU General Public License.
+## -------------------------------------------
+## ####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s): Sergei Gavrikov
+# Contributors: Sergei Gavrikov
+# Date: 2008-08-31
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+
+cdl_package CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294 {
+ display "Olimex LPC-L2294-1MB development and Terasic DE1 boards"
+ parent CYGPKG_HAL_ARM_LPC2XXX
+ define_header hal_arm_lpc2xxx_de1_olpcl2294.h
+ include_dir cyg/hal
+ hardware
+ description "
+ The OLPCL2294 HAL package provides the support needed to run
+ eCos on Olimex LPC-L2294-1MB development board."
+
+ compile de1_olpcl2294_misc.c
+
+ requires { CYGHWR_HAL_ARM_LPC2XXX == "LPC2294" }
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_lpc2xxx.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_lpc2xxx_de1_olpcl2294.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI-S\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Olimex LPC-L2294-1MB development and Terasic DE1 boards\""
+ puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value {"RAM"}
+ legal_values {"RAM" "ROM"}
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "Choose RAM or ROM startup type."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the board"
+ flavor data
+ calculated 1
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ There is one serial connector on the board."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Diagnostic serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ There is one serial connector on the board."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200 230400
+ default_value 38400
+ description "
+ This option selects the baud rate used for the diagnostic
+ port."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200 230400
+ default_value 38400
+ description "
+ This option controls the baud rate used for the GDB
+ connection."
+ }
+
+ # Real-time clock/counter specifics
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ {
+ display "CPU xtal frequency"
+ flavor data
+ default_value {14745600}
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL {
+ display "CPU PLL multiplier"
+ flavor data
+ default_value {4}
+ }
+
+ cdl_option CYGNUM_HAL_ARM_LPC2XXX_CLOCK_SPEED {
+ display "CPU clock speed"
+ flavor data
+ calculated { CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL *
+ CYGNUM_HAL_ARM_LPC2XXX_XTAL_FREQ }
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ parent CYGPKG_NONE
+ description "
+ Global build options including control over compiler flags,
+ linker flags and choice of toolchain."
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-eabi" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ default_value { CYGBLD_GLOBAL_WARNFLAGS . CYGBLD_ARCH_CFLAGS .
+ "-mcpu=arm7tdmi -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions" }
+ description "
+ This option controls the global compiler flags which
+ are used to compile all packages by default. Individual
+ packages may define options which override these global
+ flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { CYGBLD_ARCH_LDFLAGS . "-mcpu=arm7tdmi -Wl,--gc-sections -Wl,-static -g -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global
+ flags."
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" }
+ description "
+ Enable this option if this program is to be used as a
+ ROM monitor, i.e. applications will be loaded into RAM on
+ the board, and this ROM monitor may process exceptions or
+ interrupts generated from the application. This enables
+ features such as utilizing a separate interrupt stack when
+ exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM
+ monitor. This support changes various eCos semantics such
+ as the encoding of diagnostic output, or the overriding of
+ hardware interrupt vectors.
+ Firstly there is \"Generic\" support which prevents the
+ HAL from overriding the hardware vectors that it does not
+ use, to instead allow an installed ROM monitor to handle
+ them. This is the most basic support which is likely to be
+ common to most implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included
+ in the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid
+ Redboot configuration."
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ requires { !CYGBLD_BUILD_REDBOOT_WITH_EXEC }
+ default_value 1
+ no_define
+ description "
+ This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ compile -library=libextras.a redboot_cmds.c
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O ihex $< $(@:.bin=.hex)
+ $(OBJCOPY) -O binary $< $@
+ }
+
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_lpc2xxx_de1_olpcl2294_ram" :
+ "arm_lpc2xxx_de1_olpcl2294_rom" }
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { (CYG_HAL_STARTUP == "RAM") ?
+ "<pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.ldi>" :
+ "<pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { (CYG_HAL_STARTUP == "RAM") ?
+ "<pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.h>" :
+ "<pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.h>" }
+ }
+ }
+}
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/hal_platform_setup.h ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/hal_platform_setup.h
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/hal_platform_setup.h 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/hal_platform_setup.h 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,230 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+/*=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Sergei Gavrikov
+// Contributors: Sergei Gavrikov
+// Date: 2008-08-31
+// Purpose: Olimex LPC-L2294-1MB platform specific support routines
+// Description:
+// Usage: #include <cyg/hal/hal_platform_setup.h>
+//
+//####DESCRIPTIONEND####
+//
+//===========================================================================*/
+
+#include <pkgconf/system.h>
+#include <pkgconf/hal.h>
+#include <cyg/hal/var_io.h>
+
+ // There is one only diagnostic led marked STAT on the board
+ // |P1.23 330 Om LED
+ // |------\/\/\/-----|<|-----> 3.3 V
+ // |
+
+ .macro _led_init
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+ ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
+ orr r1,r1,#(1<<23)
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1DIR]
+
+ .endm // _led_init
+
+ .macro _led x
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_IO_BASE
+ ldr r1,=(1<<23)
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1SET]
+ ldr r1,=((\x & 1)<<23)
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_IO1CLR]
+
+ .endm // _led
+
+ .macro _pll_init
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
+
+ mov r2,#0xAA
+ mov r3,#0x55
+
+ // enable PLL
+ mov r1,#1
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
+
+ mov r1,#(0x20 | (CYGNUM_HAL_ARM_LPC2XXX_PLL_MUL - 1))
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCFG]
+
+ // update PLL registers
+ str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
+ str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
+
+ // wait for it to lock
+1:
+ ldr r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLSTAT]
+ ands r1,r1,#(1<<10)
+ beq 1b
+
+ // connect PLL
+ mov r1,#3
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLCON]
+
+ // update PLL registers
+ str r2,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
+ str r3,[r0,#CYGARC_HAL_LPC2XXX_REG_PLLFEED]
+
+ .endm // _pll_init
+
+ .macro _mem_init
+ // copy first 64 bytes from ROM to on-chip RAM
+ mov r0,#0
+ mov r1,#0x40000000
+ mov r2,#0x40
+1:
+ ldr r3,[r0,#4]!
+ str r3,[r1,#4]!
+ cmps r0,r2
+ bne 1b
+
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_SCB_BASE
+ mov r1,#2 // interrupt vector table is mapped to RAM
+ str r1, [r0,#CYGARC_HAL_LPC2XXX_REG_MEMMAP]
+ // flash timings
+ mov r1,#4
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMTIM]
+ mov r1,#2 // 2, full MAM
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_MAMCR]
+
+ // External memory interface depends on the bank width (32, 16 or 8 bit
+ // selected via MW bits in corresponding BCFG register). Furthermore,
+ // choice of the memory chip(s) will require an adequate setup of RBLE
+ // bit in BCFG register, too. RBLE = 0 in case of 8-bit based external
+ // memories, while memory chips capable of accepting 16 or 32 bit wide
+ // data will work with RBLE = 1.
+ //
+ // BANK0: 2M FLASH
+ // TE28F160C3BD70 (1024Kx16 x 1, 70nS)
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG0
+ ldr r1,= (0x3 << 0) /* IDCY=3, idle timing */\
+ | (0x4 << 5) /* WST1=4, read timing */\
+ | (0x1 << 10) /* RBLE=1 */\
+ | (0x6 << 11) /* WST2=6, write timing */\
+ | (0x1 << 28) /* MW=1, 16-bits */
+ str r1,[r0]
+
+ // BANK1: 1M RAM
+ // K6R4016V1D (512Kx16 x 2, 10nS)
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG1
+ // Warning: changed these timings, you can fall dramatically the eCos
+ // kernel performance. Check it then using the eCos 'tm_basic' test.
+ ldr r1,= (0x0 << 0) /* IDCY=0, idle cycles */\
+ | (0x0 << 5) /* WST1=0, read timing */\
+ | (0x1 << 10) /* RBLE=1 */\
+ | (0x0 << 11) /* WST2=0, write timing */\
+ | (0x2 << 28) /* MW=2, 32-bits */
+ str r1,[r0]
+
+ // BANK2: Ethernet
+ // CS8900A (16-bit, an interrupt driven mode)
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_BCFG2
+ ldr r1,= (0x1 << 0) /* IDCY=1, idle cycles */\
+ | (0x8 << 5) /* WST1=8, read timing */\
+ | (0x1 << 10) /* RBLE=1 */\
+ | (0x6 << 11) /* WST2=6, write timing */\
+ | (0x1 << 28) /* MW=1, 16-bits */
+ str r1,[r0]
+
+ .endm // _mem_init
+
+ .macro _gpio_init
+ ldr r0,=CYGARC_HAL_LPC2XXX_REG_PIN_BASE
+
+ // Configure P0.15:0 as PIO, but UART0, EINT2
+ ldr r1,= (0x1 << 0) /* P0.0 as TxD0 */\
+ | (0x1 << 2) /* P0.1 as RxD0 */\
+ | (0x2 << 30) /* P0.1 as EINT2(CL/IRQ)*/
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL0]
+
+ // Configure P0.30:16 as PIO, but EINT0 ('BUT' button)
+ ldr r1,= (0x1 << 0) /* P0.16 as EINT0 */
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL1]
+
+ // GPIO P1.25:16, P3.24 are used as PIO
+ ldr r1,= (0x1 << 2) /* P1.31:26 Debug port */\
+ | (0x2 << 4) /* D31:0,CS0,OE,BLS0-3 */\
+ | (0x1 << 8) /* WE enabled */\
+ | (0x1 << 11) /* CS1 enabled */\
+ | (0x1 << 14) /* CS2 enabled */\
+ | (0x1 << 23) /* A0 enabled */\
+ | (0x1 << 24) /* A1 enabled */\
+ | (0x7 << 25) /* A23:2 enabled */
+ str r1,[r0,#CYGARC_HAL_LPC2XXX_REG_PINSEL2]
+
+ .endm // _gpio_init
+
+#define CYGHWR_LED_MACRO _led \x
+
+#if defined(CYG_HAL_STARTUP_ROM)
+
+ .macro _setup
+
+ _pll_init
+
+ _mem_init
+
+ _gpio_init
+
+ _led_init
+
+ .endm
+
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+
+#else
+
+ .macro _setup
+
+ .endm
+
+#endif // CYG_HAL_STARTUP_ROM
+
+#define PLATFORM_SETUP1 _setup
+
+#endif // CYGONCE_HAL_PLATFORM_SETUP_H
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.h ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.h
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.h 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.h 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,19 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+
+#define CYGMEM_REGION_ram (0x81000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+
+#endif
+
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+
+#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.ldi ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.ldi
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.ldi 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_ram.ldi 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,25 @@
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram0 : ORIGIN = 0x40000000, LENGTH = 0x4000
+ ram : ORIGIN = 0x81000000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_fixed_vectors (ram0, 0x40000020, LMA_EQ_VMA)
+ SECTION_rom_vectors (ram, 0x81010000, LMA_EQ_VMA)
+ SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.h ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.h
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.h 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.h 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,22 @@
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+
+#define CYGMEM_REGION_rom (0x00000000)
+#define CYGMEM_REGION_rom_SIZE (0x00040000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#define CYGMEM_REGION_ram (0x81000000)
+#define CYGMEM_REGION_ram_SIZE (0x00100000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+
+#endif
+
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+
+#define CYGMEM_SECTION_heap1_SIZE (0x81100000 - (size_t) CYG_LABEL_NAME (__heap1))
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.ldi ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.ldi
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.ldi 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/pkgconf/mlt_arm_lpc2xxx_de1_olpcl2294_rom.ldi 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,26 @@
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+ ram0 : ORIGIN = 0x40000000, LENGTH = 0x4000
+ ram : ORIGIN = 0x81000000, LENGTH = 0x100000
+ rom : ORIGIN = 0x00000000, LENGTH = 0x40000
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, 0x00000000, LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram0, 0x40000020, LMA_EQ_VMA)
+ SECTION_data (ram, 0x81000000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/plf_io.h ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/plf_io.h
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/plf_io.h 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/include/plf_io.h 2009-12-04 15:45:06.000000000 -0800
@@ -0,0 +1,66 @@
+#ifndef CYGONCE_HAL_PLF_IO_H
+#define CYGONCE_HAL_PLF_IO_H
+//=============================================================================
+//
+// plf_io.h
+//
+// Olimex LPC-L2294-1MB board specific registers
+//
+//=============================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Sergei Gavrikov
+// Contributors: Sergei Gavrikov
+// Date: 2008-08-31
+// Purpose: Olimex LPC-L2294-1MB board specific registers
+// Description:
+// Usage: #include <cyg/hal/plf_io.h>
+//
+//####DESCRIPTIONEND####
+//
+//=============================================================================
+// On-chip device base addresses
+
+#ifndef __ASSEMBLER__
+extern void hal_plf_hardware_init(void);
+#define HAL_PLF_HARDWARE_INIT() \
+ hal_plf_hardware_init()
+
+#endif // __ASSEMBLER__
+
+//-----------------------------------------------------------------------------
+// end of plf_io.h
+#endif // CYGONCE_HAL_PLF_IO_H
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_RAM.ecm ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_RAM.ecm
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_RAM.ecm 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_RAM.ecm 2009-12-04 15:45:07.000000000 -0800
@@ -0,0 +1,104 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware olpcl2294 ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_STRATA_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_CL_CS8900A v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX v3_0 ;
+ package -template CYGPKG_HAL v3_0 ;
+ package -template CYGPKG_INFRA v3_0 ;
+ package -template CYGPKG_REDBOOT v3_0 ;
+ package -template CYGPKG_ISOINFRA v3_0 ;
+ package -template CYGPKG_LIBC_STRING v3_0 ;
+ package -template CYGPKG_CRC v3_0 ;
+ package CYGPKG_IO_ETH_DRIVERS v3_0 ;
+ package CYGPKG_NS_DNS v3_0 ;
+ package CYGPKG_COMPRESS_ZLIB v3_0 ;
+ package CYGPKG_IO_FLASH v3_0 ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ inferred_value 0 0
+};
+
+cdl_component CYGHWR_HAL_ARM_LPC2XXX {
+ inferred_value LPC2294
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM.ecm ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM.ecm
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM.ecm 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM.ecm 2009-12-04 17:20:22.000000000 -0800
@@ -0,0 +1,112 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware de1_olpcl2294 ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX_DE1_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_STRATA_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_ARM_DE1_OLPCX2294_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_CL_CS8900A v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX v3_0 ;
+ package -template CYGPKG_HAL v3_0 ;
+ package -template CYGPKG_INFRA v3_0 ;
+ package -template CYGPKG_REDBOOT v3_0 ;
+ package -template CYGPKG_ISOINFRA v3_0 ;
+ package -template CYGPKG_LIBC_STRING v3_0 ;
+ package -template CYGPKG_CRC v3_0 ;
+ package CYGPKG_IO_ETH_DRIVERS v3_0 ;
+ package CYGPKG_NS_DNS v3_0 ;
+ package CYGPKG_COMPRESS_ZLIB v3_0 ;
+ package CYGPKG_IO_FLASH v3_0 ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ inferred_value 0 0
+};
+
+cdl_component CYGHWR_HAL_ARM_LPC2XXX {
+ inferred_value LPC2294
+};
+
+cdl_component CYG_HAL_STARTUP {
+ inferred_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_DNS_HEADER {
+ inferred_value 1 <cyg/ns/dns/dns.h>
+};
+
+cdl_option CYGPKG_NS_DNS_BUILD {
+ inferred_value 0
+};
+
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM_minimal.ecm ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM_minimal.ecm
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM_minimal.ecm 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/misc/redboot_ROM_minimal.ecm 2009-12-04 15:45:07.000000000 -0800
@@ -0,0 +1,100 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware olpcl2294 ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_HAL_ARM_LPC2XXX_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_STRATA_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_FLASH_ARM_OLPCX2294_V2 v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_CL_CS8900A v3_0 ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_OLPCL2294 v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v3_0 ;
+ package -hardware CYGPKG_IO_SERIAL_ARM_LPC2XXX v3_0 ;
+ package -hardware CYGPKG_DEVICES_WATCHDOG_ARM_LPC2XXX v3_0 ;
+ package -template CYGPKG_HAL v3_0 ;
+ package -template CYGPKG_INFRA v3_0 ;
+ package -template CYGPKG_REDBOOT v3_0 ;
+ package -template CYGPKG_ISOINFRA v3_0 ;
+ package -template CYGPKG_LIBC_STRING v3_0 ;
+ package -template CYGPKG_CRC v3_0 ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ inferred_value 0 0
+};
+
+cdl_component CYGHWR_HAL_ARM_LPC2XXX {
+ inferred_value LPC2294
+};
+
+cdl_component CYG_HAL_STARTUP {
+ inferred_value ROM
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
+ inferred_value 0
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/de1_olpcl2294_misc.c ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/de1_olpcl2294_misc.c
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/de1_olpcl2294_misc.c 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/de1_olpcl2294_misc.c 2009-12-04 15:45:07.000000000 -0800
@@ -0,0 +1,109 @@
+//==========================================================================
+//
+// olpcl2294_misc.c
+//
+// HAL misc board support code for Olimex LPC-L2294-1MB development
+// board
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Sergei Gavrikov
+// Contributors: Sergei Gavrikov
+// Date: 2008-08-31
+// Purpose: HAL board support
+// Description: Implementations of HAL board interfaces
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/hal/var_io.h>
+
+#include <cyg/hal/hal_var_ints.h>
+#include <cyg/hal/drv_api.h>
+
+extern void cyg_hal_plf_serial_init (void);
+
+//--------------------------------------------------------------------------
+// hal_lpc2xxx_set_leds --
+//
+// There is one diagnostic LED marked 'STAT' on the board
+//
+void
+hal_lpc2xxx_set_leds (int mask)
+{
+ HAL_WRITE_UINT32 (CYGARC_HAL_LPC2XXX_REG_IO_BASE +
+ CYGARC_HAL_LPC2XXX_REG_IO1SET, (1 << 23));
+ if (mask & 1)
+ HAL_WRITE_UINT32 (CYGARC_HAL_LPC2XXX_REG_IO_BASE +
+ CYGARC_HAL_LPC2XXX_REG_IO1CLR, (1 << 23));
+}
+
+//--------------------------------------------------------------------------
+// cyg_hal_plf_comms_init --
+//
+void
+cyg_hal_plf_comms_init (void)
+{
+ static int initialized = 0;
+
+ if (initialized)
+ return;
+ initialized = 1;
+
+ cyg_hal_plf_serial_init ();
+}
+
+#ifdef HAL_PLF_HARDWARE_INIT
+//--------------------------------------------------------------------------
+// hal_plf_hardware_init --
+//
+void
+hal_plf_hardware_init (void)
+{
+ // configure IRQ level from CL CS8900A
+ cyg_drv_interrupt_configure (CYGNUM_HAL_INTERRUPT_EINT2, 0, 1);
+}
+#endif // HAL_PLF_HARDWARE_INIT
+
+// indent: --indent-level4 -br -nut; vim: expandtab tabstop=4 shiftwidth=4
+//--------------------------------------------------------------------------
+// EOF olpcl2294_misc.c
diff -NaurbBw --exclude-from=diff_exclude.txt /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/redboot_cmds.c ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/redboot_cmds.c
--- /opt/ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/redboot_cmds.c 1969-12-31 16:00:00.000000000 -0800
+++ ./ecos-3.0/packages/hal/arm/lpc2xxx/de1_olpcl2294/v3_0/src/redboot_cmds.c 2009-12-04 15:45:07.000000000 -0800
@@ -0,0 +1,115 @@
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// OLPCL2294 [platform] specific RedBoot commands
+//
+//==========================================================================
+// ####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2008 Free Software Foundation, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later
+// version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
+// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+//
+// As a special exception, if other files instantiate templates or use
+// macros or inline functions from this file, or you compile this file
+// and link it with other works to produce a work based on this file,
+// this file does not by itself cause the resulting work to be covered by
+// the GNU General Public License. However the source code for this file
+// must still be made available in accordance with section (3) of the GNU
+// General Public License v2.
+//
+// This exception does not invalidate any other reasons why a work based
+// on this file might be covered by the GNU General Public License.
+// -------------------------------------------
+// ####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s): Sergei Gavrikov
+// Contributors: Sergei Gavrikov
+// Date: 2008-08-31
+// Purpose:
+// Description:
+//
+// This code is part of RedBoot (tm).
+//
+//####DESCRIPTIONEND####
+//
+//========================================================================*/
+
+#include <cyg/hal/hal_diag.h>
+#include <redboot.h>
+
+// CLI functions
+static void do_echo (int argc, char *argv[]);
+RedBoot_cmd ("echo",
+ "Outputs the args. If -n is specified, the trailing newline is suppressed.",
+ "-n [arg ...]", do_echo);
+
+static void do_led (int argc, char *argv[]);
+RedBoot_cmd ("led", "Manage diagnostic led(s)", "[-m mask]", do_led);
+
+//--------------------------------------------------------------------------
+// do_echo --
+//
+static void
+do_echo (int argc, char *argv[])
+{
+ bool newline = true;
+ if (argc > 1) {
+ int i = 1;
+ if (strncmp (&argv[i][0], "-n", 2) == 0) {
+ newline = false;
+ i++;
+ }
+ for (; i < argc; i++) {
+ diag_write_string (&argv[i][0]);
+ if ((argc - i) > 1)
+ diag_write_char (' ');
+ }
+ }
+ if (newline)
+ diag_write_char ('\n');
+ return;
+}
+
+//--------------------------------------------------------------------------
+// do_led --
+//
+static void
+do_led (int argc, char *argv[])
+{
+ struct option_info opts[1];
+ unsigned long mask;
+ bool mask_set;
+
+ init_opts (&opts[0], 'm', true, OPTION_ARG_TYPE_NUM,
+ &mask, &mask_set, "mask");
+ if (!scan_opts (argc, argv, 1, opts, 1, 0, 0, "")) {
+ return;
+ }
+ if (!mask_set) {
+ diag_printf ("led what <mask>?\n");
+ return;
+ }
+ hal_lpc2xxx_set_leds (mask);
+ return;
+}
+
+// indent: --indent-level4 -br -nut; vim: expandtab tabstop=4 shiftwidth=4
+//--------------------------------------------------------------------------
+// EOF redboot_cmds.c
/trunk/syn/debug/top.qsf
28,7 → 28,7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:25:28 APRIL 24, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 9.0
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
491,7 → 491,6
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
 
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
514,8 → 513,10
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_clk_i" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_GAP_RECORD=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_MODE=TRANSITIONAL" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
set_global_assignment -name VERILOG_FILE ../../src/qaz_system.v
set_global_assignment -name VERILOG_FILE ../../src/hex_led_encoder.v
set_global_assignment -name VERILOG_FILE ../../src/top.v
set_global_assignment -name VERILOG_FILE ../../../gpio/rtl/verilog/gpio_top.v
set_global_assignment -name VERILOG_FILE ../../../wb_size_bridge/src/async_mem_if.v
533,1169 → 534,744
set_global_assignment -name VERILOG_FILE ../../../wb_conmax/rtl/verilog/wb_conmax_rf.v
set_global_assignment -name VERILOG_FILE ../../../wb_conmax/rtl/verilog/wb_conmax_slave_if.v
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "gpio_top:i_gpio_a|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "gpio_top:i_gpio_a|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "gpio_top:i_gpio_a|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "gpio_top:i_gpio_a|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "gpio_top:i_gpio_a|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "gpio_top:i_gpio_a|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "gpio_top:i_gpio_a|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "gpio_top:i_gpio_a|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "gpio_top:i_gpio_a|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "gpio_top:i_gpio_a|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "gpio_top:i_gpio_a|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "gpio_top:i_gpio_a|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "gpio_top:i_gpio_a|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "gpio_top:i_gpio_a|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "gpio_top:i_gpio_a|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "gpio_top:i_gpio_a|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "gpio_top:i_gpio_a|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "gpio_top:i_gpio_a|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "gpio_top:i_gpio_a|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "gpio_top:i_gpio_a|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "gpio_top:i_gpio_a|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "gpio_top:i_gpio_a|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "gpio_top:i_gpio_a|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "gpio_top:i_gpio_a|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "gpio_top:i_gpio_a|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "gpio_top:i_gpio_a|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "gpio_top:i_gpio_a|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "gpio_top:i_gpio_a|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "gpio_top:i_gpio_a|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "gpio_top:i_gpio_a|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "gpio_top:i_gpio_a|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "gpio_top:i_gpio_a|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "gpio_top:i_gpio_a|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "gpio_top:i_gpio_a|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "gpio_top:i_gpio_a|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "gpio_top:i_gpio_a|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "gpio_top:i_gpio_a|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "gpio_top:i_gpio_a|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "gpio_top:i_gpio_a|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "gpio_top:i_gpio_a|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "gpio_top:i_gpio_a|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "gpio_top:i_gpio_a|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "gpio_top:i_gpio_a|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "gpio_top:i_gpio_a|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "gpio_top:i_gpio_a|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "gpio_top:i_gpio_a|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "gpio_top:i_gpio_a|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "gpio_top:i_gpio_a|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "gpio_top:i_gpio_a|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "gpio_top:i_gpio_a|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "gpio_top:i_gpio_a|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "gpio_top:i_gpio_a|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "gpio_top:i_gpio_a|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "gpio_top:i_gpio_a|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "gpio_top:i_gpio_a|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "gpio_top:i_gpio_a|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "gpio_top:i_gpio_a|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "gpio_top:i_gpio_a|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "gpio_top:i_gpio_a|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "gpio_top:i_gpio_a|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "gpio_top:i_gpio_a|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "gpio_top:i_gpio_a|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "gpio_top:i_gpio_a|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "gpio_top:i_gpio_a|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "gpio_top:i_gpio_a|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "gpio_top:i_gpio_a|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "gpio_top:i_gpio_a|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "gpio_top:i_gpio_a|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "gpio_top:i_gpio_a|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "gpio_top:i_gpio_a|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "gpio_top:i_gpio_a|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "gpio_top:i_gpio_a|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "gpio_top:i_gpio_a|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "gpio_top:i_gpio_a|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "gpio_top:i_gpio_a|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "gpio_top:i_gpio_a|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "gpio_top:i_gpio_a|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "gpio_top:i_gpio_a|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "gpio_top:i_gpio_a|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "gpio_top:i_gpio_a|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "gpio_top:i_gpio_a|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "gpio_top:i_gpio_a|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "gpio_top:i_gpio_b|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "gpio_top:i_gpio_b|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "gpio_top:i_gpio_b|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "gpio_top:i_gpio_b|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "gpio_top:i_gpio_b|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "gpio_top:i_gpio_b|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "gpio_top:i_gpio_b|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "gpio_top:i_gpio_b|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "gpio_top:i_gpio_b|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "gpio_top:i_gpio_b|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "gpio_top:i_gpio_b|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "gpio_top:i_gpio_b|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "gpio_top:i_gpio_b|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "gpio_top:i_gpio_b|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "gpio_top:i_gpio_b|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "gpio_top:i_gpio_b|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "gpio_top:i_gpio_b|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "gpio_top:i_gpio_b|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "gpio_top:i_gpio_b|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "gpio_top:i_gpio_b|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "gpio_top:i_gpio_b|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "gpio_top:i_gpio_b|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "gpio_top:i_gpio_b|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "gpio_top:i_gpio_b|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "gpio_top:i_gpio_b|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "gpio_top:i_gpio_b|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "gpio_top:i_gpio_b|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "gpio_top:i_gpio_b|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "gpio_top:i_gpio_b|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "gpio_top:i_gpio_b|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "gpio_top:i_gpio_b|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "gpio_top:i_gpio_b|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "gpio_top:i_gpio_b|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "gpio_top:i_gpio_b|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "gpio_top:i_gpio_b|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "gpio_top:i_gpio_b|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "gpio_top:i_gpio_b|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "gpio_top:i_gpio_b|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "gpio_top:i_gpio_b|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "gpio_top:i_gpio_b|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "gpio_top:i_gpio_b|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "gpio_top:i_gpio_b|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "gpio_top:i_gpio_b|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "gpio_top:i_gpio_b|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "gpio_top:i_gpio_b|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "gpio_top:i_gpio_b|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "gpio_top:i_gpio_b|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "gpio_top:i_gpio_b|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "gpio_top:i_gpio_b|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "gpio_top:i_gpio_b|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "gpio_top:i_gpio_b|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "gpio_top:i_gpio_b|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "gpio_top:i_gpio_b|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "gpio_top:i_gpio_b|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "gpio_top:i_gpio_b|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "gpio_top:i_gpio_b|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "gpio_top:i_gpio_b|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "gpio_top:i_gpio_b|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "gpio_top:i_gpio_b|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "gpio_top:i_gpio_b|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "gpio_top:i_gpio_b|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "gpio_top:i_gpio_b|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "gpio_top:i_gpio_b|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "gpio_top:i_gpio_b|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "gpio_top:i_gpio_b|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "gpio_top:i_gpio_b|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "gpio_top:i_gpio_b|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "gpio_top:i_gpio_b|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "gpio_top:i_gpio_b|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "gpio_top:i_gpio_b|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "gpio_top:i_gpio_b|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "gpio_top:i_gpio_b|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "gpio_top:i_gpio_b|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "gpio_top:i_gpio_b|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "gpio_top:i_gpio_b|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "gpio_top:i_gpio_b|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "gpio_top:i_gpio_b|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "gpio_top:i_gpio_b|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "gpio_top:i_gpio_b|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "gpio_top:i_gpio_b|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "gpio_top:i_gpio_b|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to hex0[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to hex0[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to hex0[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to hex0[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to hex0[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to hex0[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to hex0[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to hex1[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to hex1[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to hex1[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to hex1[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to hex1[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to hex1[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to hex1[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to hex2[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to hex2[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to hex2[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to hex2[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to hex2[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to hex2[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to hex2[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to hex3[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to hex3[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to hex3[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to hex3[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to hex3[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to hex3[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to hex3[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[265] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[266] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[267] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[268] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[269] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[270] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[271] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[272] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[273] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[274] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[275] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[276] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[277] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[278] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[279] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[280] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[281] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[282] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[283] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[284] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[285] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[286] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[287] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[288] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[289] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[290] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[291] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[292] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[293] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[294] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[295] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[296] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[297] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[298] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[299] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[300] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[301] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[302] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[303] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[304] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[305] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[306] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[307] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[308] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[309] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[310] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[311] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[312] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[313] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[314] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[315] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[316] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[317] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[318] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[319] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[320] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[321] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[322] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[323] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[324] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[325] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[326] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[327] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[328] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[329] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[330] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[331] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[332] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[333] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[334] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[335] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[336] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[337] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[338] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[339] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[340] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[341] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[342] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[343] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[344] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[345] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[346] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[347] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[348] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[349] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[350] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[351] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[352] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[353] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[354] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[355] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[356] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[357] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[358] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[359] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[360] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[361] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[362] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[363] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[364] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[365] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[366] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[367] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[368] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[369] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[370] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[371] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[372] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[373] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[374] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[375] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[376] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[377] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[378] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[379] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[380] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[381] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[382] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[383] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[384] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[385] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "gpio_top:i_gpio_a|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "gpio_top:i_gpio_a|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "gpio_top:i_gpio_a|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "gpio_top:i_gpio_a|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "gpio_top:i_gpio_a|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "gpio_top:i_gpio_a|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "gpio_top:i_gpio_a|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "gpio_top:i_gpio_a|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "gpio_top:i_gpio_a|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "gpio_top:i_gpio_a|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "gpio_top:i_gpio_a|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "gpio_top:i_gpio_a|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "gpio_top:i_gpio_a|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "gpio_top:i_gpio_a|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "gpio_top:i_gpio_a|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "gpio_top:i_gpio_a|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "gpio_top:i_gpio_a|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "gpio_top:i_gpio_a|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "gpio_top:i_gpio_a|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "gpio_top:i_gpio_a|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "gpio_top:i_gpio_a|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "gpio_top:i_gpio_a|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "gpio_top:i_gpio_a|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "gpio_top:i_gpio_a|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "gpio_top:i_gpio_a|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "gpio_top:i_gpio_a|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "gpio_top:i_gpio_a|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "gpio_top:i_gpio_a|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "gpio_top:i_gpio_a|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "gpio_top:i_gpio_a|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "gpio_top:i_gpio_a|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "gpio_top:i_gpio_a|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "gpio_top:i_gpio_a|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "gpio_top:i_gpio_a|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "gpio_top:i_gpio_a|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "gpio_top:i_gpio_a|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "gpio_top:i_gpio_a|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "gpio_top:i_gpio_a|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "gpio_top:i_gpio_a|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "gpio_top:i_gpio_a|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "gpio_top:i_gpio_a|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "gpio_top:i_gpio_a|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "gpio_top:i_gpio_a|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "gpio_top:i_gpio_a|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "gpio_top:i_gpio_a|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "gpio_top:i_gpio_a|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "gpio_top:i_gpio_a|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "gpio_top:i_gpio_a|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "gpio_top:i_gpio_a|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "gpio_top:i_gpio_a|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "gpio_top:i_gpio_a|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "gpio_top:i_gpio_a|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "gpio_top:i_gpio_a|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "gpio_top:i_gpio_a|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "gpio_top:i_gpio_a|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "gpio_top:i_gpio_a|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "gpio_top:i_gpio_a|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "gpio_top:i_gpio_a|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "gpio_top:i_gpio_a|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "gpio_top:i_gpio_a|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "gpio_top:i_gpio_a|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "gpio_top:i_gpio_a|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "gpio_top:i_gpio_a|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "gpio_top:i_gpio_a|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "gpio_top:i_gpio_a|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "gpio_top:i_gpio_a|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "gpio_top:i_gpio_a|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "gpio_top:i_gpio_a|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "gpio_top:i_gpio_a|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "gpio_top:i_gpio_a|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "gpio_top:i_gpio_a|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "gpio_top:i_gpio_a|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "gpio_top:i_gpio_a|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "gpio_top:i_gpio_a|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "gpio_top:i_gpio_a|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "gpio_top:i_gpio_a|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "gpio_top:i_gpio_a|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "gpio_top:i_gpio_a|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "gpio_top:i_gpio_a|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "gpio_top:i_gpio_a|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "gpio_top:i_gpio_a|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "gpio_top:i_gpio_a|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "gpio_top:i_gpio_b|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "gpio_top:i_gpio_b|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "gpio_top:i_gpio_b|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "gpio_top:i_gpio_b|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "gpio_top:i_gpio_b|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "gpio_top:i_gpio_b|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "gpio_top:i_gpio_b|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "gpio_top:i_gpio_b|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "gpio_top:i_gpio_b|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "gpio_top:i_gpio_b|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "gpio_top:i_gpio_b|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "gpio_top:i_gpio_b|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "gpio_top:i_gpio_b|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "gpio_top:i_gpio_b|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "gpio_top:i_gpio_b|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "gpio_top:i_gpio_b|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "gpio_top:i_gpio_b|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "gpio_top:i_gpio_b|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "gpio_top:i_gpio_b|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "gpio_top:i_gpio_b|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "gpio_top:i_gpio_b|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "gpio_top:i_gpio_b|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "gpio_top:i_gpio_b|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "gpio_top:i_gpio_b|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "gpio_top:i_gpio_b|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "gpio_top:i_gpio_b|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "gpio_top:i_gpio_b|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "gpio_top:i_gpio_b|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "gpio_top:i_gpio_b|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "gpio_top:i_gpio_b|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "gpio_top:i_gpio_b|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "gpio_top:i_gpio_b|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "gpio_top:i_gpio_b|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "gpio_top:i_gpio_b|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "gpio_top:i_gpio_b|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "gpio_top:i_gpio_b|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "gpio_top:i_gpio_b|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "gpio_top:i_gpio_b|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "gpio_top:i_gpio_b|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "gpio_top:i_gpio_b|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "gpio_top:i_gpio_b|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "gpio_top:i_gpio_b|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "gpio_top:i_gpio_b|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "gpio_top:i_gpio_b|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "gpio_top:i_gpio_b|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "gpio_top:i_gpio_b|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "gpio_top:i_gpio_b|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "gpio_top:i_gpio_b|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "gpio_top:i_gpio_b|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "gpio_top:i_gpio_b|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "gpio_top:i_gpio_b|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "gpio_top:i_gpio_b|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "gpio_top:i_gpio_b|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "gpio_top:i_gpio_b|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "gpio_top:i_gpio_b|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "gpio_top:i_gpio_b|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "gpio_top:i_gpio_b|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "gpio_top:i_gpio_b|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "gpio_top:i_gpio_b|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "gpio_top:i_gpio_b|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "gpio_top:i_gpio_b|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "gpio_top:i_gpio_b|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "gpio_top:i_gpio_b|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "gpio_top:i_gpio_b|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "gpio_top:i_gpio_b|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "gpio_top:i_gpio_b|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "gpio_top:i_gpio_b|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "gpio_top:i_gpio_b|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "gpio_top:i_gpio_b|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "gpio_top:i_gpio_b|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "gpio_top:i_gpio_b|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "gpio_top:i_gpio_b|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "gpio_top:i_gpio_b|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "gpio_top:i_gpio_b|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "gpio_top:i_gpio_b|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "gpio_top:i_gpio_b|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "gpio_top:i_gpio_b|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "gpio_top:i_gpio_b|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "gpio_top:i_gpio_b|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "gpio_top:i_gpio_b|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "gpio_top:i_gpio_b|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to hex0[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to hex0[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to hex0[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to hex0[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to hex0[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to hex0[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to hex0[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to hex1[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to hex1[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to hex1[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to hex1[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to hex1[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to hex1[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to hex1[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to hex2[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to hex2[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to hex2[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to hex2[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to hex2[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to hex2[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to hex2[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to hex3[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to hex3[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to hex3[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to hex3[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to hex3[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to hex3[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to hex3[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[265] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[266] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[267] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[268] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[269] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[270] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[271] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[272] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[273] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[274] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[275] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[276] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[277] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[278] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[279] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[280] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[281] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[282] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[283] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[284] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[285] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[286] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[287] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[288] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[289] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[290] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[291] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[292] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[293] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[294] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[295] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[296] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[297] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[298] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[299] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[300] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[301] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[302] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[303] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[304] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[305] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[306] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[307] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[308] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[309] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[310] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[311] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[312] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[313] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[314] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[315] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[316] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[317] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[318] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[319] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[320] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[321] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[322] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[323] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[324] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[325] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[326] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[327] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[328] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[329] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[330] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[331] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[332] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[333] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[334] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[335] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[336] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[337] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[338] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[339] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[340] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[341] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[342] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[343] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[344] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[345] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[346] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[347] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[348] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[349] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[350] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[351] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[352] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[353] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[354] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[355] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[356] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[357] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[358] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[359] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[360] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[361] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[362] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[363] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[364] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[365] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[366] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[367] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[368] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[369] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[370] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[371] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[372] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[373] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[374] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[375] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[376] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[377] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[378] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[379] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[380] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[381] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[382] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[383] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[384] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[385] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to "gpio_top:i_gpio_a|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to "gpio_top:i_gpio_a|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to "gpio_top:i_gpio_a|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to "gpio_top:i_gpio_a|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to "gpio_top:i_gpio_a|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to "gpio_top:i_gpio_a|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[6] -to "gpio_top:i_gpio_a|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[7] -to "gpio_top:i_gpio_a|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[8] -to "gpio_top:i_gpio_a|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[9] -to "gpio_top:i_gpio_a|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[10] -to "gpio_top:i_gpio_a|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[11] -to "gpio_top:i_gpio_a|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[12] -to "gpio_top:i_gpio_a|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[13] -to "gpio_top:i_gpio_a|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[14] -to "gpio_top:i_gpio_a|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[15] -to "gpio_top:i_gpio_a|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[16] -to "gpio_top:i_gpio_a|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[17] -to "gpio_top:i_gpio_a|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[18] -to "gpio_top:i_gpio_a|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[19] -to "gpio_top:i_gpio_a|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[20] -to "gpio_top:i_gpio_a|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[21] -to "gpio_top:i_gpio_a|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[22] -to "gpio_top:i_gpio_a|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[23] -to "gpio_top:i_gpio_a|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[24] -to "gpio_top:i_gpio_a|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[25] -to "gpio_top:i_gpio_a|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[26] -to "gpio_top:i_gpio_a|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[27] -to "gpio_top:i_gpio_a|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[28] -to "gpio_top:i_gpio_a|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[29] -to "gpio_top:i_gpio_a|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[30] -to "gpio_top:i_gpio_a|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[31] -to "gpio_top:i_gpio_a|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[32] -to "gpio_top:i_gpio_a|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[33] -to "gpio_top:i_gpio_a|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[34] -to "gpio_top:i_gpio_a|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[35] -to "gpio_top:i_gpio_a|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[36] -to "gpio_top:i_gpio_a|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[37] -to "gpio_top:i_gpio_a|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[38] -to "gpio_top:i_gpio_a|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[39] -to "gpio_top:i_gpio_a|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[40] -to "gpio_top:i_gpio_a|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[41] -to "gpio_top:i_gpio_a|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[42] -to "gpio_top:i_gpio_a|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[43] -to "gpio_top:i_gpio_a|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[44] -to "gpio_top:i_gpio_a|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[45] -to "gpio_top:i_gpio_a|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[46] -to "gpio_top:i_gpio_a|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[47] -to "gpio_top:i_gpio_a|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[48] -to "gpio_top:i_gpio_a|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[49] -to "gpio_top:i_gpio_a|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[50] -to "gpio_top:i_gpio_a|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[51] -to "gpio_top:i_gpio_a|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[52] -to "gpio_top:i_gpio_a|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[53] -to "gpio_top:i_gpio_a|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[54] -to "gpio_top:i_gpio_a|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[55] -to "gpio_top:i_gpio_a|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[56] -to "gpio_top:i_gpio_a|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[57] -to "gpio_top:i_gpio_a|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[58] -to "gpio_top:i_gpio_a|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[59] -to "gpio_top:i_gpio_a|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[60] -to "gpio_top:i_gpio_a|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[61] -to "gpio_top:i_gpio_a|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[62] -to "gpio_top:i_gpio_a|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[63] -to "gpio_top:i_gpio_a|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[64] -to "gpio_top:i_gpio_a|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[65] -to "gpio_top:i_gpio_a|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[66] -to "gpio_top:i_gpio_a|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[67] -to "gpio_top:i_gpio_a|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[68] -to "gpio_top:i_gpio_a|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[69] -to "gpio_top:i_gpio_a|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[70] -to "gpio_top:i_gpio_a|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[71] -to "gpio_top:i_gpio_a|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[72] -to "gpio_top:i_gpio_a|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[73] -to "gpio_top:i_gpio_a|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[74] -to "gpio_top:i_gpio_a|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[75] -to "gpio_top:i_gpio_a|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[76] -to "gpio_top:i_gpio_a|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[77] -to "gpio_top:i_gpio_a|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[78] -to "gpio_top:i_gpio_a|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[79] -to "gpio_top:i_gpio_a|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[80] -to "gpio_top:i_gpio_a|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[81] -to "gpio_top:i_gpio_a|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[82] -to "gpio_top:i_gpio_b|wb_ack_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[83] -to "gpio_top:i_gpio_b|wb_adr_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[84] -to "gpio_top:i_gpio_b|wb_adr_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[85] -to "gpio_top:i_gpio_b|wb_adr_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[86] -to "gpio_top:i_gpio_b|wb_adr_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[87] -to "gpio_top:i_gpio_b|wb_adr_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[88] -to "gpio_top:i_gpio_b|wb_adr_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[89] -to "gpio_top:i_gpio_b|wb_adr_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[90] -to "gpio_top:i_gpio_b|wb_adr_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[91] -to "gpio_top:i_gpio_b|wb_cyc_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[92] -to "gpio_top:i_gpio_b|wb_dat_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[93] -to "gpio_top:i_gpio_b|wb_dat_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[94] -to "gpio_top:i_gpio_b|wb_dat_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[95] -to "gpio_top:i_gpio_b|wb_dat_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[96] -to "gpio_top:i_gpio_b|wb_dat_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[97] -to "gpio_top:i_gpio_b|wb_dat_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[98] -to "gpio_top:i_gpio_b|wb_dat_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[99] -to "gpio_top:i_gpio_b|wb_dat_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[100] -to "gpio_top:i_gpio_b|wb_dat_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[101] -to "gpio_top:i_gpio_b|wb_dat_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[102] -to "gpio_top:i_gpio_b|wb_dat_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[103] -to "gpio_top:i_gpio_b|wb_dat_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[104] -to "gpio_top:i_gpio_b|wb_dat_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[105] -to "gpio_top:i_gpio_b|wb_dat_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[106] -to "gpio_top:i_gpio_b|wb_dat_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[107] -to "gpio_top:i_gpio_b|wb_dat_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[108] -to "gpio_top:i_gpio_b|wb_dat_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[109] -to "gpio_top:i_gpio_b|wb_dat_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[110] -to "gpio_top:i_gpio_b|wb_dat_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[111] -to "gpio_top:i_gpio_b|wb_dat_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[112] -to "gpio_top:i_gpio_b|wb_dat_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[113] -to "gpio_top:i_gpio_b|wb_dat_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[114] -to "gpio_top:i_gpio_b|wb_dat_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[115] -to "gpio_top:i_gpio_b|wb_dat_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[116] -to "gpio_top:i_gpio_b|wb_dat_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[117] -to "gpio_top:i_gpio_b|wb_dat_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[118] -to "gpio_top:i_gpio_b|wb_dat_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[119] -to "gpio_top:i_gpio_b|wb_dat_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[120] -to "gpio_top:i_gpio_b|wb_dat_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[121] -to "gpio_top:i_gpio_b|wb_dat_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[122] -to "gpio_top:i_gpio_b|wb_dat_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[123] -to "gpio_top:i_gpio_b|wb_dat_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[124] -to "gpio_top:i_gpio_b|wb_dat_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[125] -to "gpio_top:i_gpio_b|wb_dat_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[126] -to "gpio_top:i_gpio_b|wb_dat_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[127] -to "gpio_top:i_gpio_b|wb_dat_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[128] -to "gpio_top:i_gpio_b|wb_dat_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[129] -to "gpio_top:i_gpio_b|wb_dat_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[130] -to "gpio_top:i_gpio_b|wb_dat_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[131] -to "gpio_top:i_gpio_b|wb_dat_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[132] -to "gpio_top:i_gpio_b|wb_dat_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[133] -to "gpio_top:i_gpio_b|wb_dat_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[134] -to "gpio_top:i_gpio_b|wb_dat_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[135] -to "gpio_top:i_gpio_b|wb_dat_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[136] -to "gpio_top:i_gpio_b|wb_dat_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[137] -to "gpio_top:i_gpio_b|wb_dat_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[138] -to "gpio_top:i_gpio_b|wb_dat_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[139] -to "gpio_top:i_gpio_b|wb_dat_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[140] -to "gpio_top:i_gpio_b|wb_dat_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[141] -to "gpio_top:i_gpio_b|wb_dat_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[142] -to "gpio_top:i_gpio_b|wb_dat_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[143] -to "gpio_top:i_gpio_b|wb_dat_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[144] -to "gpio_top:i_gpio_b|wb_dat_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[145] -to "gpio_top:i_gpio_b|wb_dat_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[146] -to "gpio_top:i_gpio_b|wb_dat_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[147] -to "gpio_top:i_gpio_b|wb_dat_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[148] -to "gpio_top:i_gpio_b|wb_dat_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[149] -to "gpio_top:i_gpio_b|wb_dat_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[150] -to "gpio_top:i_gpio_b|wb_dat_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[151] -to "gpio_top:i_gpio_b|wb_dat_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[152] -to "gpio_top:i_gpio_b|wb_dat_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[153] -to "gpio_top:i_gpio_b|wb_dat_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[154] -to "gpio_top:i_gpio_b|wb_dat_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[155] -to "gpio_top:i_gpio_b|wb_dat_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[156] -to "gpio_top:i_gpio_b|wb_err_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[157] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[158] -to "gpio_top:i_gpio_b|wb_sel_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[159] -to "gpio_top:i_gpio_b|wb_sel_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[160] -to "gpio_top:i_gpio_b|wb_sel_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[161] -to "gpio_top:i_gpio_b|wb_sel_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[162] -to "gpio_top:i_gpio_b|wb_stb_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[163] -to "gpio_top:i_gpio_b|wb_we_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[164] -to hex0[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[165] -to hex0[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[166] -to hex0[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[167] -to hex0[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[168] -to hex0[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[169] -to hex0[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[170] -to hex0[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[171] -to hex1[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[172] -to hex1[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[173] -to hex1[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[174] -to hex1[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[175] -to hex1[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[176] -to hex1[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[177] -to hex1[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[178] -to hex2[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[179] -to hex2[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[180] -to hex2[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[181] -to hex2[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[182] -to hex2[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[183] -to hex2[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[184] -to hex2[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[185] -to hex3[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[186] -to hex3[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[187] -to hex3[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[188] -to hex3[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[189] -to hex3[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[190] -to hex3[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[191] -to hex3[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[244] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[245] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[246] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[247] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[248] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[249] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[250] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[251] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[252] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[253] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[254] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[255] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[256] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[257] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[258] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[259] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[260] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[261] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[262] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[263] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[264] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[265] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[266] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[267] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[268] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[269] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[270] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[271] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[272] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[273] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[274] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[275] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[276] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[277] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[278] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[279] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[280] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[281] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[282] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[283] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[284] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[285] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[286] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[287] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[288] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[289] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[290] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[291] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[292] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[293] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[294] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[295] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[296] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[297] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[298] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[299] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[300] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[301] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[302] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[303] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[304] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[305] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[306] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[307] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[308] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[309] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[310] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[311] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[312] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[313] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[314] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[315] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[316] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[317] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[318] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[319] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[320] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[321] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[322] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[323] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[324] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[325] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[326] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[327] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[328] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[329] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[330] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[331] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[332] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[333] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[334] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[335] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[336] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[337] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[338] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[339] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[340] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[341] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[342] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[343] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[344] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[345] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[346] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[347] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[348] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[349] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[350] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[351] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[352] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[353] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[354] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[355] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[356] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[357] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[358] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[359] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[360] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[361] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[362] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[363] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[364] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[365] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[366] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[367] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[368] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[369] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[370] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[371] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[372] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[373] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[374] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[375] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[376] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[377] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[378] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[379] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[380] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[381] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[382] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[383] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[384] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[385] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=386" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=386" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=386" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=2725" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=387" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=57472" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=56037" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to gpio_0[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to gpio_0[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to gpio_0[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to gpio_0[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to gpio_1[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to gpio_1[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to gpio_1[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to gpio_1[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to gpio_0[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to gpio_0[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to gpio_0[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to gpio_0[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to gpio_1[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to gpio_1[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to gpio_1[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to gpio_1[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to gpio_0[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to gpio_0[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to gpio_0[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to gpio_0[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to gpio_1[32] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to gpio_1[33] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[6] -to gpio_1[34] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[7] -to gpio_1[35] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "gpio_top:i_gpio_b|ext_pad_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "gpio_top:i_gpio_b|ext_pad_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "gpio_top:i_gpio_b|ext_pad_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "gpio_top:i_gpio_b|ext_pad_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "gpio_top:i_gpio_b|ext_pad_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "gpio_top:i_gpio_b|ext_pad_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "gpio_top:i_gpio_b|ext_pad_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "gpio_top:i_gpio_b|ext_pad_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[8] -to "gpio_top:i_gpio_b|ext_pad_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[9] -to "gpio_top:i_gpio_b|ext_pad_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[10] -to "gpio_top:i_gpio_b|ext_pad_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[11] -to "gpio_top:i_gpio_b|ext_pad_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "gpio_top:i_gpio_b|wb_inta" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to key[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to key[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to key[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to key[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "gpio_top:i_gpio_b|wb_inta" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to key[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to key[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to key[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to key[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[12] -to "gpio_top:i_gpio_b|wb_inta" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[13] -to "gpio_top:i_gpio_b|wb_inta_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[14] -to key[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[15] -to key[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[16] -to key[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[17] -to key[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[18] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[19] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[20] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[21] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[22] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[23] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[24] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[25] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[26] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[27] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[28] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[29] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[30] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[31] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[32] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[33] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[34] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[35] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[36] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[37] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[38] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[39] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[40] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[41] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_a[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[42] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[43] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[44] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[45] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_bls_n[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[46] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_cs_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[47] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[48] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[49] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[50] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[51] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[52] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[53] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[54] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[55] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[56] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[57] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[58] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[59] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[60] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[61] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[62] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[63] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[64] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[65] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[66] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[67] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[68] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[69] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[70] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[71] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[72] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[73] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[74] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[75] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[76] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[77] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[78] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_d[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[79] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_oe_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[80] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|mem_we_n" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[81] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_ack_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[82] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[83] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[84] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[85] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[86] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[87] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[88] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[89] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[90] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[91] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[92] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[93] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[94] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[95] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[96] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[97] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[98] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[99] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[100] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[101] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[102] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[103] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[104] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[105] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_addr_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[106] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_cyc_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[107] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[108] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[109] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[110] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[111] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[112] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[113] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[114] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[115] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[116] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[117] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[118] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[119] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[120] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[121] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[122] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[123] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[124] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[125] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[126] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[127] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[128] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[129] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[130] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[131] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[132] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[133] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[134] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[135] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[136] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[137] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[138] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[139] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[140] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[141] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[142] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[143] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[144] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[145] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[146] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[147] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[148] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[149] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[150] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[151] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[152] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[153] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[154] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[155] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[156] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[157] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[158] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[159] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[160] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[161] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[162] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[163] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[164] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[165] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[166] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[167] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[168] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[169] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[170] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_i_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[171] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[172] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[173] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[174] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[175] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[176] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[177] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[178] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[179] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[180] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[181] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[182] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[183] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[184] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[185] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[186] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[187] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[188] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[189] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[190] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[191] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[192] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[193] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[194] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[195] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[196] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[197] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[198] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[199] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[200] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[201] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[202] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[203] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[204] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[205] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[206] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[207] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[208] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[209] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[210] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[211] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[212] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[213] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[214] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[215] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[216] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[217] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[218] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[219] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[220] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[221] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[222] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[223] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[224] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[225] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[226] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[227] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[228] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[229] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[230] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[231] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[232] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[233] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[234] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_data_o_r[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[235] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_err_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[236] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rst_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[237] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_rty_i" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[238] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[239] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[240] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[241] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_sel_o[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[242] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_stb_o" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[243] -to "wb_async_mem_bridge:i_wb_async_mem_bridge|wb_we_o" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=244" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=244" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=244" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=1730" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=245" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=27139" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=33058" -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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