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/trunk/bench/debounce_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/bench/debounce_atlys_top_bit.zip
trunk/bench/debounce_atlys_top_bit.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/bench/debounce_atlys_top_map.psr =================================================================== --- trunk/bench/debounce_atlys_top_map.psr (nonexistent) +++ trunk/bench/debounce_atlys_top_map.psr (revision 6) @@ -0,0 +1,151 @@ +Release 13.1 Physical Synthesis Report O.40d (nt) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + +TABLE OF CONTENTS + 1) Physical Synthesis Options Summary + 2) Optimizations statistics and details + + +========================================================================= +* Physical Synthesis Options Summary * +========================================================================= +---- Options +Global Optimization : ON + Retiming : OFF + Equivalent Register Removal : ON +Timing-Driven Packing and Placement : ON + Logic Optimization : OFF + Register Duplication : OFF + +---- Intelligent clock gating : OFF + +---- Target Parameters +Target Device : 6slx45csg324-2 + +========================================================================= + + +========================================================================= +* Optimizations * +========================================================================= +---- Statistics + Number of LUTs removed by SmartOpt Trimming | 105 + + Overall change in number of design objects | -105 + + +---- Details + + + +Removed components | Optimization +-------------------------------------------------------|-------------------------- +][103_12 | SmartOpt Trimming +][25_0 | SmartOpt Trimming +][29_1 | SmartOpt Trimming +][33_2 | SmartOpt Trimming +][40_3 | SmartOpt Trimming +][47_4 | SmartOpt Trimming +][54_5 | SmartOpt Trimming +][61_6 | SmartOpt Trimming +][68_7 | SmartOpt Trimming +][75_8 | SmartOpt Trimming +][82_9 | SmartOpt Trimming +][89_10 | SmartOpt Trimming +][96_11 | SmartOpt Trimming +][const_100_109 | SmartOpt Trimming +][const_101_110 | SmartOpt Trimming +][const_103_112 | SmartOpt Trimming +][const_104_113 | SmartOpt Trimming +][const_106_115 | SmartOpt Trimming +][const_107_116 | SmartOpt Trimming +][const_109_118 | SmartOpt Trimming +][const_10_15 | SmartOpt Trimming +][const_110_119 | SmartOpt Trimming +][const_112_121 | SmartOpt Trimming +][const_113_122 | SmartOpt Trimming +][const_115_124 | SmartOpt Trimming +][const_116_125 | SmartOpt Trimming +][const_118_127 | SmartOpt Trimming +][const_119_128 | SmartOpt Trimming +][const_11_16 | SmartOpt Trimming +][const_121_130 | SmartOpt Trimming +][const_122_131 | SmartOpt Trimming +][const_124_133 | SmartOpt Trimming +][const_125_134 | SmartOpt Trimming +][const_127_136 | SmartOpt Trimming +][const_128_137 | SmartOpt Trimming +][const_12_17 | SmartOpt Trimming +][const_13_18 | SmartOpt Trimming +][const_14_19 | SmartOpt Trimming +][const_15_20 | SmartOpt Trimming +][const_16_21 | SmartOpt Trimming +][const_17_22 | SmartOpt Trimming +][const_18_23 | SmartOpt Trimming +][const_19_24 | SmartOpt Trimming +][const_20_25 | SmartOpt Trimming +][const_21_26 | SmartOpt Trimming +][const_22_27 | SmartOpt Trimming +][const_23_28 | SmartOpt Trimming +][const_24_31 | SmartOpt Trimming +][const_25_32 | SmartOpt Trimming +][const_26_35 | SmartOpt Trimming +][const_27_36 | SmartOpt Trimming +][const_28_38 | SmartOpt Trimming +][const_29_39 | SmartOpt Trimming +][const_30_41 | SmartOpt Trimming +][const_31_42 | SmartOpt Trimming +][const_32_44 | SmartOpt Trimming +][const_33_45 | SmartOpt Trimming +][const_34_47 | SmartOpt Trimming +][const_35_48 | SmartOpt Trimming +][const_36_50 | SmartOpt Trimming +][const_37_51 | SmartOpt Trimming +][const_38_53 | SmartOpt Trimming +][const_39_54 | SmartOpt Trimming +][const_40_55 | SmartOpt Trimming +][const_41_56 | SmartOpt Trimming +][const_43_57 | SmartOpt Trimming +][const_44_58 | SmartOpt Trimming +][const_46_59 | SmartOpt Trimming +][const_47_60 | SmartOpt Trimming +][const_49_61 | SmartOpt Trimming +][const_50_62 | SmartOpt Trimming +][const_52_63 | SmartOpt Trimming +][const_53_64 | SmartOpt Trimming +][const_55_65 | SmartOpt Trimming +][const_56_66 | SmartOpt Trimming +][const_58_67 | SmartOpt Trimming +][const_59_68 | SmartOpt Trimming +][const_61_69 | SmartOpt Trimming +][const_62_70 | SmartOpt Trimming +][const_64_75 | SmartOpt Trimming +][const_65_76 | SmartOpt Trimming +][const_67_77 | SmartOpt Trimming +][const_68_78 | SmartOpt Trimming +][const_70_79 | SmartOpt Trimming +][const_71_80 | SmartOpt Trimming +][const_73_81 | SmartOpt Trimming +][const_74_82 | SmartOpt Trimming +][const_76_83 | SmartOpt Trimming +][const_77_84 | SmartOpt Trimming +][const_79_85 | SmartOpt Trimming +][const_80_86 | SmartOpt Trimming +][const_82_87 | SmartOpt Trimming +][const_83_88 | SmartOpt Trimming +][const_85_89 | SmartOpt Trimming +][const_86_90 | SmartOpt Trimming +][const_88_91 | SmartOpt Trimming +][const_89_92 | SmartOpt Trimming +][const_8_13 | SmartOpt Trimming +][const_91_100 | SmartOpt Trimming +][const_92_101 | SmartOpt Trimming +][const_94_103 | SmartOpt Trimming +][const_95_104 | SmartOpt Trimming +][const_97_106 | SmartOpt Trimming +][const_98_107 | SmartOpt Trimming +][const_9_14 | SmartOpt Trimming + + + Flops added for Enable Generation +------------------------- Index: trunk/bench/par_usage_statistics.html =================================================================== --- trunk/bench/par_usage_statistics.html (nonexistent) +++ trunk/bench/par_usage_statistics.html (revision 6) @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Par Statistics
Total Non-vccgnd Signals=83
Total Non-vccgnd Design Pins=212
Total Non-vccgnd Conns=212
Total Non-vccgnd Timing Constrained Conns=179
Phase 1 CPU=5.2 sec
Phase 2 CPU=5.9 sec
Phase 3 CPU=6.2 sec
Phase 4 CPU=7.6 sec
Phase 5 CPU=7.8 sec
Phase 6 CPU=7.8 sec
Phase 7 CPU=7.8 sec
Phase 8 CPU=7.8 sec
Phase 9 CPU=7.8 sec
Phase 10 CPU=7.8 sec
AvgWirelenPerPin Fanout 1=9.0
AvgWirelenPerPin Fanout 2=23.5
AvgWirelenPerPin Fanout 3=7.7
AvgWirelenPerPin Fanout 4=10.8
AvgWirelenPerPin Fanout 10=1.0
AvgWirelenPerPin Fanout 50=2.6
AvgWirelenPerPin Fanout 100=0.0
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0075
Index: trunk/bench/debounce_vhdl_bench.gise =================================================================== --- trunk/bench/debounce_vhdl_bench.gise (revision 5) +++ trunk/bench/debounce_vhdl_bench.gise (revision 6) @@ -21,8 +21,176 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
/trunk/bench/debounce_atlys_top_map.map
0,0 → 1,151
Release 13.1 Map O.40d (nt)
Xilinx Map Application Log File for Design 'debounce_atlys_top'
 
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf
Target Device : xc6slx45
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Aug 11 00:07:05 2011
 
Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 7 secs
Total CPU time at the beginning of Placer: 7 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:74f3dbc5) REAL time: 8 secs
 
Phase 4.2 Initial Placement for Architecture Specific Features
 
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:d6fae235) REAL time: 10 secs
 
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:d6fae235) REAL time: 10 secs
 
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
 
Phase 9.8 Global Placement
...
..
Phase 9.8 Global Placement (Checksum:2b00d50b) REAL time: 10 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:2b00d50b) REAL time: 10 secs
 
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
 
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
 
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1bfd6a39) REAL time: 11 secs
 
Total REAL time to Placer completion: 11 secs
Total CPU time to Placer completion: 11 secs
Running post-placement packing...
Writing output files...
 
Design Summary
--------------
 
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54,576 1%
Number used as Flip Flops: 46
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 43 out of 27,288 1%
Number used as logic: 38 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 12
Number using O5 and O6: 8
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 5
Number with same-slice register load: 4
Number with same-slice carry load: 1
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 17 out of 6,822 1%
Number of LUT Flip Flop pairs used: 57
Number with an unused Flip Flop: 21 out of 57 36%
Number with an unused LUT: 14 out of 57 24%
Number of fully used LUT-FF pairs: 22 out of 57 38%
Number of unique control sets: 3
Number of slice register sites lost
to control set restrictions: 2 out of 54,576 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 34 out of 218 15%
Number of LOCed IOBs: 34 out of 34 100%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
Average Fanout of Non-Clock Nets: 2.57
 
Peak Memory Usage: 299 MB
Total REAL time to MAP completion: 11 secs
Total CPU time to MAP completion (all processors): 11 secs
 
Mapping completed.
See MAP report file "debounce_atlys_top_map.mrp" for details.
/trunk/bench/debounce_atlys_top.twr
0,0 → 1,106
--------------------------------------------------------------------------------
Release 13.1 Trace (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
 
C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o
debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf
 
Design file: debounce_atlys_top.ncd
Physical constraint file: debounce_atlys_top.pcf
Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
Report level: verbose report
 
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
 
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Setup/Hold to clock gclk_i
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
sw_i<0> | 5.038(R)| SLOW | -2.761(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<1> | 5.576(R)| SLOW | -3.098(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<2> | 5.317(R)| SLOW | -2.953(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<3> | 4.491(R)| SLOW | -2.388(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<4> | 2.742(R)| SLOW | -1.466(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<5> | 4.819(R)| SLOW | -2.715(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<6> | 4.336(R)| SLOW | -2.454(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<7> | 5.893(R)| SLOW | -3.333(R)| FAST |gclk_i_BUFGP | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
 
Clock gclk_i to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<8> | 11.232(R)| SLOW | 4.814(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<9> | 11.480(R)| SLOW | 4.979(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<10> | 11.254(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<11> | 11.049(R)| SLOW | 4.732(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<12> | 11.559(R)| SLOW | 5.013(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<13> | 11.939(R)| SLOW | 5.209(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<14> | 12.377(R)| SLOW | 5.519(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<15> | 12.060(R)| SLOW | 5.330(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<0> | 9.814(R)| SLOW | 4.065(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<1> | 9.656(R)| SLOW | 3.955(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<2> | 9.469(R)| SLOW | 3.865(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<3> | 9.929(R)| SLOW | 4.132(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<4> | 9.577(R)| SLOW | 3.889(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<5> | 17.272(R)| SLOW | 8.413(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<6> | 11.323(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<7> | 10.605(R)| SLOW | 4.453(R)| FAST |gclk_i_BUFGP | 0.000|
strb_o | 13.397(R)| SLOW | 6.237(R)| FAST |gclk_i_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
 
Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i | 4.464| | | |
---------------+---------+---------+---------+---------+
 
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
sw_i<0> |dbg_o<0> | 16.209|
sw_i<1> |dbg_o<1> | 16.941|
sw_i<2> |dbg_o<2> | 16.803|
sw_i<3> |dbg_o<3> | 9.229|
sw_i<4> |dbg_o<4> | 7.980|
sw_i<5> |dbg_o<5> | 8.917|
sw_i<6> |dbg_o<6> | 9.026|
sw_i<7> |dbg_o<7> | 15.558|
---------------+---------------+---------+
 
 
Analysis completed Thu Aug 11 00:07:33 2011
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 178 MB
 
 
 
/trunk/bench/debounce_atlys_top.syr
0,0 → 1,421
Release 13.1 - xst O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
 
 
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: debounce_atlys_top.prj
 
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
 
 
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "debounce_atlys_top.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
 
---- Target Parameters
Output File Name : "debounce_atlys_top"
Output Format : NGC
Target Device : xc6slx45-2-csg324
 
---- Source Options
Top Module Name : debounce_atlys_top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Gray
Safe Implementation : No
FSM Style : LUT
RAM Extraction : No
ROM Extraction : No
Shift Register Extraction : NO
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
 
---- Target Options
LUT Combining : Area
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
 
---- General Options
Optimization Goal : Speed
Optimization Effort : 2
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
 
=========================================================================
 
 
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\grp_debouncer.vhd" into library work
Parsing entity <grp_debouncer>.
Parsing architecture <rtl> of entity <grp_debouncer>.
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" into library work
Parsing entity <debounce_atlys_top>.
Parsing architecture <rtl> of entity <debounce_atlys_top>.
 
=========================================================================
* HDL Elaboration *
=========================================================================
 
Elaborating entity <debounce_atlys_top> (architecture <rtl>) from library <work>.
 
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
 
=========================================================================
* HDL Synthesis *
=========================================================================
 
Synthesizing Unit <debounce_atlys_top>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
Found 8-bit register for signal <led_o>.
Summary:
inferred 8 D-type flip-flop(s).
Unit <debounce_atlys_top> synthesized.
 
Synthesizing Unit <grp_debouncer>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
N = 8
CNT_VAL = 5000
Found 8-bit register for signal <reg_A>.
Found 8-bit register for signal <reg_B>.
Found 1-bit register for signal <strb_reg>.
Found 8-bit register for signal <reg_out>.
Found 13-bit register for signal <cnt_reg>.
Found 14-bit adder for signal <n0026> created at line 167.
Found 8-bit comparator not equal for signal <n0009> created at line 192
Found 8-bit comparator not equal for signal <n0011> created at line 194
Summary:
inferred 1 Adder/Subtractor(s).
inferred 38 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <grp_debouncer> synthesized.
 
=========================================================================
HDL Synthesis Report
 
Macro Statistics
# Adders/Subtractors : 1
14-bit adder : 1
# Registers : 6
1-bit register : 1
13-bit register : 1
8-bit register : 4
# Comparators : 2
8-bit comparator not equal : 2
 
=========================================================================
 
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
 
 
Synthesizing (advanced) Unit <grp_debouncer>.
The following registers are absorbed into counter <cnt_reg>: 1 register on signal <cnt_reg>.
Unit <grp_debouncer> synthesized (advanced).
 
=========================================================================
Advanced HDL Synthesis Report
 
Macro Statistics
# Counters : 1
13-bit up counter : 1
# Registers : 33
Flip-Flops : 33
# Comparators : 2
8-bit comparator not equal : 2
 
=========================================================================
 
=========================================================================
* Low Level Synthesis *
=========================================================================
 
Optimizing unit <debounce_atlys_top> ...
 
Optimizing unit <grp_debouncer> ...
 
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block debounce_atlys_top, actual ratio is 0.
 
Final Macro Processing ...
 
=========================================================================
Final Register Report
 
Macro Statistics
# Registers : 46
Flip-Flops : 46
 
=========================================================================
 
=========================================================================
* Partition Report *
=========================================================================
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
=========================================================================
* Design Summary *
=========================================================================
 
Top Level Output File Name : debounce_atlys_top.ngc
 
Primitive and Black Box Usage:
------------------------------
# BELS : 75
# GND : 1
# INV : 1
# LUT1 : 12
# LUT3 : 2
# LUT4 : 8
# LUT6 : 25
# MUXCY : 12
# VCC : 1
# XORCY : 13
# FlipFlops/Latches : 46
# FD : 30
# FDE : 16
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 33
# IBUF : 8
# OBUF : 25
 
Device utilization summary:
---------------------------
 
Selected Device : 6slx45csg324-2
 
 
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54576 0%
Number of Slice LUTs: 48 out of 27288 0%
Number used as Logic: 48 out of 27288 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 72
Number with an unused Flip Flop: 26 out of 72 36%
Number with an unused LUT: 24 out of 72 33%
Number of fully used LUT-FF pairs: 22 out of 72 30%
Number of unique control sets: 3
 
IO Utilization:
Number of IOs: 34
Number of bonded IOBs: 34 out of 218 15%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
 
---------------------------
Partition Resource Summary:
---------------------------
 
No Partitions were found in this design.
 
---------------------------
 
 
=========================================================================
Timing Report
 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
 
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
gclk_i | BUFGP | 46 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
 
Timing Summary:
---------------
Speed Grade: -2
 
Minimum period: 4.749ns (Maximum Frequency: 210.571MHz)
Minimum input arrival time before clock: 2.127ns
Maximum output required time after clock: 4.412ns
Maximum combinational path delay: 4.965ns
 
Timing Details:
---------------
All values displayed in nanoseconds (ns)
 
=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
Clock period: 4.749ns (frequency: 210.571MHz)
Total number of paths / destination ports: 761 / 54
-------------------------------------------------------------------------
Delay: 4.749ns (Levels of Logic = 3)
Source: Inst_sw_debouncer/cnt_reg_0 (FF)
Destination: Inst_sw_debouncer/strb_reg (FF)
Source Clock: gclk_i rising
Destination Clock: gclk_i rising
 
Data Path: Inst_sw_debouncer/cnt_reg_0 to Inst_sw_debouncer/strb_reg
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 1.181 Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
LUT6:I0->O 9 0.254 1.084 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
LUT3:I1->O 14 0.250 1.127 Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next7 (Inst_sw_debouncer/strb_next)
FD:D 0.074 Inst_sw_debouncer/strb_reg
----------------------------------------
Total 4.749ns (1.357ns logic, 3.392ns route)
(28.6% logic, 71.4% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 2.127ns (Levels of Logic = 1)
Source: sw_i<7> (PAD)
Destination: Inst_sw_debouncer/reg_A_7 (FF)
Destination Clock: gclk_i rising
 
Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
FD:D 0.074 Inst_sw_debouncer/reg_A_7
----------------------------------------
Total 2.127ns (1.402ns logic, 0.725ns route)
(65.9% logic, 34.1% route)
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
Total number of paths / destination ports: 17 / 17
-------------------------------------------------------------------------
Offset: 4.412ns (Levels of Logic = 1)
Source: Inst_sw_debouncer/strb_reg (FF)
Destination: strb_o (PAD)
Source Clock: gclk_i rising
 
Data Path: Inst_sw_debouncer/strb_reg to strb_o
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 9 0.525 0.975 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
OBUF:I->O 2.912 strb_o_OBUF (strb_o)
----------------------------------------
Total 4.412ns (3.437ns logic, 0.975ns route)
(77.9% logic, 22.1% route)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay: 4.965ns (Levels of Logic = 2)
Source: sw_i<7> (PAD)
Destination: dbg_o<7> (PAD)
 
Data Path: sw_i<7> to dbg_o<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
OBUF:I->O 2.912 dbg_o_7_OBUF (dbg_o<7>)
----------------------------------------
Total 4.965ns (4.240ns logic, 0.725ns route)
(85.4% logic, 14.6% route)
 
=========================================================================
 
Cross Clock Domains Report:
--------------------------
 
Clock to Setup on destination clock gclk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i | 4.749| | | |
---------------+---------+---------+---------+---------+
 
=========================================================================
 
 
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.87 secs
-->
 
Total memory usage is 188424 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/trunk/bench/debounce_atlys_top.xst
0,0 → 1,51
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn debounce_atlys_top.prj
-ifmt mixed
-ofn debounce_atlys_top
-ofmt NGC
-p xc6slx45-2-csg324
-top debounce_atlys_top
-opt_mode Speed
-opt_level 2
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Area
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Gray
-safe_implementation No
-fsm_style LUT
-ram_extract No
-rom_extract No
-shreg_extract NO
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
/trunk/bench/debounce_atlys_top.vhd
57,7 → 57,7
--=============================================================================================
-- debounce generics
constant N : integer := 8; -- 8 bits (8 switch inputs)
constant CNT_VAL : integer := 1000; -- debounce period = 1000 * 10 ns (10 us)
constant CNT_VAL : integer := 5000; -- debounce period = 1000 * 10 ns (50 us)
--=============================================================================================
-- Signals for internal operation
105,8 → 105,8
leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
 
-- update debug register
dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has debounced switch data
dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has direct switch connections
dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has direct switch connections
dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has debounced switch data
 
--=============================================================================================
/trunk/bench/debounce_atlys_top_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/11/2011 - 00:07:47)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>debounce_vhdl_bench.xise</TD>
13,18 → 13,19
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>debounce_atlys_top</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
<TD>Programming File Generated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
31,49 → 32,375
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD>
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
<TD>0 &nbsp;<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>46</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>46</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>43</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>38</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>18</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>12</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>8</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>6,408</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>5</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>4</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>6,822</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>57</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>36%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>24%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>22</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>38%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
<TD ALIGN=RIGHT>3</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>218</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>116</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>232</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>256</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.57</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
 
 
 
 
 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:00 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:03 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:17 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:27 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:33 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:43 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:17 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:43 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:47 2011</TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 08/10/2011 - 21:25:06</center>
<br><center><b>Date Generated:</b> 08/11/2011 - 00:09:45</center>
</BODY></HTML>
/trunk/bench/debounce_atlys_top.par
0,0 → 1,178
Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
 
DEVELOP-W7:: Thu Aug 11 00:07:18 2011
 
par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
debounce_atlys_top.ncd debounce_atlys_top.pcf
 
 
Constraints file: debounce_atlys_top.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\13.1\ISE_DS\ISE\.
"debounce_atlys_top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -2
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
 
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
 
Device speed data version: "PRODUCTION 1.18 2011-04-07".
 
 
 
Device Utilization Summary:
 
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54,576 1%
Number used as Flip Flops: 46
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 43 out of 27,288 1%
Number used as logic: 38 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 12
Number using O5 and O6: 8
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 5
Number with same-slice register load: 4
Number with same-slice carry load: 1
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 17 out of 6,822 1%
Number of LUT Flip Flop pairs used: 57
Number with an unused Flip Flop: 21 out of 57 36%
Number with an unused LUT: 14 out of 57 24%
Number of fully used LUT-FF pairs: 22 out of 57 38%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 34 out of 218 15%
Number of LOCed IOBs: 34 out of 34 100%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
 
Overall effort level (-ol): High
Router effort level (-rl): High
 
WARNING:Par:545 - Multi-threading ("-mt" option) is not supported for the Performance Evaluation Mode. PAR will use only one processor.
 
Starting initial Timing Analysis. REAL time: 4 secs
Finished initial Timing Analysis. REAL time: 4 secs
 
Starting Router
 
 
Phase 1 : 231 unrouted; REAL time: 5 secs
 
Phase 2 : 199 unrouted; REAL time: 5 secs
 
Phase 3 : 51 unrouted; REAL time: 6 secs
 
Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Updating file: debounce_atlys_top.ncd with current fully routed design.
 
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
Total REAL time to Router completion: 7 secs
Total CPU time to Router completion: 7 secs
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
 
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.464ns| N/A| 0
k_i_BUFGP | HOLD | 0.388ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 8 secs
Total CPU time to PAR completion: 8 secs
 
Peak Memory Usage: 262 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2
 
Writing design to file debounce_atlys_top.ncd
 
 
 
PAR done!
/trunk/bench/debounce_vhdl_bench.xise
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="debounce_atlys.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
 
/trunk/bench/debounce_atlys_top_map.mrp
0,0 → 1,283
Release 13.1 Map O.40d (nt)
Xilinx Mapping Report File for Design 'debounce_atlys_top'
 
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
off -o debounce_atlys_top_map.ncd debounce_atlys_top.ngd debounce_atlys_top.pcf
Target Device : xc6slx45
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Aug 11 00:07:05 2011
 
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54,576 1%
Number used as Flip Flops: 46
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 43 out of 27,288 1%
Number used as logic: 38 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 12
Number using O5 and O6: 8
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 5
Number with same-slice register load: 4
Number with same-slice carry load: 1
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 17 out of 6,822 1%
Number of LUT Flip Flop pairs used: 57
Number with an unused Flip Flop: 21 out of 57 36%
Number with an unused LUT: 14 out of 57 24%
Number of fully used LUT-FF pairs: 22 out of 57 38%
Number of unique control sets: 3
Number of slice register sites lost
to control set restrictions: 2 out of 54,576 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 34 out of 218 15%
Number of LOCed IOBs: 34 out of 34 100%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 8 0%
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 58 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 4 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
Average Fanout of Non-Clock Nets: 2.57
 
Peak Memory Usage: 299 MB
Total REAL time to MAP completion: 11 secs
Total CPU time to MAP completion (all processors): 11 secs
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
 
Section 3 - Informational
-------------------------
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:LIT:243 - Logical network gclk_i_BUFGP/N2 has no load.
INFO:LIT:243 - Logical network gclk_i_BUFGP/N3 has no load.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
 
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
2 block(s) optimized away
2 signal(s) removed
12 Block(s) redundant
 
Section 5 - Removed Logic
-------------------------
 
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
 
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
 
The signal "gclk_i_BUFGP/N2" is sourceless and has been removed.
The signal "gclk_i_BUFGP/N3" is sourceless and has been removed.
Unused block "gclk_i_BUFGP/XST_GND" (ZERO) removed.
Unused block "gclk_i_BUFGP/XST_VCC" (ONE) removed.
 
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
 
Redundant Block(s):
TYPE BLOCK
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<11>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<10>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<9>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<8>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<7>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
LUT1 Inst_sw_debouncer/Mcount_cnt_reg_xor<12>_rt
 
Section 6 - IOB Properties
--------------------------
 
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| dbg_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| dbg_o<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gclk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| led_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| led_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| strb_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| sw_i<7> | IOB | INPUT | LVCMOS25 | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Partition Implementation Status
-------------------------------
 
No Partitions were found in this design.
 
-------------------------------
 
Area Group Information
----------------------
 
No area groups were found in this design.
 
----------------------
 
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
 
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
 
Section 11 - Configuration String Details
-----------------------------------------
 
Section 12 - Control Set Information
------------------------------------
+-----------------------------------------------------------------------------------------------------------+
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
+-----------------------------------------------------------------------------------------------------------+
| gclk_i_BUFGP | | | | 7 | 30 |
| gclk_i_BUFGP | | | Inst_sw_debouncer/strb_reg | 2 | 8 |
| gclk_i_BUFGP | | | lut119_33 | 3 | 8 |
+-----------------------------------------------------------------------------------------------------------+
 
Section 13 - Utilization by Hierarchy
-------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| debounce_atlys_top/ | | 12/26 | 8/46 | 26/27 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top |
| +Inst_sw_debouncer | | 14/14 | 38/38 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top/Inst_sw_debouncer |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
<A> is the number of elements that belong to that specific hierarchical module.
<B> is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

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