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https://opencores.org/ocsvn/dirac/dirac/trunk
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- This comparison shows the changes necessary to convert path
/dirac/tags/dirac_0_0_1_0/src/common
- from Rev 3 to Rev 12
- ↔ Reverse comparison
Rev 3 → Rev 12
/INPUT_CONTROL.vhd
0,0 → 1,107
-- ***** BEGIN LICENSE BLOCK ***** |
-- |
-- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $ |
-- * |
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1 |
-- * |
-- * The contents of this file are subject to the Mozilla Public License |
-- * Version 1.1 (the "License"); you may not use this file except in compliance |
-- * with the License. You may obtain a copy of the License at |
-- * http://www.mozilla.org/MPL/ |
-- * |
-- * Software distributed under the License is distributed on an "AS IS" basis, |
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for |
-- * the specific language governing rights and limitations under the License. |
-- * |
-- * The Original Code is BBC Research and Development code. |
-- * |
-- * The Initial Developer of the Original Code is the British Broadcasting |
-- * Corporation. |
-- * Portions created by the Initial Developer are Copyright (C) 2004. |
-- * All Rights Reserved. |
-- * |
-- * Contributor(s): Peter Bleackley (Original author) |
-- * |
-- * Alternatively, the contents of this file may be used under the terms of |
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser |
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of |
-- * the GPL or the LGPL are applicable instead of those above. If you wish to |
-- * allow use of your version of this file only under the terms of the either |
-- * the GPL or LGPL and not to allow others to use your version of this file |
-- * under the MPL, indicate your decision by deleting the provisions above |
-- * and replace them with the notice and other provisions required by the GPL |
-- * or LGPL. If you do not delete the provisions above, a recipient may use |
-- * your version of this file under the terms of any one of the MPL, the GPL |
-- * or the LGPL. |
-- * ***** END LICENSE BLOCK ***** */ |
|
|
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
-- Uncomment the following lines to use the declarations that are |
-- provided for instantiating Xilinx primitive components. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity INPUT_CONTROL is |
Port ( ENABLE : in std_logic; |
DATA_IN : in std_logic; |
BUFFER_CONTROL : in std_logic; |
DEMAND : in std_logic; |
RESET : in std_logic; |
CLOCK : in std_logic; |
SENDING : out std_logic; |
DATA_OUT : out std_logic); |
end INPUT_CONTROL; |
|
architecture RTL of INPUT_CONTROL is |
component FIFO |
port( WRITE_ENABLE : in std_logic; |
DATA_IN : in std_logic; |
READ_ENABLE : in std_logic; |
RESET : in std_logic; |
CLOCK : in std_logic; |
DATA_OUT : out std_logic; |
EMPTY : out std_logic); |
end component FIFO; |
signal FIFO_WRITE_ENABLE : std_logic; |
signal FIFO_READ_ENABLE : std_logic; |
signal FIFO_DATA_IN : std_logic; |
signal FIFO_DATA_OUT : std_logic; |
signal FIFO_EMPTY : std_logic; |
signal USE_BUFFER : std_logic; |
signal PUT_IN_BUFFER : std_logic; |
begin |
|
STORAGE : FIFO |
port map(WRITE_ENABLE => FIFO_WRITE_ENABLE, |
DATA_IN => FIFO_DATA_IN, |
READ_ENABLE => FIFO_READ_ENABLE, |
RESET => RESET, |
CLOCK => CLOCK, |
DATA_OUT => FIFO_DATA_OUT, |
EMPTY => FIFO_EMPTY); |
|
FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER; |
FIFO_DATA_IN <= DATA_IN and USE_BUFFER; |
FIFO_READ_ENABLE <= DEMAND and USE_BUFFER; |
|
PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL; |
USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY; |
|
OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN) |
begin |
if USE_BUFFER = '1' then |
SENDING <= DEMAND; |
DATA_OUT <= FIFO_DATA_OUT; |
else |
SENDING <= ENABLE; |
DATA_OUT <= DATA_IN; |
end if; |
end process OUTPUT_SELECT; |
|
|
end RTL; |
INPUT_CONTROL.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: count_unit.prj
===================================================================
--- count_unit.prj (nonexistent)
+++ count_unit.prj (revision 12)
@@ -0,0 +1,2 @@
+vhdl work D_TYPE.vhd
+vhdl work COUNT_UNIT.vhd
count_unit.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: arithmetic_unit.prj
===================================================================
--- arithmetic_unit.prj (nonexistent)
+++ arithmetic_unit.prj (revision 12)
@@ -0,0 +1,2 @@
+vhdl work D_TYPE.vhd
+vhdl work ARITHMETIC_UNIT.vhd
arithmetic_unit.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: convergence_check.prj
===================================================================
--- convergence_check.prj (nonexistent)
+++ convergence_check.prj (revision 12)
@@ -0,0 +1 @@
+vhdl work CONVERGENCE_CHECK.vhd
convergence_check.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: STORE_BLOCK.vhd
===================================================================
--- STORE_BLOCK.vhd (nonexistent)
+++ STORE_BLOCK.vhd (revision 12)
@@ -0,0 +1,86 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: STORE_BLOCK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity STORE_BLOCK is
+ Port ( LOAD_IN : in std_logic;
+ SHIFT_IN : in std_logic;
+ SHIFT : in std_logic;
+ ENABLE : in std_logic;
+ CLK : in std_logic;
+ OUTPUT : out std_logic);
+end STORE_BLOCK;
+
+architecture RTL of STORE_BLOCK is
+ component ENABLEABLE_D_TYPE
+ port (DATA_IN, ENABLE, CLK: in std_logic;
+ DATA_OUT: out std_logic);
+ end component;
+
+ signal LOAD_VALUE : std_logic;
+begin
+
+
+ STORAGE: ENABLEABLE_D_TYPE
+ port map(DATA_IN => LOAD_VALUE,
+ ENABLE => ENABLE,
+ CLK => CLK,
+ DATA_OUT => OUTPUT);
+
+ SELECT_VALUE: process(SHIFT,SHIFT_IN,LOAD_IN)
+ begin
+ if SHIFT = '1' then
+ LOAD_VALUE <= SHIFT_IN;
+ else
+ LOAD_VALUE <= LOAD_IN;
+ end if;
+ end process SELECT_VALUE;
+
+
+
+
+end RTL;
STORE_BLOCK.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: input_control.prj
===================================================================
--- input_control.prj (nonexistent)
+++ input_control.prj (revision 12)
@@ -0,0 +1,5 @@
+vhdl work D_TYPE.vhd
+vhdl work COUNT_UNIT.vhd
+vhdl work ENABLEABLE_D_TYPE.vhd
+vhdl work FIFO.vhd
+vhdl work INPUT_CONTROL.vhd
input_control.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ENABLEABLE_D_TYPE.vhd
===================================================================
--- ENABLEABLE_D_TYPE.vhd (nonexistent)
+++ ENABLEABLE_D_TYPE.vhd (revision 12)
@@ -0,0 +1,82 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: ENABLEABLE_D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ENABLEABLE_D_TYPE is
+ Port ( DATA_IN : in std_logic;
+ ENABLE : in std_logic;
+ CLK : in std_logic;
+ DATA_OUT : out std_logic);
+end ENABLEABLE_D_TYPE;
+
+architecture RTL of ENABLEABLE_D_TYPE is
+ signal RETAIN : std_logic;
+ signal D_IN : std_logic;
+ component D_TYPE
+ port(D,CLOCK: in std_logic;
+ Q: out std_logic);
+ end component;
+begin
+
+ FLIP_FLOP: D_TYPE
+ port map(
+ D => D_IN,
+ CLOCK => CLK,
+ Q => RETAIN);
+
+ DATA_OUT <= RETAIN;
+
+ LOAD: process(ENABLE,DATA_IN,RETAIN)
+ begin
+ if ENABLE = '1' then
+ D_IN <= DATA_IN;
+ else
+ D_IN <= RETAIN;
+ end if;
+ end process LOAD;
+
+end architecture RTL;
ENABLEABLE_D_TYPE.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: store_block.prj
===================================================================
--- store_block.prj (nonexistent)
+++ store_block.prj (revision 12)
@@ -0,0 +1,3 @@
+vhdl work D_TYPE.vhd
+vhdl work ENABLEABLE_D_TYPE.vhd
+vhdl work STORE_BLOCK.vhd
store_block.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: FIFO.vhd
===================================================================
--- FIFO.vhd (nonexistent)
+++ FIFO.vhd (revision 12)
@@ -0,0 +1,212 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: FIFO.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity FIFO is
+ generic (RANK : integer range 0 to 16 :=8);
+ Port ( WRITE_ENABLE : in std_logic;
+ DATA_IN : in std_logic;
+ READ_ENABLE : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ DATA_OUT : out std_logic;
+ EMPTY : out std_logic);
+end FIFO;
+
+architecture RTL of FIFO is
+ component ENABLEABLE_D_TYPE
+ port (DATA_IN : in std_logic;
+ ENABLE : in std_logic;
+ CLK : in std_logic;
+ DATA_OUT: out std_logic);
+ end component ENABLEABLE_D_TYPE;
+ component D_TYPE
+ port( D : in std_logic;
+ CLOCK : in std_logic;
+ Q : out std_logic);
+end component D_TYPE;
+ component COUNT_UNIT
+ port( INCREMENT : in std_logic;
+ DECREMENT : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ OUTPUT : out std_logic;
+ INCREMENT_CARRY : out std_logic;
+ DECREMENT_CARRY : out std_logic);
+end component COUNT_UNIT;
+ function TWO_TO_N(N: integer) return integer is
+ variable A: integer;
+ begin
+ A := 1;
+ for Z in 0 to N - 1 loop
+ A := 2*A;
+ end loop;
+ return A;
+ end function TWO_TO_N;
+ function ZERO_VALUE(ADDRESS: std_logic_vector) return std_logic is
+ begin
+ for J in 0 to RANK - 1 loop
+ if ADDRESS(J) = '1' then
+ return '0';
+ end if;
+ end loop;
+ return '1';
+ end function ZERO_VALUE;
+
+ signal READ_ADDRESS : std_logic_vector (RANK - 1 downto 0);
+ signal INC : std_logic_vector (RANK - 1 downto 0);
+ signal DEC : std_logic_vector (RANK - 1 downto 0);
+ type MATRIX is
+ array (RANK downto 0) of std_logic_vector (TWO_TO_N(RANK) -1 downto 0);
+ signal GET_OUTPUT: MATRIX;
+ signal NEWVAL : std_logic_vector(TWO_TO_N(RANK) - 1 downto 0);
+ signal INCREMENT : std_logic;
+ signal DECREMENT : std_logic;
+ signal TOGGLE : std_logic;
+ signal IS_EMPTY : std_logic;
+ signal ZERO : std_logic;
+ signal NEW_EMPTY : std_logic;
+ signal EMPTY_OUT : std_logic;
+ signal NOWRITE : std_logic;
+ signal CHANGED_VALUE : std_logic;
+ signal EMPTY_IF_READ : std_logic;
+ signal LOAD_ENABLE : std_logic;
+begin
+-- Storage registers
+
+
+BUILD: for I in 0 to RANK -1 generate
+
+LSB: if I = 0 generate
+COUNTER : COUNT_UNIT
+ port map( INCREMENT => INCREMENT,
+ DECREMENT => DECREMENT,
+ RESET => RESET,
+ CLOCK => CLOCK,
+ OUTPUT => READ_ADDRESS(I),
+ INCREMENT_CARRY => INC(I),
+ DECREMENT_CARRY => DEC(I));
+
+ end generate;
+
+OTHER_BITS: if I > 0 generate
+COUNTER : COUNT_UNIT
+ port map( INCREMENT => INC(I-1),
+ DECREMENT => DEC(I-1),
+ RESET => RESET,
+ CLOCK => CLOCK,
+ OUTPUT => READ_ADDRESS(I),
+ INCREMENT_CARRY => INC(I),
+ DECREMENT_CARRY => DEC(I));
+ end generate;
+
+MULTIPLEX: for Z in 0 to TWO_TO_N(I) - 1 generate
+OUTPUT_SELECT: process(READ_ADDRESS(RANK - I - 1),GET_OUTPUT(RANK - I -1))
+begin
+ if READ_ADDRESS(RANK - I - 1) = '1' then
+ GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z + 1);
+ else
+ GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z);
+ end if;
+end process OUTPUT_SELECT;
+end generate;
+
+STORAGE: if I = RANK - 1 generate
+BITS: for X in 0 to TWO_TO_N(RANK) - 1 generate
+STORE: ENABLEABLE_D_TYPE
+ port map (DATA_IN => NEWVAL(X),
+ ENABLE => LOAD_ENABLE,
+ CLK => CLOCK,
+ DATA_OUT => GET_OUTPUT(0)(X));
+MOST_RECENT: if X = 0 generate
+ NEWVAL(X) <= DATA_IN and not RESET;
+end generate;
+
+OLDER_DATA: if X > 0 generate
+ NEWVAL(X) <= GET_OUTPUT(0)(X-1) and not RESET;
+end generate;
+end generate;
+end generate;
+
+
+end generate;
+
+LOAD_ENABLE <= WRITE_ENABLE or RESET;
+INCREMENT <= WRITE_ENABLE and not (READ_ENABLE or EMPTY_OUT);
+DECREMENT <= READ_ENABLE and not (WRITE_ENABLE or ZERO);
+
+EMPTY_VALUE: D_TYPE
+ port map(D => IS_EMPTY,
+ CLOCK => CLOCK,
+ Q => EMPTY_OUT);
+
+IS_EMPTY <= NEW_EMPTY or RESET;
+
+SWITCH_EMPTY: process(TOGGLE,EMPTY_OUT,CHANGED_VALUE)
+begin
+ if(TOGGLE = '1') then
+ NEW_EMPTY <= CHANGED_VALUE;
+ else
+ NEW_EMPTY <= EMPTY_OUT;
+ end if;
+end process SWITCH_EMPTY;
+
+TOGGLE <= WRITE_ENABLE xor READ_ENABLE;
+CHANGED_VALUE <= EMPTY_IF_READ and NOWRITE;
+NOWRITE <= not WRITE_ENABLE;
+EMPTY_IF_READ <= ZERO or EMPTY_OUT;
+
+
+ZERO <= ZERO_VALUE(READ_ADDRESS);
+
+EMPTY <= EMPTY_OUT;
+
+DATA_OUT <= GET_OUTPUT(RANK)(0);
+
+
+
+end RTL;
FIFO.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: D_TYPE.vhd
===================================================================
--- D_TYPE.vhd (nonexistent)
+++ D_TYPE.vhd (revision 12)
@@ -0,0 +1,69 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity D_TYPE is
+ Port (
+ D : in std_logic;
+ CLOCK : in std_logic;
+ Q : out std_logic);
+end D_TYPE;
+
+architecture RTL of D_TYPE is
+begin
+FLIP_FLOP: process(CLOCK)
+begin
+ if CLOCK'event and CLOCK = '1' then
+ Q <= D;
+ end if;
+end process FLIP_FLOP;
+
+end RTL;
+
+configuration STANDARD of D_TYPE is
+for RTL end for;
+end configuration STANDARD;
\ No newline at end of file
D_TYPE.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: COUNT_UNIT.vhd
===================================================================
--- COUNT_UNIT.vhd (nonexistent)
+++ COUNT_UNIT.vhd (revision 12)
@@ -0,0 +1,92 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: COUNT_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNT_UNIT is
+ Port ( INCREMENT : in std_logic;
+ DECREMENT : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ OUTPUT : out std_logic;
+ INCREMENT_CARRY : out std_logic;
+ DECREMENT_CARRY : out std_logic);
+end COUNT_UNIT;
+
+architecture RTL of COUNT_UNIT is
+ component D_TYPE
+ port(D,CLOCK: in std_logic;
+ Q: out std_logic);
+ end component D_TYPE;
+ signal UPDATE: std_logic :='0';
+ signal TOGGLE: std_logic;
+ signal Q_VAL: std_logic;
+ signal INVERSE: std_logic;
+ signal NEWVAL : std_logic;
+begin
+
+-- combinatorial logic
+
+ TOGGLE <= INCREMENT xor DECREMENT;
+ INVERSE <= not Q_VAL;
+ OUTPUT <= Q_VAL;
+ INCREMENT_CARRY <= INCREMENT and not DECREMENT and Q_VAL;
+ DECREMENT_CARRY <= DECREMENT and not INCREMENT and INVERSE;
+ NEWVAL <= Q_VAL xor TOGGLE;
+ UPDATE <= NEWVAL and not RESET;
+
+
+
+
+
+-- The D_TYPE
+
+FLIP_FLOP: D_TYPE
+ port map(D => UPDATE,
+ CLOCK => CLOCK,
+ Q => Q_VAL);
+
+end RTL;
COUNT_UNIT.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ARITHMETIC_UNIT.vhd
===================================================================
--- ARITHMETIC_UNIT.vhd (nonexistent)
+++ ARITHMETIC_UNIT.vhd (revision 12)
@@ -0,0 +1,143 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: ARITHMETIC_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ARITHMETIC_UNIT is
+ Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
+ PROB : in std_logic_vector(9 downto 0);
+ LOW : in std_logic_vector(15 downto 0);
+ ENABLE : in std_logic;
+ RESET : in std_logic;
+ CLOCK : in std_logic;
+ DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
+ DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
+ RESULT_OUT0 : out std_logic_vector(15 downto 0);
+ RESULT_OUT1 : out std_logic_vector(15 downto 0);
+ DATA_LOAD : out std_logic :='1');
+end ARITHMETIC_UNIT;
+
+architecture RTL of ARITHMETIC_UNIT is
+ component D_TYPE
+ port(D,CLOCK: in std_logic;
+ Q: out std_logic);
+ end component D_TYPE;
+ signal LOW2 : std_logic_vector(16 downto 0);
+ signal PRODUCT : std_logic_vector (26 downto 0);
+ signal PRODUCT2 : std_logic_vector (16 downto 0);
+ signal RESULT : std_logic_vector (16 downto 0);
+ signal RESULT0 : std_logic_vector (15 downto 0);
+ signal DIFFERENCE1 : std_logic_vector (16 downto 0);
+ signal DIFFERENCE2 : std_logic_vector(16 downto 0);
+ signal DIFFERENCE3 : std_logic_vector(16 downto 0);
+ signal DIFFERENCE4 : std_logic_vector(16 downto 0);
+ signal DELAY1 : std_logic;
+ signal DELAY2 : std_logic;
+ signal CALCULATE : std_logic;
+begin
+
+-- The arithmetic
+ DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
+MULTIPLY : process (CLOCK, DIFFERENCE2, PROB)
+ begin
+ if CLOCK'event and CLOCK = '1' then
+ PRODUCT <= DIFFERENCE2 * PROB;
+ end if;
+ end process MULTIPLY;
+ PRODUCT2 <= PRODUCT(26 downto 10);
+ RESULT <= LOW2 + PRODUCT2;
+ RESULT_OUT1 <= RESULT(15 downto 0);
+ RESULT0 <= (RESULT - "00000000000000001");
+ RESULT_OUT0 <= RESULT0(15 downto 0);
+ DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
+ DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
+ DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
+
+
+
+
+-- Control logic
+ CALCULATE <= ENABLE and not RESET;
+ DATA_LOAD <= DELAY1 and DELAY2;
+
+-- Sequential control logic
+
+READ_DELAY: D_TYPE
+ port map(D => CALCULATE,
+ CLOCK => CLOCK,
+ Q => DELAY1);
+
+CHECK_DELAY: D_TYPE
+ port map(D => DELAY1,
+ CLOCK => CLOCK,
+ Q => DELAY2);
+
+DELAYS: for I in 0 to 15 generate
+
+DIFF_DELAY: D_TYPE
+ port map(D => DIFFERENCE(I),
+ CLOCK => CLOCK,
+ Q => DIFFERENCE1(I));
+
+LOW_DELAY: D_TYPE
+ port map(D => LOW(I),
+ CLOCK => CLOCK,
+ Q => LOW2(I));
+
+OUT_DELAY0: D_TYPE
+ port map(D => DIFFERENCE3(I),
+ CLOCK => CLOCK,
+ Q => DIFFERENCE_OUT0(I));
+
+
+end generate;
+
+LOW2(16) <= '0';
+DIFFERENCE1(16) <= '0';
+
+
+end RTL;
ARITHMETIC_UNIT.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: enableable_d_type.prj
===================================================================
--- enableable_d_type.prj (nonexistent)
+++ enableable_d_type.prj (revision 12)
@@ -0,0 +1,2 @@
+vhdl work D_TYPE.vhd
+vhdl work ENABLEABLE_D_TYPE.vhd
enableable_d_type.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: CONVERGENCE_CHECK.vhd
===================================================================
--- CONVERGENCE_CHECK.vhd (nonexistent)
+++ CONVERGENCE_CHECK.vhd (revision 12)
@@ -0,0 +1,82 @@
+-- ***** BEGIN LICENSE BLOCK *****
+--
+-- $Id: CONVERGENCE_CHECK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
+-- *
+-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
+-- *
+-- * The contents of this file are subject to the Mozilla Public License
+-- * Version 1.1 (the "License"); you may not use this file except in compliance
+-- * with the License. You may obtain a copy of the License at
+-- * http://www.mozilla.org/MPL/
+-- *
+-- * Software distributed under the License is distributed on an "AS IS" basis,
+-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+-- * the specific language governing rights and limitations under the License.
+-- *
+-- * The Original Code is BBC Research and Development code.
+-- *
+-- * The Initial Developer of the Original Code is the British Broadcasting
+-- * Corporation.
+-- * Portions created by the Initial Developer are Copyright (C) 2004.
+-- * All Rights Reserved.
+-- *
+-- * Contributor(s): Peter Bleackley (Original author)
+-- *
+-- * Alternatively, the contents of this file may be used under the terms of
+-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
+-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
+-- * the GPL or the LGPL are applicable instead of those above. If you wish to
+-- * allow use of your version of this file only under the terms of the either
+-- * the GPL or LGPL and not to allow others to use your version of this file
+-- * under the MPL, indicate your decision by deleting the provisions above
+-- * and replace them with the notice and other provisions required by the GPL
+-- * or LGPL. If you do not delete the provisions above, a recipient may use
+-- * your version of this file under the terms of any one of the MPL, the GPL
+-- * or the LGPL.
+-- * ***** END LICENSE BLOCK ***** */
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity CONVERGENCE_CHECK is
+ Port ( HIGH_MSB : in std_logic;
+ LOW_MSB : in std_logic;
+ HIGH_SECONDBIT : in std_logic;
+ LOW_SECONDBIT : in std_logic;
+ CHECK : in std_logic;
+ TRIGGER_OUTPUT : out std_logic;
+ TRIGGER_FOLLOW : out std_logic);
+end CONVERGENCE_CHECK;
+
+architecture RTL of CONVERGENCE_CHECK is
+ signal MSB_AND : std_logic;
+ signal MSB_NOR : std_logic;
+ signal MSB_EQ : std_logic;
+ signal MSB_XOR : std_logic;
+ signal INV : std_logic;
+ signal SECOND_BIT_01: std_logic;
+ signal STRADDLE: std_logic;
+begin
+
+ MSB_AND <= HIGH_MSB and LOW_MSB;
+ MSB_NOR <= HIGH_MSB nor LOW_MSB;
+ MSB_EQ <= MSB_AND or MSB_NOR;
+ MSB_XOR <= not MSB_EQ;
+
+ INV <= not HIGH_SECONDBIT;
+ SECOND_BIT_01 <= INV and LOW_SECONDBIT;
+ STRADDLE <= MSB_XOR and SECOND_BIT_01;
+
+ TRIGGER_OUTPUT <= CHECK and MSB_EQ;
+ TRIGGER_FOLLOW <= CHECK and STRADDLE;
+
+
+end RTL;
CONVERGENCE_CHECK.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: fifo.prj
===================================================================
--- fifo.prj (nonexistent)
+++ fifo.prj (revision 12)
@@ -0,0 +1,4 @@
+vhdl work D_TYPE.vhd
+vhdl work COUNT_UNIT.vhd
+vhdl work ENABLEABLE_D_TYPE.vhd
+vhdl work FIFO.vhd
fifo.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: d_type.prj
===================================================================
--- d_type.prj (nonexistent)
+++ d_type.prj (revision 12)
@@ -0,0 +1 @@
+vhdl work D_TYPE.vhd
d_type.prj
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property