URL
https://opencores.org/ocsvn/dirac/dirac/trunk
Subversion Repositories dirac
Compare Revisions
- This comparison shows the changes necessary to convert path
/dirac/tags/dirac_0_0_1_0/src/encoder
- from Rev 12 to Rev 3
- ↔ Reverse comparison
Rev 12 → Rev 3
/OUTPUT_UNIT.vhd
File deleted
OUTPUT_UNIT.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: arithmeticcoder.prj
===================================================================
--- arithmeticcoder.prj (revision 12)
+++ arithmeticcoder.prj (nonexistent)
@@ -1,12 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/FIFO.vhd
-vhdl work ../common/INPUT_CONTROL.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work LIMIT_REGISTER.vhd
-vhdl work ../common/ARITHMETIC_UNIT.vhd
-vhdl work ../common/CONVERGENCE_CHECK.vhd
-vhdl work FOLLOW_COUNTER.vhd
-vhdl work OUTPUT_UNIT.vhd
-vhdl work ARITHMETICCODER.vhd
arithmeticcoder.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: FOLLOW_COUNTER.vhd
===================================================================
--- FOLLOW_COUNTER.vhd (revision 12)
+++ FOLLOW_COUNTER.vhd (nonexistent)
@@ -1,170 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: FOLLOW_COUNTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity FOLLOW_COUNTER is
- Port ( INCREMENT : in std_logic;
- TEST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic);
-end FOLLOW_COUNTER;
-
-architecture RTL of FOLLOW_COUNTER is
- component COUNT_UNIT
- port(INCREMENT: in std_logic;
- DECREMENT: in std_logic;
- RESET : in std_logic;
- CLOCK: in std_logic;
- OUTPUT: out std_logic;
- INCREMENT_CARRY: out std_logic;
- DECREMENT_CARRY: out std_logic);
- end component COUNT_UNIT;
- signal A,B,C,D,E,F,G,H: std_logic;
- signal AB,CD,EF,GH: std_logic;
- signal AD,EH: std_logic;
- signal NONZERO: std_logic;
- signal INC0,INC1,INC2,INC3,INC4,INC5,INC6,INC7: std_logic;
- signal DEC0,DEC1,DEC2,DEC3,DEC4,DEC5,DEC6,DEC7: std_logic;
- signal DECREMENT: std_logic;
-begin
-
--- detect non-zero result
-
- AB <= A or B;
- CD <= C or D;
- EF <= E or F;
- GH <= G or H;
-
- AD <= AB or CD;
- EH <= EF or GH;
-
- NONZERO <= AD or EH;
-
--- Output
-
- OUTPUT <= DECREMENT;
-
--- Feedback
-
- DECREMENT <= TEST and NONZERO;
-
--- Sequential arithmetic
-
-COUNT0: COUNT_UNIT
- port map(INCREMENT => INCREMENT,
- DECREMENT => DECREMENT,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => A,
- INCREMENT_CARRY => INC0,
- DECREMENT_CARRY => DEC0);
-
-COUNT1: COUNT_UNIT
- port map(INCREMENT => INC0,
- DECREMENT => DEC0,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => B,
- INCREMENT_CARRY => INC1,
- DECREMENT_CARRY => DEC1);
-
-COUNT2: COUNT_UNIT
- port map(INCREMENT => INC1,
- DECREMENT => DEC1,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => C,
- INCREMENT_CARRY => INC2,
- DECREMENT_CARRY => DEC2);
-
-COUNT3: COUNT_UNIT
- port map(INCREMENT => INC2,
- DECREMENT => DEC2,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => D,
- INCREMENT_CARRY => INC3,
- DECREMENT_CARRY => DEC3);
-
-COUNT4: COUNT_UNIT
- port map(INCREMENT => INC3,
- DECREMENT => DEC3,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => E,
- INCREMENT_CARRY => INC4,
- DECREMENT_CARRY => DEC4);
-
-COUNT5: COUNT_UNIT
- port map(INCREMENT => INC4,
- DECREMENT => DEC4,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => F,
- INCREMENT_CARRY => INC5,
- DECREMENT_CARRY => DEC5);
-
-COUNT6: COUNT_UNIT
- port map(INCREMENT => INC5,
- DECREMENT => DEC5,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => G,
- INCREMENT_CARRY => INC6,
- DECREMENT_CARRY => DEC6);
-
-COUNT7: COUNT_UNIT
- port map(INCREMENT => INC6,
- DECREMENT => DEC6,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => H,
- INCREMENT_CARRY => INC7,
- DECREMENT_CARRY => DEC7);
-
-
-end RTL;
FOLLOW_COUNTER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: LIMIT_REGISTER.vhd
===================================================================
--- LIMIT_REGISTER.vhd (revision 12)
+++ LIMIT_REGISTER.vhd (nonexistent)
@@ -1,272 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: LIMIT_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity LIMIT_REGISTER is
- generic(CONST : std_logic := '1');
- Port ( LOAD : in std_logic_vector(15 downto 0);
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
-end entity LIMIT_REGISTER;
-
-architecture RTL of LIMIT_REGISTER is
- component STORE_BLOCK
- port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic;
- OUTPUT: out std_logic);
- end component STORE_BLOCK;
- signal SHIFT_LSBS: std_logic;
- signal SET_RESET: std_logic;
- signal ENABLE_MSB: std_logic;
- signal ENABLE_LSBS: std_logic;
- signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic;
- signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic;
-begin
-
--- control logic
- SET_RESET <= SET_VALUE or RESET;
- ENABLE_MSB <= SET_RESET or SHIFT_ALL;
- SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
- ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
-
--- outputs
-
- OUTPUT(0) <= Q0;
- OUTPUT(1) <= Q1;
- OUTPUT(2) <= Q2;
- OUTPUT(3) <= Q3;
- OUTPUT(4) <= Q4;
- OUTPUT(5) <= Q5;
- OUTPUT(6) <= Q6;
- OUTPUT(7) <= Q7;
- OUTPUT(8) <= Q8;
- OUTPUT(9) <= Q9;
- OUTPUT(10) <= Q10;
- OUTPUT(11) <= Q11;
- OUTPUT(12) <= Q12;
- OUTPUT(13) <= Q13;
- OUTPUT(14) <= Q14;
- OUTPUT(15) <= Q15;
-
--- initialisation
-
-INIT: process(RESET,LOAD)
-begin
- if RESET = '1' then
- D0 <= CONST;
- D1 <= CONST;
- D2 <= CONST;
- D3 <= CONST;
- D4 <= CONST;
- D5 <= CONST;
- D6 <= CONST;
- D7 <= CONST;
- D8 <= CONST;
- D9 <= CONST;
- D10 <= CONST;
- D11 <= CONST;
- D12 <= CONST;
- D13 <= CONST;
- D14 <= CONST;
- D15 <= CONST;
- else
- D0 <= LOAD(0);
- D1 <= LOAD(1);
- D2 <= LOAD(2);
- D3 <= LOAD(3);
- D4 <= LOAD(4);
- D5 <= LOAD(5);
- D6 <= LOAD(6);
- D7 <= LOAD(7);
- D8 <= LOAD(8);
- D9 <= LOAD(9);
- D10 <= LOAD(10);
- D11 <= LOAD(11);
- D12 <= LOAD(12);
- D13 <= LOAD(13);
- D14 <= LOAD(14);
- D15 <= LOAD(15);
- end if;
-end process INIT;
-
--- storage
-
- STORE0: STORE_BLOCK
- port map(LOAD_IN => D0,
- SHIFT_IN => CONST,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q0);
-
- STORE1: STORE_BLOCK
- port map(LOAD_IN => D1,
- SHIFT_IN => Q0,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q1);
-
- STORE2: STORE_BLOCK
- port map(LOAD_IN => D2,
- SHIFT_IN => Q1,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q2);
-
- STORE3: STORE_BLOCK
- port map(LOAD_IN => D3,
- SHIFT_IN => Q2,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q3);
-
- STORE4: STORE_BLOCK
- port map(LOAD_IN => D4,
- SHIFT_IN => Q3,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q4);
-
- STORE5: STORE_BLOCK
- port map(LOAD_IN => D5,
- SHIFT_IN => Q4,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q5);
-
- STORE6: STORE_BLOCK
- port map(LOAD_IN => D6,
- SHIFT_IN => Q5,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q6);
-
- STORE7: STORE_BLOCK
- port map(LOAD_IN => D7,
- SHIFT_IN => Q6,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q7);
-
- STORE8: STORE_BLOCK
- port map(LOAD_IN => D8,
- SHIFT_IN => Q7,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q8);
-
- STORE9: STORE_BLOCK
- port map(LOAD_IN => D9,
- SHIFT_IN => Q8,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q9);
-
- STORE10: STORE_BLOCK
- port map(LOAD_IN => D10,
- SHIFT_IN => Q9,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q10);
-
- STORE11: STORE_BLOCK
- port map(LOAD_IN => D11,
- SHIFT_IN => Q10,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q11);
-
- STORE12: STORE_BLOCK
- port map(LOAD_IN => D12,
- SHIFT_IN => Q11,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q12);
-
- STORE13: STORE_BLOCK
- port map(LOAD_IN => D13,
- SHIFT_IN => Q12,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q13);
-
- STORE14: STORE_BLOCK
- port map(LOAD_IN => D14,
- SHIFT_IN => Q13,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q14);
-
- STORE15: STORE_BLOCK
- port map(LOAD_IN => D15,
- SHIFT_IN => Q14,
- SHIFT => SHIFT_ALL,
- ENABLE => ENABLE_MSB,
- CLK => CLOCK,
- OUTPUT => Q15);
-
-
-
-end architecture RTL;
-
LIMIT_REGISTER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: ARITHMETICCODER.vhd
===================================================================
--- ARITHMETICCODER.vhd (revision 12)
+++ ARITHMETICCODER.vhd (nonexistent)
@@ -1,286 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: ARITHMETICCODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ARITHMETICCODER is
- generic (PROB : std_logic_vector (9 downto 0) := "1010101010");
- Port ( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
-end ARITHMETICCODER;
-
-architecture RTL of ARITHMETICCODER is
- component D_TYPE
- port(D: in std_logic;
- CLOCK: in std_logic;
- Q: out std_logic);
- end component D_TYPE;
- component INPUT_CONTROL
- port( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- BUFFER_CONTROL : in std_logic;
- DEMAND : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
- end component INPUT_CONTROL;
- component LIMIT_REGISTER
- generic(CONST: std_logic);
- port( LOAD : in std_logic_vector(15 downto 0);
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
- end component LIMIT_REGISTER;
- component FOLLOW_COUNTER
- port ( INCREMENT : in std_logic;
- TEST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic);
- end component FOLLOW_COUNTER;
- component CONVERGENCE_CHECK
- port ( HIGH_MSB : in std_logic;
- LOW_MSB : in std_logic;
- HIGH_SECONDBIT : in std_logic;
- LOW_SECONDBIT : in std_logic;
- CHECK : in std_logic;
- TRIGGER_OUTPUT : out std_logic;
- TRIGGER_FOLLOW : out std_logic);
- end component CONVERGENCE_CHECK;
- component ARITHMETIC_UNIT
- port ( DIFFERENCE : in std_logic_vector(15 downto 0);
- PROB : in std_logic_vector(9 downto 0);
- LOW : in std_logic_vector(15 downto 0);
- ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
- DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
- RESULT_OUT0 : out std_logic_vector(15 downto 0);
- RESULT_OUT1 : out std_logic_vector(15 downto 0);
- DATA_LOAD : out std_logic);
- end component ARITHMETIC_UNIT;
- component OUTPUT_UNIT
- port ( ENABLE : in std_logic;
- DATA : in std_logic;
- FOLLOW : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic;
- FOLLOW_COUNTER_TEST : out std_logic;
- SHIFT : out std_logic);
- end component OUTPUT_UNIT;
- signal HIGH_SET : std_logic;
- signal LOW_SET : std_logic;
- signal SHIFT_ALL : std_logic;
- signal DIFFERENCE_SHIFT_ALL : std_logic;
- signal SHIFT_MOST : std_logic;
- signal ZERO_INPUT : std_logic;
- signal ARITHMETIC_UNIT_ENABLE : std_logic;
- signal ARITHMETIC_UNIT_DATA_LOAD : std_logic;
- signal CONVERGENCE_TEST : std_logic;
- signal TRIGGER_OUTPUT : std_logic;
- signal FOLLOW_COUNTER_TEST : std_logic;
- signal FOLLOW: std_logic;
- signal DATA_LOAD: std_logic;
- signal OUTPUT_ACTIVE : std_logic;
- signal CHECK : std_logic;
- signal DELAYED_CHECK : std_logic;
- signal DATA_AVAILABLE : std_logic;
- signal BUFFERED_DATA : std_logic;
- signal BUFFER_INPUT : std_logic;
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
- signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
- signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
- signal HIGH_OUT : std_logic_vector (15 downto 0);
- signal LOW_OUT : std_logic_vector (15 downto 0);
-
-begin
--- input buffering
-INBUFFER: INPUT_CONTROL
- port map(ENABLE => ENABLE,
- DATA_IN => DATA_IN,
- BUFFER_CONTROL => BUFFER_INPUT,
- DEMAND => ARITHMETIC_UNIT_DATA_LOAD,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => DATA_AVAILABLE,
- DATA_OUT => BUFFERED_DATA);
-
--- Specify the registers
-HIGH: LIMIT_REGISTER
- generic map(CONST => '1')
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
- SET_VALUE => HIGH_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => HIGH_OUT);
-
-DIFFERENCE: LIMIT_REGISTER
- generic map(CONST => '1')
- port map( LOAD => DIFFERENCE_IN,
- SET_VALUE => DATA_LOAD,
- SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
- SHIFT_MOST => '0',
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => DIFFERENCE_OUT);
-
-LOW: LIMIT_REGISTER
- generic map(CONST => '0')
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
- SET_VALUE => LOW_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => LOW_OUT);
-
--- The arithmetic
-
-ARITH: ARITHMETIC_UNIT
- port map(DIFFERENCE => DIFFERENCE_OUT,
- PROB => PROB,
- LOW => LOW_OUT,
- ENABLE => ARITHMETIC_UNIT_ENABLE,
- RESET => RESET,
- CLOCK => CLOCK,
- DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
- DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
- RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
- RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
- DATA_LOAD => ARITHMETIC_UNIT_DATA_LOAD);
-
---The convergence checks
-
-CONVERGE: CONVERGENCE_CHECK
- port map(HIGH_MSB => HIGH_OUT(15),
- LOW_MSB => LOW_OUT(15),
- HIGH_SECONDBIT => HIGH_OUT(14),
- LOW_SECONDBIT => LOW_OUT(14),
- CHECK => CONVERGENCE_TEST,
- TRIGGER_OUTPUT => TRIGGER_OUTPUT,
- TRIGGER_FOLLOW => SHIFT_MOST);
-
---The Follow Counter
-
-FC: FOLLOW_COUNTER
- port map( INCREMENT => SHIFT_MOST,
- TEST => FOLLOW_COUNTER_TEST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => FOLLOW);
-
---The output unit
-
-OUTPUT: OUTPUT_UNIT
- port map(ENABLE => TRIGGER_OUTPUT,
- DATA => HIGH_OUT(15),
- FOLLOW => FOLLOW,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => OUTPUT_ACTIVE,
- DATA_OUT => DATA_OUT,
- FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST,
- SHIFT => SHIFT_ALL);
-
- SENDING <= OUTPUT_ACTIVE;
-
--- Input logic
-
- DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD;
- HIGH_SET <= ZERO_INPUT and DATA_LOAD;
- ZERO_INPUT <= not BUFFERED_DATA;
- LOW_SET <= BUFFERED_DATA and DATA_LOAD;
-
--- Control logic for DIFFERENCE register
-
- DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
-
--- Control logic for convergence check
-
- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD;
-
-CONVERGENCE_TEST_DELAY: D_TYPE
- port map( D => CHECK,
- CLOCK => CLOCK,
- Q => DELAYED_CHECK);
-
- CONVERGENCE_TEST <= DELAYED_CHECK or FOLLOW_COUNTER_TEST;
-
--- Control logic for arithmetic unit
-
- ARITHMETIC_UNIT_ENABLE <= not(OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL or DATA_LOAD);
-
--- Control Logic for input control
-
- BUFFER_INPUT <= OUTPUT_ACTIVE or not ARITHMETIC_UNIT_DATA_LOAD;
-
--- Select the new difference value
-
-NEWDIFF : process(BUFFERED_DATA,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
- begin
- if(BUFFERED_DATA = '1') then
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
- else
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
- end if;
- end process NEWDIFF;
-
-end RTL;
ARITHMETICCODER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: output_unit.prj
===================================================================
--- output_unit.prj (revision 12)
+++ output_unit.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work OUTPUT_UNIT.vhd
output_unit.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: follow_counter.prj
===================================================================
--- follow_counter.prj (revision 12)
+++ follow_counter.prj (nonexistent)
@@ -1,3 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/FOLLOW_COUNTER.vhd
follow_counter.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: limit_register.prj
===================================================================
--- limit_register.prj (revision 12)
+++ limit_register.prj (nonexistent)
@@ -1,4 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work REGISTER.vhd
limit_register.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property