URL
https://opencores.org/ocsvn/dirac/dirac/trunk
Subversion Repositories dirac
Compare Revisions
- This comparison shows the changes necessary to convert path
/dirac/tags/dirac_0_0_1_0/src
- from Rev 12 to Rev 3
- ↔ Reverse comparison
Rev 12 → Rev 3
/encoder/OUTPUT_UNIT.vhd
File deleted
encoder/OUTPUT_UNIT.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/arithmeticcoder.prj
===================================================================
--- encoder/arithmeticcoder.prj (revision 12)
+++ encoder/arithmeticcoder.prj (nonexistent)
@@ -1,12 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/FIFO.vhd
-vhdl work ../common/INPUT_CONTROL.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work LIMIT_REGISTER.vhd
-vhdl work ../common/ARITHMETIC_UNIT.vhd
-vhdl work ../common/CONVERGENCE_CHECK.vhd
-vhdl work FOLLOW_COUNTER.vhd
-vhdl work OUTPUT_UNIT.vhd
-vhdl work ARITHMETICCODER.vhd
encoder/arithmeticcoder.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/FOLLOW_COUNTER.vhd
===================================================================
--- encoder/FOLLOW_COUNTER.vhd (revision 12)
+++ encoder/FOLLOW_COUNTER.vhd (nonexistent)
@@ -1,170 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: FOLLOW_COUNTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity FOLLOW_COUNTER is
- Port ( INCREMENT : in std_logic;
- TEST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic);
-end FOLLOW_COUNTER;
-
-architecture RTL of FOLLOW_COUNTER is
- component COUNT_UNIT
- port(INCREMENT: in std_logic;
- DECREMENT: in std_logic;
- RESET : in std_logic;
- CLOCK: in std_logic;
- OUTPUT: out std_logic;
- INCREMENT_CARRY: out std_logic;
- DECREMENT_CARRY: out std_logic);
- end component COUNT_UNIT;
- signal A,B,C,D,E,F,G,H: std_logic;
- signal AB,CD,EF,GH: std_logic;
- signal AD,EH: std_logic;
- signal NONZERO: std_logic;
- signal INC0,INC1,INC2,INC3,INC4,INC5,INC6,INC7: std_logic;
- signal DEC0,DEC1,DEC2,DEC3,DEC4,DEC5,DEC6,DEC7: std_logic;
- signal DECREMENT: std_logic;
-begin
-
--- detect non-zero result
-
- AB <= A or B;
- CD <= C or D;
- EF <= E or F;
- GH <= G or H;
-
- AD <= AB or CD;
- EH <= EF or GH;
-
- NONZERO <= AD or EH;
-
--- Output
-
- OUTPUT <= DECREMENT;
-
--- Feedback
-
- DECREMENT <= TEST and NONZERO;
-
--- Sequential arithmetic
-
-COUNT0: COUNT_UNIT
- port map(INCREMENT => INCREMENT,
- DECREMENT => DECREMENT,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => A,
- INCREMENT_CARRY => INC0,
- DECREMENT_CARRY => DEC0);
-
-COUNT1: COUNT_UNIT
- port map(INCREMENT => INC0,
- DECREMENT => DEC0,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => B,
- INCREMENT_CARRY => INC1,
- DECREMENT_CARRY => DEC1);
-
-COUNT2: COUNT_UNIT
- port map(INCREMENT => INC1,
- DECREMENT => DEC1,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => C,
- INCREMENT_CARRY => INC2,
- DECREMENT_CARRY => DEC2);
-
-COUNT3: COUNT_UNIT
- port map(INCREMENT => INC2,
- DECREMENT => DEC2,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => D,
- INCREMENT_CARRY => INC3,
- DECREMENT_CARRY => DEC3);
-
-COUNT4: COUNT_UNIT
- port map(INCREMENT => INC3,
- DECREMENT => DEC3,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => E,
- INCREMENT_CARRY => INC4,
- DECREMENT_CARRY => DEC4);
-
-COUNT5: COUNT_UNIT
- port map(INCREMENT => INC4,
- DECREMENT => DEC4,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => F,
- INCREMENT_CARRY => INC5,
- DECREMENT_CARRY => DEC5);
-
-COUNT6: COUNT_UNIT
- port map(INCREMENT => INC5,
- DECREMENT => DEC5,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => G,
- INCREMENT_CARRY => INC6,
- DECREMENT_CARRY => DEC6);
-
-COUNT7: COUNT_UNIT
- port map(INCREMENT => INC6,
- DECREMENT => DEC6,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => H,
- INCREMENT_CARRY => INC7,
- DECREMENT_CARRY => DEC7);
-
-
-end RTL;
encoder/FOLLOW_COUNTER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/LIMIT_REGISTER.vhd
===================================================================
--- encoder/LIMIT_REGISTER.vhd (revision 12)
+++ encoder/LIMIT_REGISTER.vhd (nonexistent)
@@ -1,272 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: LIMIT_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity LIMIT_REGISTER is
- generic(CONST : std_logic := '1');
- Port ( LOAD : in std_logic_vector(15 downto 0);
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
-end entity LIMIT_REGISTER;
-
-architecture RTL of LIMIT_REGISTER is
- component STORE_BLOCK
- port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic;
- OUTPUT: out std_logic);
- end component STORE_BLOCK;
- signal SHIFT_LSBS: std_logic;
- signal SET_RESET: std_logic;
- signal ENABLE_MSB: std_logic;
- signal ENABLE_LSBS: std_logic;
- signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic;
- signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic;
-begin
-
--- control logic
- SET_RESET <= SET_VALUE or RESET;
- ENABLE_MSB <= SET_RESET or SHIFT_ALL;
- SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
- ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
-
--- outputs
-
- OUTPUT(0) <= Q0;
- OUTPUT(1) <= Q1;
- OUTPUT(2) <= Q2;
- OUTPUT(3) <= Q3;
- OUTPUT(4) <= Q4;
- OUTPUT(5) <= Q5;
- OUTPUT(6) <= Q6;
- OUTPUT(7) <= Q7;
- OUTPUT(8) <= Q8;
- OUTPUT(9) <= Q9;
- OUTPUT(10) <= Q10;
- OUTPUT(11) <= Q11;
- OUTPUT(12) <= Q12;
- OUTPUT(13) <= Q13;
- OUTPUT(14) <= Q14;
- OUTPUT(15) <= Q15;
-
--- initialisation
-
-INIT: process(RESET,LOAD)
-begin
- if RESET = '1' then
- D0 <= CONST;
- D1 <= CONST;
- D2 <= CONST;
- D3 <= CONST;
- D4 <= CONST;
- D5 <= CONST;
- D6 <= CONST;
- D7 <= CONST;
- D8 <= CONST;
- D9 <= CONST;
- D10 <= CONST;
- D11 <= CONST;
- D12 <= CONST;
- D13 <= CONST;
- D14 <= CONST;
- D15 <= CONST;
- else
- D0 <= LOAD(0);
- D1 <= LOAD(1);
- D2 <= LOAD(2);
- D3 <= LOAD(3);
- D4 <= LOAD(4);
- D5 <= LOAD(5);
- D6 <= LOAD(6);
- D7 <= LOAD(7);
- D8 <= LOAD(8);
- D9 <= LOAD(9);
- D10 <= LOAD(10);
- D11 <= LOAD(11);
- D12 <= LOAD(12);
- D13 <= LOAD(13);
- D14 <= LOAD(14);
- D15 <= LOAD(15);
- end if;
-end process INIT;
-
--- storage
-
- STORE0: STORE_BLOCK
- port map(LOAD_IN => D0,
- SHIFT_IN => CONST,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q0);
-
- STORE1: STORE_BLOCK
- port map(LOAD_IN => D1,
- SHIFT_IN => Q0,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q1);
-
- STORE2: STORE_BLOCK
- port map(LOAD_IN => D2,
- SHIFT_IN => Q1,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q2);
-
- STORE3: STORE_BLOCK
- port map(LOAD_IN => D3,
- SHIFT_IN => Q2,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q3);
-
- STORE4: STORE_BLOCK
- port map(LOAD_IN => D4,
- SHIFT_IN => Q3,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q4);
-
- STORE5: STORE_BLOCK
- port map(LOAD_IN => D5,
- SHIFT_IN => Q4,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q5);
-
- STORE6: STORE_BLOCK
- port map(LOAD_IN => D6,
- SHIFT_IN => Q5,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q6);
-
- STORE7: STORE_BLOCK
- port map(LOAD_IN => D7,
- SHIFT_IN => Q6,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q7);
-
- STORE8: STORE_BLOCK
- port map(LOAD_IN => D8,
- SHIFT_IN => Q7,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q8);
-
- STORE9: STORE_BLOCK
- port map(LOAD_IN => D9,
- SHIFT_IN => Q8,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q9);
-
- STORE10: STORE_BLOCK
- port map(LOAD_IN => D10,
- SHIFT_IN => Q9,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q10);
-
- STORE11: STORE_BLOCK
- port map(LOAD_IN => D11,
- SHIFT_IN => Q10,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q11);
-
- STORE12: STORE_BLOCK
- port map(LOAD_IN => D12,
- SHIFT_IN => Q11,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q12);
-
- STORE13: STORE_BLOCK
- port map(LOAD_IN => D13,
- SHIFT_IN => Q12,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q13);
-
- STORE14: STORE_BLOCK
- port map(LOAD_IN => D14,
- SHIFT_IN => Q13,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q14);
-
- STORE15: STORE_BLOCK
- port map(LOAD_IN => D15,
- SHIFT_IN => Q14,
- SHIFT => SHIFT_ALL,
- ENABLE => ENABLE_MSB,
- CLK => CLOCK,
- OUTPUT => Q15);
-
-
-
-end architecture RTL;
-
encoder/LIMIT_REGISTER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/ARITHMETICCODER.vhd
===================================================================
--- encoder/ARITHMETICCODER.vhd (revision 12)
+++ encoder/ARITHMETICCODER.vhd (nonexistent)
@@ -1,286 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: ARITHMETICCODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ARITHMETICCODER is
- generic (PROB : std_logic_vector (9 downto 0) := "1010101010");
- Port ( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
-end ARITHMETICCODER;
-
-architecture RTL of ARITHMETICCODER is
- component D_TYPE
- port(D: in std_logic;
- CLOCK: in std_logic;
- Q: out std_logic);
- end component D_TYPE;
- component INPUT_CONTROL
- port( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- BUFFER_CONTROL : in std_logic;
- DEMAND : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
- end component INPUT_CONTROL;
- component LIMIT_REGISTER
- generic(CONST: std_logic);
- port( LOAD : in std_logic_vector(15 downto 0);
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
- end component LIMIT_REGISTER;
- component FOLLOW_COUNTER
- port ( INCREMENT : in std_logic;
- TEST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic);
- end component FOLLOW_COUNTER;
- component CONVERGENCE_CHECK
- port ( HIGH_MSB : in std_logic;
- LOW_MSB : in std_logic;
- HIGH_SECONDBIT : in std_logic;
- LOW_SECONDBIT : in std_logic;
- CHECK : in std_logic;
- TRIGGER_OUTPUT : out std_logic;
- TRIGGER_FOLLOW : out std_logic);
- end component CONVERGENCE_CHECK;
- component ARITHMETIC_UNIT
- port ( DIFFERENCE : in std_logic_vector(15 downto 0);
- PROB : in std_logic_vector(9 downto 0);
- LOW : in std_logic_vector(15 downto 0);
- ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
- DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
- RESULT_OUT0 : out std_logic_vector(15 downto 0);
- RESULT_OUT1 : out std_logic_vector(15 downto 0);
- DATA_LOAD : out std_logic);
- end component ARITHMETIC_UNIT;
- component OUTPUT_UNIT
- port ( ENABLE : in std_logic;
- DATA : in std_logic;
- FOLLOW : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic;
- FOLLOW_COUNTER_TEST : out std_logic;
- SHIFT : out std_logic);
- end component OUTPUT_UNIT;
- signal HIGH_SET : std_logic;
- signal LOW_SET : std_logic;
- signal SHIFT_ALL : std_logic;
- signal DIFFERENCE_SHIFT_ALL : std_logic;
- signal SHIFT_MOST : std_logic;
- signal ZERO_INPUT : std_logic;
- signal ARITHMETIC_UNIT_ENABLE : std_logic;
- signal ARITHMETIC_UNIT_DATA_LOAD : std_logic;
- signal CONVERGENCE_TEST : std_logic;
- signal TRIGGER_OUTPUT : std_logic;
- signal FOLLOW_COUNTER_TEST : std_logic;
- signal FOLLOW: std_logic;
- signal DATA_LOAD: std_logic;
- signal OUTPUT_ACTIVE : std_logic;
- signal CHECK : std_logic;
- signal DELAYED_CHECK : std_logic;
- signal DATA_AVAILABLE : std_logic;
- signal BUFFERED_DATA : std_logic;
- signal BUFFER_INPUT : std_logic;
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
- signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
- signal DIFFERENCE_OUT : std_logic_vector (15 downto 0);
- signal HIGH_OUT : std_logic_vector (15 downto 0);
- signal LOW_OUT : std_logic_vector (15 downto 0);
-
-begin
--- input buffering
-INBUFFER: INPUT_CONTROL
- port map(ENABLE => ENABLE,
- DATA_IN => DATA_IN,
- BUFFER_CONTROL => BUFFER_INPUT,
- DEMAND => ARITHMETIC_UNIT_DATA_LOAD,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => DATA_AVAILABLE,
- DATA_OUT => BUFFERED_DATA);
-
--- Specify the registers
-HIGH: LIMIT_REGISTER
- generic map(CONST => '1')
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
- SET_VALUE => HIGH_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => HIGH_OUT);
-
-DIFFERENCE: LIMIT_REGISTER
- generic map(CONST => '1')
- port map( LOAD => DIFFERENCE_IN,
- SET_VALUE => DATA_LOAD,
- SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
- SHIFT_MOST => '0',
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => DIFFERENCE_OUT);
-
-LOW: LIMIT_REGISTER
- generic map(CONST => '0')
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
- SET_VALUE => LOW_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => LOW_OUT);
-
--- The arithmetic
-
-ARITH: ARITHMETIC_UNIT
- port map(DIFFERENCE => DIFFERENCE_OUT,
- PROB => PROB,
- LOW => LOW_OUT,
- ENABLE => ARITHMETIC_UNIT_ENABLE,
- RESET => RESET,
- CLOCK => CLOCK,
- DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
- DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
- RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
- RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
- DATA_LOAD => ARITHMETIC_UNIT_DATA_LOAD);
-
---The convergence checks
-
-CONVERGE: CONVERGENCE_CHECK
- port map(HIGH_MSB => HIGH_OUT(15),
- LOW_MSB => LOW_OUT(15),
- HIGH_SECONDBIT => HIGH_OUT(14),
- LOW_SECONDBIT => LOW_OUT(14),
- CHECK => CONVERGENCE_TEST,
- TRIGGER_OUTPUT => TRIGGER_OUTPUT,
- TRIGGER_FOLLOW => SHIFT_MOST);
-
---The Follow Counter
-
-FC: FOLLOW_COUNTER
- port map( INCREMENT => SHIFT_MOST,
- TEST => FOLLOW_COUNTER_TEST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => FOLLOW);
-
---The output unit
-
-OUTPUT: OUTPUT_UNIT
- port map(ENABLE => TRIGGER_OUTPUT,
- DATA => HIGH_OUT(15),
- FOLLOW => FOLLOW,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => OUTPUT_ACTIVE,
- DATA_OUT => DATA_OUT,
- FOLLOW_COUNTER_TEST => FOLLOW_COUNTER_TEST,
- SHIFT => SHIFT_ALL);
-
- SENDING <= OUTPUT_ACTIVE;
-
--- Input logic
-
- DATA_LOAD <= DATA_AVAILABLE and ARITHMETIC_UNIT_DATA_LOAD;
- HIGH_SET <= ZERO_INPUT and DATA_LOAD;
- ZERO_INPUT <= not BUFFERED_DATA;
- LOW_SET <= BUFFERED_DATA and DATA_LOAD;
-
--- Control logic for DIFFERENCE register
-
- DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
-
--- Control logic for convergence check
-
- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD;
-
-CONVERGENCE_TEST_DELAY: D_TYPE
- port map( D => CHECK,
- CLOCK => CLOCK,
- Q => DELAYED_CHECK);
-
- CONVERGENCE_TEST <= DELAYED_CHECK or FOLLOW_COUNTER_TEST;
-
--- Control logic for arithmetic unit
-
- ARITHMETIC_UNIT_ENABLE <= not(OUTPUT_ACTIVE or DIFFERENCE_SHIFT_ALL or DATA_LOAD);
-
--- Control Logic for input control
-
- BUFFER_INPUT <= OUTPUT_ACTIVE or not ARITHMETIC_UNIT_DATA_LOAD;
-
--- Select the new difference value
-
-NEWDIFF : process(BUFFERED_DATA,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
- begin
- if(BUFFERED_DATA = '1') then
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
- else
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
- end if;
- end process NEWDIFF;
-
-end RTL;
encoder/ARITHMETICCODER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/output_unit.prj
===================================================================
--- encoder/output_unit.prj (revision 12)
+++ encoder/output_unit.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work OUTPUT_UNIT.vhd
encoder/output_unit.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/follow_counter.prj
===================================================================
--- encoder/follow_counter.prj (revision 12)
+++ encoder/follow_counter.prj (nonexistent)
@@ -1,3 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/FOLLOW_COUNTER.vhd
encoder/follow_counter.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: encoder/limit_register.prj
===================================================================
--- encoder/limit_register.prj (revision 12)
+++ encoder/limit_register.prj (nonexistent)
@@ -1,4 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work REGISTER.vhd
encoder/limit_register.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: testbench/ArithmeticCoderTestbench.prj
===================================================================
--- testbench/ArithmeticCoderTestbench.prj (revision 12)
+++ testbench/ArithmeticCoderTestbench.prj (nonexistent)
@@ -1,16 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/FIFO.vhd
-vhdl work ../common/INPUT_CONTROL.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work ../encoder/LIMIT_REGISTER.vhd
-vhdl work ../common/ARITHMETIC_UNIT.vhd
-vhdl work ../common/CONVERGENCE_CHECK.vhd
-vhdl work ../encoder/FOLLOW_COUNTER.vhd
-vhdl work ../encoder/OUTPUT_UNIT.vhd
-vhdl work ../encoder.ARITHMETICCODER.vhd
-vhdl work ../decoder/STORAGE_REGISTER.vhd
-vhdl work ../decoder/SYMBOL_DETECTOR.vhd
-vhdl work ../decoder/ARITHMETICDECODER.vhd
-vhdl work ArithmeticCoderTestbench.vhd
\ No newline at end of file
testbench/ArithmeticCoderTestbench.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: testbench/raw_data
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: testbench/raw_data
===================================================================
--- testbench/raw_data (revision 12)
+++ testbench/raw_data (nonexistent)
testbench/raw_data
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: testbench/ArithmeticCoderTestbench.vhd
===================================================================
--- testbench/ArithmeticCoderTestbench.vhd (revision 12)
+++ testbench/ArithmeticCoderTestbench.vhd (nonexistent)
@@ -1,151 +0,0 @@
-
--- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-use IEEE.std_logic_textio.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use STD.textio.all;
-
-ENTITY arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
-END arithmeticcoder_ArithmeticCoderTestbench_vhd_tb;
-
-ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
-
- COMPONENT arithmeticcoder
- generic(
- PROB : std_logic_vector (9 downto 0));
- PORT(
- ENABLE : IN std_logic;
- DATA_IN : IN std_logic;
- CONTEXT_ENABLE : in std_logic;
- CONTEXT_IN : in std_logic_vector (5 downto 0);
- RESET : IN std_logic;
- CLOCK : IN std_logic;
- SENDING : OUT std_logic;
- DATA_OUT : OUT std_logic
- );
- END COMPONENT;
- component ARITHMETICDECODER
- generic(
- PROB : std_logic_vector (9 downto 0));
- port (ENABLE : in std_logic;
- DATA_IN : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
- end component ARITHMETICDECODER;
-
- SIGNAL ENABLE : std_logic;
- SIGNAL DATA_IN : std_logic := '0';
- SIGNAL RESET : std_logic;
- SIGNAL CLOCK : std_logic := '0';
- SIGNAL SENDING : std_logic;
- SIGNAL DATA_OUT : std_logic;
- signal TRANSMIT : std_logic;
- signal DATA_TRANSFER : std_logic;
- constant PERIOD : time := 10 ns;
- signal CONTEXT_ENABLE : std_logic;
- signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
- file TESTDATA : text is in "";
- file RESULTS : text is out "results";
-
-BEGIN
-
- uut: arithmeticcoder
- generic map(
- PROB => "1110010000")
- PORT MAP(
- ENABLE => ENABLE,
- DATA_IN => DATA_IN,
- CONTEXT_ENABLE => CONTEXT_ENABLE,
- CONTEXT_IN => CONTEXT,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => TRANSMIT,
- DATA_OUT => DATA_TRANSFER
- );
-
- CLOCK <= not CLOCK after PERIOD/2;
-
- DECODER: ARITHMETICDECODER
- generic map(
- PROB => "1110010000")
- port map( ENABLE => TRANSMIT,
- DATA_IN => DATA_TRANSFER,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => SENDING,
- DATA_OUT => DATA_OUT);
- --*** Test Bench - User Defined Section ***
- tb : PROCESS
- variable GETLINE : line;
- variable INDATA : std_logic;
- BEGIN
- for COUNT in 0 to 4194307 loop
- wait until CLOCK'event and CLOCK = '1';
- if COUNT = 0 then
- RESET <= '1';
- ENABLE <= '0';
- DATA_IN <= '0';
- elsif COUNT = 1 then
- RESET <= '0';
-
- elsif (COUNT - 2) mod 4 = 0 then
- if (COUNT < 4194307) then
- if (COUNT - 2) mod 128 = 0 then
- readline(TESTDATA,GETLINE);
- end if;
- read(GETLINE,INDATA);
- DATA_IN <= INDATA;
- ENABLE <= '1';
- else
- DATA_IN <= '1';
- ENABLE <= '1';
- end if;
-
- elsif COUNT < 4194307 then
- ENABLE <= '0';
- else
- wait; -- will wait forever
- end if;
- end loop;
- END PROCESS;
-
- OUTPUT : process
- variable OUTLINE : line;
- begin
- for WRITTEN in 0 to 1048576 loop
- wait until CLOCK'event and CLOCK = '1' and SENDING = '1';
- if WRITTEN = 1048576 then
- report "Process Complete" severity failure;
- wait;
- else
- write(OUTLINE,DATA_OUT);
- if (WRITTEN mod 32) = 31 then
- writeline(RESULTS,OUTLINE);
- end if;
- end loop;
- end process;
-
-
--- *** End Test Bench - User Defined Section ***
-
-COUNT_BITS: process (CLOCK, TRANSMIT)
- variable BITS_SENT : integer range 0 to 1048576 := 0;
- begin
- if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then
- BITS_SENT := BITS_SENT+1;
- end if;
- end process;
-END;
testbench/ArithmeticCoderTestbench.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/ARITHMETICDECODER.vhd
===================================================================
--- decoder/ARITHMETICDECODER.vhd (revision 12)
+++ decoder/ARITHMETICDECODER.vhd (nonexistent)
@@ -1,265 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: ARITHMETICDECODER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ARITHMETICDECODER is
- generic (PROB : std_logic_vector (9 downto 0) := "1010101010");
- Port ( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
-end ARITHMETICDECODER;
-
-architecture RTL of ARITHMETICDECODER is
- component INPUT_CONTROL
- port( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- BUFFER_CONTROL : in std_logic;
- DEMAND : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
- end component INPUT_CONTROL;
- component STORAGE_REGISTER
- Port ( LOAD : in std_logic_vector(15 downto 0);
- SHIFT_IN : in std_logic;
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
- end component STORAGE_REGISTER;
- component CONVERGENCE_CHECK
- port ( HIGH_MSB : in std_logic;
- LOW_MSB : in std_logic;
- HIGH_SECONDBIT : in std_logic;
- LOW_SECONDBIT : in std_logic;
- CHECK : in std_logic;
- TRIGGER_OUTPUT : out std_logic;
- TRIGGER_FOLLOW : out std_logic);
- end component CONVERGENCE_CHECK;
- component ARITHMETIC_UNIT
- port ( DIFFERENCE : in std_logic_vector(15 downto 0);
- PROB : in std_logic_vector(9 downto 0);
- LOW : in std_logic_vector(15 downto 0);
- ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
- DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
- RESULT_OUT0 : out std_logic_vector(15 downto 0);
- RESULT_OUT1 : out std_logic_vector(15 downto 0);
- DATA_LOAD : out std_logic);
- end component ARITHMETIC_UNIT;
- component SYMBOL_DETECTOR
- port ( ENABLE : in std_logic;
- DATA_IN : in std_logic_vector (15 downto 0);
- THRESHOLD : in std_logic_vector (15 downto 0);
- DATA_OUT : out std_logic);
- end component SYMBOL_DETECTOR;
- signal HIGH_SET : std_logic;
- signal LOW_SET : std_logic;
- signal SHIFT_ALL : std_logic;
- signal DIFFERENCE_SHIFT_ALL : std_logic;
- signal SHIFT_MOST : std_logic;
- signal ZERO_OUTPUT : std_logic;
- signal ARITHMETIC_UNIT_ENABLE : std_logic;
- signal CONVERGENCE_TEST : std_logic;
- signal TRIGGER_INPUT : std_logic;
- signal TRIGGER_FOLLOW: std_logic;
- signal DATA_LOAD: std_logic;
- signal GET_DATA : std_logic;
- signal DATA_AVAILABLE : std_logic;
- signal BUFFERED_DATA : std_logic;
- signal SYMBOL : std_logic;
- signal HOLD : std_logic;
- signal DIFFERENCE_IN : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT0 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_RESULT_OUT1 : std_logic_vector (15 downto 0);
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT0 : std_logic_vector(15 downto 0);
- signal ARITHMETIC_UNIT_DIFFERENCE_OUT1 : std_logic_vector(15 downto 0);
- signal DIFFERENCE_VALUE : std_logic_vector (15 downto 0);
- signal HIGH_VALUE : std_logic_vector (15 downto 0);
- signal LOW_VALUE : std_logic_vector (15 downto 0);
- signal CURRENT_VALUE : std_logic_vector (15 downto 0);
-
-begin
--- input buffering
-INBUFFER: INPUT_CONTROL
- port map(ENABLE => ENABLE,
- DATA_IN => DATA_IN,
- BUFFER_CONTROL => HOLD,
- DEMAND => GET_DATA,
- RESET => RESET,
- CLOCK => CLOCK,
- SENDING => DATA_AVAILABLE,
- DATA_OUT => BUFFERED_DATA);
-
--- Specify the registers
- HIGH: STORAGE_REGISTER
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT0,
- SHIFT_IN => '1',
- SET_VALUE => HIGH_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => HIGH_VALUE);
-
-LOW: STORAGE_REGISTER
- port map( LOAD => ARITHMETIC_UNIT_RESULT_OUT1,
- SHIFT_IN => '0',
- SET_VALUE => LOW_SET,
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => LOW_VALUE);
-
-DIFFERENCE: STORAGE_REGISTER
- port map( LOAD => DIFFERENCE_IN,
- SHIFT_IN => '1',
- SET_VALUE => DATA_LOAD,
- SHIFT_ALL => DIFFERENCE_SHIFT_ALL,
- SHIFT_MOST => '0',
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => DIFFERENCE_VALUE);
-
-CURRENT: STORAGE_REGISTER
- port map( LOAD => "0000000000000000",
- SHIFT_IN => BUFFERED_DATA,
- SET_VALUE => '0',
- SHIFT_ALL => SHIFT_ALL,
- SHIFT_MOST => SHIFT_MOST,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => CURRENT_VALUE);
--- The arithmetic
-
-ARITH: ARITHMETIC_UNIT
- port map(DIFFERENCE => DIFFERENCE_VALUE,
- PROB => PROB,
- LOW => LOW_VALUE,
- ENABLE => ARITHMETIC_UNIT_ENABLE,
- RESET => RESET,
- CLOCK => CLOCK,
- DIFFERENCE_OUT0 => ARITHMETIC_UNIT_DIFFERENCE_OUT0,
- DIFFERENCE_OUT1 => ARITHMETIC_UNIT_DIFFERENCE_OUT1,
- RESULT_OUT0 => ARITHMETIC_UNIT_RESULT_OUT0,
- RESULT_OUT1 => ARITHMETIC_UNIT_RESULT_OUT1,
- DATA_LOAD => DATA_LOAD);
-
---The convergence checks
-
-CONVERGE: CONVERGENCE_CHECK
- port map(HIGH_MSB => HIGH_VALUE(15),
- LOW_MSB => LOW_VALUE(15),
- HIGH_SECONDBIT => HIGH_VALUE(14),
- LOW_SECONDBIT => LOW_VALUE(14),
- CHECK => CONVERGENCE_TEST,
- TRIGGER_OUTPUT => TRIGGER_INPUT,
- TRIGGER_FOLLOW => TRIGGER_FOLLOW);
-
---The output unit
-
-OUTPUT: SYMBOL_DETECTOR
- port map(ENABLE => DATA_LOAD,
- DATA_IN => CURRENT_VALUE,
- THRESHOLD => ARITHMETIC_UNIT_RESULT_OUT1,
- DATA_OUT => SYMBOL);
-
- SENDING <= DATA_LOAD;
- DATA_OUT <= SYMBOL;
--- Input logic
-
- HIGH_SET <= ZERO_OUTPUT and DATA_LOAD;
- ZERO_OUTPUT <= not SYMBOL;
- LOW_SET <= SYMBOL and DATA_LOAD;
- GET_DATA <= TRIGGER_INPUT or TRIGGER_FOLLOW;
- HOLD <= DATA_LOAD or not GET_DATA;
-
--- Control logic for DIFFERENCE register
-
- DIFFERENCE_SHIFT_ALL <= SHIFT_ALL or SHIFT_MOST;
-
--- Control logic for convergence check
-
--- CHECK <= DIFFERENCE_SHIFT_ALL or DATA_LOAD or RESET;
-
--- CONVERGENCE_TEST_DELAY: D_TYPE
--- port map( D => CHECK,
--- CLOCK => CLOCK,
--- Q => CONVERGENCE_TEST);
-
- CONVERGENCE_TEST <= not DATA_LOAD;
-
--- Control logic for arithmetic unit
-
- ARITHMETIC_UNIT_ENABLE <= GET_DATA nor DATA_LOAD;
-
--- Control Logic for input control
- SHIFT_ALL <= TRIGGER_INPUT and DATA_AVAILABLE;
- SHIFT_MOST <= TRIGGER_FOLLOW and DATA_AVAILABLE;
-
---Select new difference value
-NEWDIFF : process(SYMBOL,ARITHMETIC_UNIT_DIFFERENCE_OUT0,ARITHMETIC_UNIT_DIFFERENCE_OUT1)
- begin
- if(SYMBOL = '1') then
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT1;
- else
- DIFFERENCE_IN <= ARITHMETIC_UNIT_DIFFERENCE_OUT0;
- end if;
- end process NEWDIFF;
-
-
-
-end RTL;
decoder/ARITHMETICDECODER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/storage_register.prj
===================================================================
--- decoder/storage_register.prj (revision 12)
+++ decoder/storage_register.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work STORAGE_REGISTER.vhd
decoder/storage_register.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/STORAGE_REGISTER.vhd
===================================================================
--- decoder/STORAGE_REGISTER.vhd (revision 12)
+++ decoder/STORAGE_REGISTER.vhd (nonexistent)
@@ -1,272 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: STORAGE_REGISTER.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity STORAGE_REGISTER is
- Port ( LOAD : in std_logic_vector(15 downto 0);
- SHIFT_IN : in std_logic;
- SET_VALUE : in std_logic;
- SHIFT_ALL : in std_logic;
- SHIFT_MOST : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic_vector(15 downto 0));
-end entity STORAGE_REGISTER;
-
-architecture RTL of STORAGE_REGISTER is
- component STORE_BLOCK
- port(LOAD_IN, SHIFT_IN, SHIFT, ENABLE, CLK: in std_logic;
- OUTPUT: out std_logic);
- end component STORE_BLOCK;
- signal SHIFT_LSBS: std_logic;
- signal SET_RESET: std_logic;
- signal ENABLE_MSB: std_logic;
- signal ENABLE_LSBS: std_logic;
- signal D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15: std_logic;
- signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15: std_logic;
-begin
-
--- control logic
- SET_RESET <= SET_VALUE or RESET;
- ENABLE_MSB <= SET_RESET or SHIFT_ALL;
- SHIFT_LSBS <= SHIFT_ALL or SHIFT_MOST;
- ENABLE_LSBS <= SET_RESET or SHIFT_LSBS;
-
--- outputs
-
- OUTPUT(0) <= Q0;
- OUTPUT(1) <= Q1;
- OUTPUT(2) <= Q2;
- OUTPUT(3) <= Q3;
- OUTPUT(4) <= Q4;
- OUTPUT(5) <= Q5;
- OUTPUT(6) <= Q6;
- OUTPUT(7) <= Q7;
- OUTPUT(8) <= Q8;
- OUTPUT(9) <= Q9;
- OUTPUT(10) <= Q10;
- OUTPUT(11) <= Q11;
- OUTPUT(12) <= Q12;
- OUTPUT(13) <= Q13;
- OUTPUT(14) <= Q14;
- OUTPUT(15) <= Q15;
-
--- initialisation
-
-INIT: process(RESET,LOAD)
-begin
- if RESET = '1' then
- D0 <= '0';
- D1 <= '0';
- D2 <= '0';
- D3 <= '0';
- D4 <= '0';
- D5 <= '0';
- D6 <= '0';
- D7 <= '0';
- D8 <= '0';
- D9 <= '0';
- D10 <= '0';
- D11 <= '0';
- D12 <= '0';
- D13 <= '0';
- D14 <= '0';
- D15 <= '0';
- else
- D0 <= LOAD(0);
- D1 <= LOAD(1);
- D2 <= LOAD(2);
- D3 <= LOAD(3);
- D4 <= LOAD(4);
- D5 <= LOAD(5);
- D6 <= LOAD(6);
- D7 <= LOAD(7);
- D8 <= LOAD(8);
- D9 <= LOAD(9);
- D10 <= LOAD(10);
- D11 <= LOAD(11);
- D12 <= LOAD(12);
- D13 <= LOAD(13);
- D14 <= LOAD(14);
- D15 <= LOAD(15);
- end if;
-end process INIT;
-
--- storage
-
- STORE0: STORE_BLOCK
- port map(LOAD_IN => D0,
- SHIFT_IN => SHIFT_IN,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q0);
-
- STORE1: STORE_BLOCK
- port map(LOAD_IN => D1,
- SHIFT_IN => Q0,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q1);
-
- STORE2: STORE_BLOCK
- port map(LOAD_IN => D2,
- SHIFT_IN => Q1,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q2);
-
- STORE3: STORE_BLOCK
- port map(LOAD_IN => D3,
- SHIFT_IN => Q2,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q3);
-
- STORE4: STORE_BLOCK
- port map(LOAD_IN => D4,
- SHIFT_IN => Q3,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q4);
-
- STORE5: STORE_BLOCK
- port map(LOAD_IN => D5,
- SHIFT_IN => Q4,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q5);
-
- STORE6: STORE_BLOCK
- port map(LOAD_IN => D6,
- SHIFT_IN => Q5,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q6);
-
- STORE7: STORE_BLOCK
- port map(LOAD_IN => D7,
- SHIFT_IN => Q6,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q7);
-
- STORE8: STORE_BLOCK
- port map(LOAD_IN => D8,
- SHIFT_IN => Q7,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q8);
-
- STORE9: STORE_BLOCK
- port map(LOAD_IN => D9,
- SHIFT_IN => Q8,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q9);
-
- STORE10: STORE_BLOCK
- port map(LOAD_IN => D10,
- SHIFT_IN => Q9,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q10);
-
- STORE11: STORE_BLOCK
- port map(LOAD_IN => D11,
- SHIFT_IN => Q10,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q11);
-
- STORE12: STORE_BLOCK
- port map(LOAD_IN => D12,
- SHIFT_IN => Q11,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q12);
-
- STORE13: STORE_BLOCK
- port map(LOAD_IN => D13,
- SHIFT_IN => Q12,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q13);
-
- STORE14: STORE_BLOCK
- port map(LOAD_IN => D14,
- SHIFT_IN => Q13,
- SHIFT => SHIFT_LSBS,
- ENABLE => ENABLE_LSBS,
- CLK => CLOCK,
- OUTPUT => Q14);
-
- STORE15: STORE_BLOCK
- port map(LOAD_IN => D15,
- SHIFT_IN => Q14,
- SHIFT => SHIFT_ALL,
- ENABLE => ENABLE_MSB,
- CLK => CLOCK,
- OUTPUT => Q15);
-
-
-
-end architecture RTL;
-
decoder/STORAGE_REGISTER.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/symbol_detector.prj
===================================================================
--- decoder/symbol_detector.prj (revision 12)
+++ decoder/symbol_detector.prj (nonexistent)
@@ -1 +0,0 @@
-vhdl work SYMBOL_DETECTOR.vhd
decoder/symbol_detector.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/arithmeticdecoder.prj
===================================================================
--- decoder/arithmeticdecoder.prj (revision 12)
+++ decoder/arithmeticdecoder.prj (nonexistent)
@@ -1,11 +0,0 @@
-vhdl work ../common/D_TYPE.vhd
-vhdl work ../common/COUNT_UNIT.vhd
-vhdl work ../common/ENABLEABLE_D_TYPE.vhd
-vhdl work ../common/FIFO.vhd
-vhdl work ../common/INPUT_CONTROL.vhd
-vhdl work ../common/STORE_BLOCK.vhd
-vhdl work STORAGE_REGISTER.vhd
-vhdl work ../common/ARITHMETIC_UNIT.vhd
-vhdl work ../common/CONVERGENCE_CHECK.vhd
-vhdl work SYMBOL_DETECTOR.vhd
-vhdl work ARITHMETICDECODER.vhd
decoder/arithmeticdecoder.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: decoder/SYMBOL_DETECTOR.vhd
===================================================================
--- decoder/SYMBOL_DETECTOR.vhd (revision 12)
+++ decoder/SYMBOL_DETECTOR.vhd (nonexistent)
@@ -1,71 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: SYMBOL_DETECTOR.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity SYMBOL_DETECTOR is
- Port ( ENABLE : in std_logic;
- DATA_IN : in std_logic_vector(15 downto 0);
- THRESHOLD : in std_logic_vector(15 downto 0);
- DATA_OUT : out std_logic);
-end SYMBOL_DETECTOR;
-
-architecture RTL of SYMBOL_DETECTOR is
-
-begin
-DECODE: process(ENABLE,DATA_IN,THRESHOLD)
- begin
- if ((ENABLE = '1') and (DATA_IN >= THRESHOLD)) then
- DATA_OUT <= '1';
- else
- DATA_OUT <= '0';
- end if;
-end process DECODE;
-
-
-
-
-end RTL;
decoder/SYMBOL_DETECTOR.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/INPUT_CONTROL.vhd
===================================================================
--- common/INPUT_CONTROL.vhd (revision 12)
+++ common/INPUT_CONTROL.vhd (nonexistent)
@@ -1,107 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: INPUT_CONTROL.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity INPUT_CONTROL is
- Port ( ENABLE : in std_logic;
- DATA_IN : in std_logic;
- BUFFER_CONTROL : in std_logic;
- DEMAND : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- SENDING : out std_logic;
- DATA_OUT : out std_logic);
-end INPUT_CONTROL;
-
-architecture RTL of INPUT_CONTROL is
- component FIFO
- port( WRITE_ENABLE : in std_logic;
- DATA_IN : in std_logic;
- READ_ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DATA_OUT : out std_logic;
- EMPTY : out std_logic);
- end component FIFO;
- signal FIFO_WRITE_ENABLE : std_logic;
- signal FIFO_READ_ENABLE : std_logic;
- signal FIFO_DATA_IN : std_logic;
- signal FIFO_DATA_OUT : std_logic;
- signal FIFO_EMPTY : std_logic;
- signal USE_BUFFER : std_logic;
- signal PUT_IN_BUFFER : std_logic;
-begin
-
-STORAGE : FIFO
- port map(WRITE_ENABLE => FIFO_WRITE_ENABLE,
- DATA_IN => FIFO_DATA_IN,
- READ_ENABLE => FIFO_READ_ENABLE,
- RESET => RESET,
- CLOCK => CLOCK,
- DATA_OUT => FIFO_DATA_OUT,
- EMPTY => FIFO_EMPTY);
-
- FIFO_WRITE_ENABLE <= ENABLE and USE_BUFFER;
- FIFO_DATA_IN <= DATA_IN and USE_BUFFER;
- FIFO_READ_ENABLE <= DEMAND and USE_BUFFER;
-
- PUT_IN_BUFFER <= ENABLE and BUFFER_CONTROL;
- USE_BUFFER <= PUT_IN_BUFFER or not FIFO_EMPTY;
-
-OUTPUT_SELECT: process(USE_BUFFER,DEMAND,FIFO_DATA_OUT,ENABLE,DATA_IN)
-begin
- if USE_BUFFER = '1' then
- SENDING <= DEMAND;
- DATA_OUT <= FIFO_DATA_OUT;
- else
- SENDING <= ENABLE;
- DATA_OUT <= DATA_IN;
- end if;
-end process OUTPUT_SELECT;
-
-
-end RTL;
common/INPUT_CONTROL.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/count_unit.prj
===================================================================
--- common/count_unit.prj (revision 12)
+++ common/count_unit.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work COUNT_UNIT.vhd
common/count_unit.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/arithmetic_unit.prj
===================================================================
--- common/arithmetic_unit.prj (revision 12)
+++ common/arithmetic_unit.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work ARITHMETIC_UNIT.vhd
common/arithmetic_unit.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/convergence_check.prj
===================================================================
--- common/convergence_check.prj (revision 12)
+++ common/convergence_check.prj (nonexistent)
@@ -1 +0,0 @@
-vhdl work CONVERGENCE_CHECK.vhd
common/convergence_check.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/STORE_BLOCK.vhd
===================================================================
--- common/STORE_BLOCK.vhd (revision 12)
+++ common/STORE_BLOCK.vhd (nonexistent)
@@ -1,86 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: STORE_BLOCK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity STORE_BLOCK is
- Port ( LOAD_IN : in std_logic;
- SHIFT_IN : in std_logic;
- SHIFT : in std_logic;
- ENABLE : in std_logic;
- CLK : in std_logic;
- OUTPUT : out std_logic);
-end STORE_BLOCK;
-
-architecture RTL of STORE_BLOCK is
- component ENABLEABLE_D_TYPE
- port (DATA_IN, ENABLE, CLK: in std_logic;
- DATA_OUT: out std_logic);
- end component;
-
- signal LOAD_VALUE : std_logic;
-begin
-
-
- STORAGE: ENABLEABLE_D_TYPE
- port map(DATA_IN => LOAD_VALUE,
- ENABLE => ENABLE,
- CLK => CLK,
- DATA_OUT => OUTPUT);
-
- SELECT_VALUE: process(SHIFT,SHIFT_IN,LOAD_IN)
- begin
- if SHIFT = '1' then
- LOAD_VALUE <= SHIFT_IN;
- else
- LOAD_VALUE <= LOAD_IN;
- end if;
- end process SELECT_VALUE;
-
-
-
-
-end RTL;
common/STORE_BLOCK.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/input_control.prj
===================================================================
--- common/input_control.prj (revision 12)
+++ common/input_control.prj (nonexistent)
@@ -1,5 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work COUNT_UNIT.vhd
-vhdl work ENABLEABLE_D_TYPE.vhd
-vhdl work FIFO.vhd
-vhdl work INPUT_CONTROL.vhd
common/input_control.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/ENABLEABLE_D_TYPE.vhd
===================================================================
--- common/ENABLEABLE_D_TYPE.vhd (revision 12)
+++ common/ENABLEABLE_D_TYPE.vhd (nonexistent)
@@ -1,82 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: ENABLEABLE_D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ENABLEABLE_D_TYPE is
- Port ( DATA_IN : in std_logic;
- ENABLE : in std_logic;
- CLK : in std_logic;
- DATA_OUT : out std_logic);
-end ENABLEABLE_D_TYPE;
-
-architecture RTL of ENABLEABLE_D_TYPE is
- signal RETAIN : std_logic;
- signal D_IN : std_logic;
- component D_TYPE
- port(D,CLOCK: in std_logic;
- Q: out std_logic);
- end component;
-begin
-
- FLIP_FLOP: D_TYPE
- port map(
- D => D_IN,
- CLOCK => CLK,
- Q => RETAIN);
-
- DATA_OUT <= RETAIN;
-
- LOAD: process(ENABLE,DATA_IN,RETAIN)
- begin
- if ENABLE = '1' then
- D_IN <= DATA_IN;
- else
- D_IN <= RETAIN;
- end if;
- end process LOAD;
-
-end architecture RTL;
common/ENABLEABLE_D_TYPE.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/store_block.prj
===================================================================
--- common/store_block.prj (revision 12)
+++ common/store_block.prj (nonexistent)
@@ -1,3 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work ENABLEABLE_D_TYPE.vhd
-vhdl work STORE_BLOCK.vhd
common/store_block.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/FIFO.vhd
===================================================================
--- common/FIFO.vhd (revision 12)
+++ common/FIFO.vhd (nonexistent)
@@ -1,212 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: FIFO.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity FIFO is
- generic (RANK : integer range 0 to 16 :=8);
- Port ( WRITE_ENABLE : in std_logic;
- DATA_IN : in std_logic;
- READ_ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DATA_OUT : out std_logic;
- EMPTY : out std_logic);
-end FIFO;
-
-architecture RTL of FIFO is
- component ENABLEABLE_D_TYPE
- port (DATA_IN : in std_logic;
- ENABLE : in std_logic;
- CLK : in std_logic;
- DATA_OUT: out std_logic);
- end component ENABLEABLE_D_TYPE;
- component D_TYPE
- port( D : in std_logic;
- CLOCK : in std_logic;
- Q : out std_logic);
-end component D_TYPE;
- component COUNT_UNIT
- port( INCREMENT : in std_logic;
- DECREMENT : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic;
- INCREMENT_CARRY : out std_logic;
- DECREMENT_CARRY : out std_logic);
-end component COUNT_UNIT;
- function TWO_TO_N(N: integer) return integer is
- variable A: integer;
- begin
- A := 1;
- for Z in 0 to N - 1 loop
- A := 2*A;
- end loop;
- return A;
- end function TWO_TO_N;
- function ZERO_VALUE(ADDRESS: std_logic_vector) return std_logic is
- begin
- for J in 0 to RANK - 1 loop
- if ADDRESS(J) = '1' then
- return '0';
- end if;
- end loop;
- return '1';
- end function ZERO_VALUE;
-
- signal READ_ADDRESS : std_logic_vector (RANK - 1 downto 0);
- signal INC : std_logic_vector (RANK - 1 downto 0);
- signal DEC : std_logic_vector (RANK - 1 downto 0);
- type MATRIX is
- array (RANK downto 0) of std_logic_vector (TWO_TO_N(RANK) -1 downto 0);
- signal GET_OUTPUT: MATRIX;
- signal NEWVAL : std_logic_vector(TWO_TO_N(RANK) - 1 downto 0);
- signal INCREMENT : std_logic;
- signal DECREMENT : std_logic;
- signal TOGGLE : std_logic;
- signal IS_EMPTY : std_logic;
- signal ZERO : std_logic;
- signal NEW_EMPTY : std_logic;
- signal EMPTY_OUT : std_logic;
- signal NOWRITE : std_logic;
- signal CHANGED_VALUE : std_logic;
- signal EMPTY_IF_READ : std_logic;
- signal LOAD_ENABLE : std_logic;
-begin
--- Storage registers
-
-
-BUILD: for I in 0 to RANK -1 generate
-
-LSB: if I = 0 generate
-COUNTER : COUNT_UNIT
- port map( INCREMENT => INCREMENT,
- DECREMENT => DECREMENT,
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => READ_ADDRESS(I),
- INCREMENT_CARRY => INC(I),
- DECREMENT_CARRY => DEC(I));
-
- end generate;
-
-OTHER_BITS: if I > 0 generate
-COUNTER : COUNT_UNIT
- port map( INCREMENT => INC(I-1),
- DECREMENT => DEC(I-1),
- RESET => RESET,
- CLOCK => CLOCK,
- OUTPUT => READ_ADDRESS(I),
- INCREMENT_CARRY => INC(I),
- DECREMENT_CARRY => DEC(I));
- end generate;
-
-MULTIPLEX: for Z in 0 to TWO_TO_N(I) - 1 generate
-OUTPUT_SELECT: process(READ_ADDRESS(RANK - I - 1),GET_OUTPUT(RANK - I -1))
-begin
- if READ_ADDRESS(RANK - I - 1) = '1' then
- GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z + 1);
- else
- GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z);
- end if;
-end process OUTPUT_SELECT;
-end generate;
-
-STORAGE: if I = RANK - 1 generate
-BITS: for X in 0 to TWO_TO_N(RANK) - 1 generate
-STORE: ENABLEABLE_D_TYPE
- port map (DATA_IN => NEWVAL(X),
- ENABLE => LOAD_ENABLE,
- CLK => CLOCK,
- DATA_OUT => GET_OUTPUT(0)(X));
-MOST_RECENT: if X = 0 generate
- NEWVAL(X) <= DATA_IN and not RESET;
-end generate;
-
-OLDER_DATA: if X > 0 generate
- NEWVAL(X) <= GET_OUTPUT(0)(X-1) and not RESET;
-end generate;
-end generate;
-end generate;
-
-
-end generate;
-
-LOAD_ENABLE <= WRITE_ENABLE or RESET;
-INCREMENT <= WRITE_ENABLE and not (READ_ENABLE or EMPTY_OUT);
-DECREMENT <= READ_ENABLE and not (WRITE_ENABLE or ZERO);
-
-EMPTY_VALUE: D_TYPE
- port map(D => IS_EMPTY,
- CLOCK => CLOCK,
- Q => EMPTY_OUT);
-
-IS_EMPTY <= NEW_EMPTY or RESET;
-
-SWITCH_EMPTY: process(TOGGLE,EMPTY_OUT,CHANGED_VALUE)
-begin
- if(TOGGLE = '1') then
- NEW_EMPTY <= CHANGED_VALUE;
- else
- NEW_EMPTY <= EMPTY_OUT;
- end if;
-end process SWITCH_EMPTY;
-
-TOGGLE <= WRITE_ENABLE xor READ_ENABLE;
-CHANGED_VALUE <= EMPTY_IF_READ and NOWRITE;
-NOWRITE <= not WRITE_ENABLE;
-EMPTY_IF_READ <= ZERO or EMPTY_OUT;
-
-
-ZERO <= ZERO_VALUE(READ_ADDRESS);
-
-EMPTY <= EMPTY_OUT;
-
-DATA_OUT <= GET_OUTPUT(RANK)(0);
-
-
-
-end RTL;
common/FIFO.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/D_TYPE.vhd
===================================================================
--- common/D_TYPE.vhd (revision 12)
+++ common/D_TYPE.vhd (nonexistent)
@@ -1,69 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: D_TYPE.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity D_TYPE is
- Port (
- D : in std_logic;
- CLOCK : in std_logic;
- Q : out std_logic);
-end D_TYPE;
-
-architecture RTL of D_TYPE is
-begin
-FLIP_FLOP: process(CLOCK)
-begin
- if CLOCK'event and CLOCK = '1' then
- Q <= D;
- end if;
-end process FLIP_FLOP;
-
-end RTL;
-
-configuration STANDARD of D_TYPE is
-for RTL end for;
-end configuration STANDARD;
\ No newline at end of file
common/D_TYPE.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/COUNT_UNIT.vhd
===================================================================
--- common/COUNT_UNIT.vhd (revision 12)
+++ common/COUNT_UNIT.vhd (nonexistent)
@@ -1,92 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: COUNT_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity COUNT_UNIT is
- Port ( INCREMENT : in std_logic;
- DECREMENT : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- OUTPUT : out std_logic;
- INCREMENT_CARRY : out std_logic;
- DECREMENT_CARRY : out std_logic);
-end COUNT_UNIT;
-
-architecture RTL of COUNT_UNIT is
- component D_TYPE
- port(D,CLOCK: in std_logic;
- Q: out std_logic);
- end component D_TYPE;
- signal UPDATE: std_logic :='0';
- signal TOGGLE: std_logic;
- signal Q_VAL: std_logic;
- signal INVERSE: std_logic;
- signal NEWVAL : std_logic;
-begin
-
--- combinatorial logic
-
- TOGGLE <= INCREMENT xor DECREMENT;
- INVERSE <= not Q_VAL;
- OUTPUT <= Q_VAL;
- INCREMENT_CARRY <= INCREMENT and not DECREMENT and Q_VAL;
- DECREMENT_CARRY <= DECREMENT and not INCREMENT and INVERSE;
- NEWVAL <= Q_VAL xor TOGGLE;
- UPDATE <= NEWVAL and not RESET;
-
-
-
-
-
--- The D_TYPE
-
-FLIP_FLOP: D_TYPE
- port map(D => UPDATE,
- CLOCK => CLOCK,
- Q => Q_VAL);
-
-end RTL;
common/COUNT_UNIT.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/ARITHMETIC_UNIT.vhd
===================================================================
--- common/ARITHMETIC_UNIT.vhd (revision 12)
+++ common/ARITHMETIC_UNIT.vhd (nonexistent)
@@ -1,143 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: ARITHMETIC_UNIT.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity ARITHMETIC_UNIT is
- Port ( DIFFERENCE : in std_logic_vector(15 downto 0);
- PROB : in std_logic_vector(9 downto 0);
- LOW : in std_logic_vector(15 downto 0);
- ENABLE : in std_logic;
- RESET : in std_logic;
- CLOCK : in std_logic;
- DIFFERENCE_OUT0 : out std_logic_vector(15 downto 0);
- DIFFERENCE_OUT1 : out std_logic_vector(15 downto 0);
- RESULT_OUT0 : out std_logic_vector(15 downto 0);
- RESULT_OUT1 : out std_logic_vector(15 downto 0);
- DATA_LOAD : out std_logic :='1');
-end ARITHMETIC_UNIT;
-
-architecture RTL of ARITHMETIC_UNIT is
- component D_TYPE
- port(D,CLOCK: in std_logic;
- Q: out std_logic);
- end component D_TYPE;
- signal LOW2 : std_logic_vector(16 downto 0);
- signal PRODUCT : std_logic_vector (26 downto 0);
- signal PRODUCT2 : std_logic_vector (16 downto 0);
- signal RESULT : std_logic_vector (16 downto 0);
- signal RESULT0 : std_logic_vector (15 downto 0);
- signal DIFFERENCE1 : std_logic_vector (16 downto 0);
- signal DIFFERENCE2 : std_logic_vector(16 downto 0);
- signal DIFFERENCE3 : std_logic_vector(16 downto 0);
- signal DIFFERENCE4 : std_logic_vector(16 downto 0);
- signal DELAY1 : std_logic;
- signal DELAY2 : std_logic;
- signal CALCULATE : std_logic;
-begin
-
--- The arithmetic
- DIFFERENCE2 <= ('0' & DIFFERENCE) + "00000000000000001";
-MULTIPLY : process (CLOCK, DIFFERENCE2, PROB)
- begin
- if CLOCK'event and CLOCK = '1' then
- PRODUCT <= DIFFERENCE2 * PROB;
- end if;
- end process MULTIPLY;
- PRODUCT2 <= PRODUCT(26 downto 10);
- RESULT <= LOW2 + PRODUCT2;
- RESULT_OUT1 <= RESULT(15 downto 0);
- RESULT0 <= (RESULT - "00000000000000001");
- RESULT_OUT0 <= RESULT0(15 downto 0);
- DIFFERENCE3 <= (PRODUCT2 - "00000000000000001");
- DIFFERENCE4 <= (DIFFERENCE1 - PRODUCT2);
- DIFFERENCE_OUT1 <= DIFFERENCE4(15 downto 0);
-
-
-
-
--- Control logic
- CALCULATE <= ENABLE and not RESET;
- DATA_LOAD <= DELAY1 and DELAY2;
-
--- Sequential control logic
-
-READ_DELAY: D_TYPE
- port map(D => CALCULATE,
- CLOCK => CLOCK,
- Q => DELAY1);
-
-CHECK_DELAY: D_TYPE
- port map(D => DELAY1,
- CLOCK => CLOCK,
- Q => DELAY2);
-
-DELAYS: for I in 0 to 15 generate
-
-DIFF_DELAY: D_TYPE
- port map(D => DIFFERENCE(I),
- CLOCK => CLOCK,
- Q => DIFFERENCE1(I));
-
-LOW_DELAY: D_TYPE
- port map(D => LOW(I),
- CLOCK => CLOCK,
- Q => LOW2(I));
-
-OUT_DELAY0: D_TYPE
- port map(D => DIFFERENCE3(I),
- CLOCK => CLOCK,
- Q => DIFFERENCE_OUT0(I));
-
-
-end generate;
-
-LOW2(16) <= '0';
-DIFFERENCE1(16) <= '0';
-
-
-end RTL;
common/ARITHMETIC_UNIT.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/enableable_d_type.prj
===================================================================
--- common/enableable_d_type.prj (revision 12)
+++ common/enableable_d_type.prj (nonexistent)
@@ -1,2 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work ENABLEABLE_D_TYPE.vhd
common/enableable_d_type.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/CONVERGENCE_CHECK.vhd
===================================================================
--- common/CONVERGENCE_CHECK.vhd (revision 12)
+++ common/CONVERGENCE_CHECK.vhd (nonexistent)
@@ -1,82 +0,0 @@
--- ***** BEGIN LICENSE BLOCK *****
---
--- $Id: CONVERGENCE_CHECK.vhd,v 1.1.1.1 2005-03-30 10:09:49 petebleackley Exp $ $Name: not supported by cvs2svn $
--- *
--- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
--- *
--- * The contents of this file are subject to the Mozilla Public License
--- * Version 1.1 (the "License"); you may not use this file except in compliance
--- * with the License. You may obtain a copy of the License at
--- * http://www.mozilla.org/MPL/
--- *
--- * Software distributed under the License is distributed on an "AS IS" basis,
--- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--- * the specific language governing rights and limitations under the License.
--- *
--- * The Original Code is BBC Research and Development code.
--- *
--- * The Initial Developer of the Original Code is the British Broadcasting
--- * Corporation.
--- * Portions created by the Initial Developer are Copyright (C) 2004.
--- * All Rights Reserved.
--- *
--- * Contributor(s): Peter Bleackley (Original author)
--- *
--- * Alternatively, the contents of this file may be used under the terms of
--- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
--- * the GPL or the LGPL are applicable instead of those above. If you wish to
--- * allow use of your version of this file only under the terms of the either
--- * the GPL or LGPL and not to allow others to use your version of this file
--- * under the MPL, indicate your decision by deleting the provisions above
--- * and replace them with the notice and other provisions required by the GPL
--- * or LGPL. If you do not delete the provisions above, a recipient may use
--- * your version of this file under the terms of any one of the MPL, the GPL
--- * or the LGPL.
--- * ***** END LICENSE BLOCK ***** */
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
--- Uncomment the following lines to use the declarations that are
--- provided for instantiating Xilinx primitive components.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity CONVERGENCE_CHECK is
- Port ( HIGH_MSB : in std_logic;
- LOW_MSB : in std_logic;
- HIGH_SECONDBIT : in std_logic;
- LOW_SECONDBIT : in std_logic;
- CHECK : in std_logic;
- TRIGGER_OUTPUT : out std_logic;
- TRIGGER_FOLLOW : out std_logic);
-end CONVERGENCE_CHECK;
-
-architecture RTL of CONVERGENCE_CHECK is
- signal MSB_AND : std_logic;
- signal MSB_NOR : std_logic;
- signal MSB_EQ : std_logic;
- signal MSB_XOR : std_logic;
- signal INV : std_logic;
- signal SECOND_BIT_01: std_logic;
- signal STRADDLE: std_logic;
-begin
-
- MSB_AND <= HIGH_MSB and LOW_MSB;
- MSB_NOR <= HIGH_MSB nor LOW_MSB;
- MSB_EQ <= MSB_AND or MSB_NOR;
- MSB_XOR <= not MSB_EQ;
-
- INV <= not HIGH_SECONDBIT;
- SECOND_BIT_01 <= INV and LOW_SECONDBIT;
- STRADDLE <= MSB_XOR and SECOND_BIT_01;
-
- TRIGGER_OUTPUT <= CHECK and MSB_EQ;
- TRIGGER_FOLLOW <= CHECK and STRADDLE;
-
-
-end RTL;
common/CONVERGENCE_CHECK.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/fifo.prj
===================================================================
--- common/fifo.prj (revision 12)
+++ common/fifo.prj (nonexistent)
@@ -1,4 +0,0 @@
-vhdl work D_TYPE.vhd
-vhdl work COUNT_UNIT.vhd
-vhdl work ENABLEABLE_D_TYPE.vhd
-vhdl work FIFO.vhd
common/fifo.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: common/d_type.prj
===================================================================
--- common/d_type.prj (revision 12)
+++ common/d_type.prj (nonexistent)
@@ -1 +0,0 @@
-vhdl work D_TYPE.vhd
common/d_type.prj
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property