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Subversion Repositories distributed_intelligence

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  • This comparison shows the changes necessary to convert path 
    /distributed_intelligence/trunk/LIB
    from Rev 4 to Rev 5
    ↔ Reverse comparison
  •

Rev 4 → Rev 5

/UnitTest.vhd
1,7 → 1,6
-- Package File Template
-- UNIT TESTS
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
-- Purpose: This package gives procedures and function to make automated unit tests.
 
 
library IEEE;
9,15 → 8,17
use IEEE.NUMERIC_STD.all;
 
package UnitTest is
 
-- Declare constants
 
-- Declare functions and procedure
 
-- assertEqual:
-- This procedure tests if 2 values are equal, if they are not, it shows an error report
procedure assertEqual(current, expected: in integer; resultName: in string := "Result");
procedure assertEqual(current, expected: in std_logic; resultName: in string := "Result");
procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result");
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result");
-- assertOperationResult:
-- This procedure tests if an operation is working under overflow conditions. If they are not, it reports an error.
-- You can also specify an overflow bit to be verified automatically by the procedure to be at '1' when there is an
-- overflow and at '0' when there is no overflow.
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
procedure assertOperationResult( actual, expected : in std_logic_vector; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
end UnitTest;
 
42,16 → 43,16
begin
assertEqual(to_integer(unsigned(current)), to_integer(unsigned(expected)), resultName);
end procedure;
 
 
-- Automaticaly verifies that the result is correct, beeing given the boundaries of the calculator and that
-- overflow bit is correctly set in both cases
-- Arguments:
-- actual, expected: Actual and expected results
-- opName: Name of the operation
-- overflowCond: Condition for an overflow, ignored by default
 
-- Automaticaly verifies that the result is correct, beeing given the boundaries of the calculator and that
-- overflow bit is correctly set in both cases
-- Arguments:
-- actual, expected: Actual and expected results
-- opName: Name of the operation
-- overflowCond: Condition for an overflow, ignored by default
-- overflowBit: Overflow bit set to 1 in case of overflow, no verification if set to '-' (default)
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation";
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation";
overflowCond: boolean := false; overflowBit: std_logic := '-') is
begin
if overflowCond then
64,11 → 65,11
end if;
assertEqual(actual, expected , opName & " result");
end if;
end procedure;
end procedure;
procedure assertOperationResult( actual, expected : in std_logic_vector; opName: in string:= "operation";
overflowCond: boolean := false; overflowBit: std_logic := '-') is
begin
assertOperationResult(to_integer(unsigned(actual)), to_integer(unsigned(expected)), opName, overflowCond, overflowBit);
overflowCond: boolean := false; overflowBit: std_logic := '-') is
begin
assertOperationResult(to_integer(unsigned(actual)), to_integer(unsigned(expected)), opName, overflowCond, overflowBit);
end procedure;
end UnitTest;
/MY_FUNCS.vhd
7,7 → 7,7
use IEEE.STD_LOGIC_1164.all;
 
package MY_FUNCS is
 
-- Operator sll and srl for a std_logic_vector
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector;
function "srl"(val : std_logic_vector; shift : integer) return std_logic_vector;
end MY_FUNCS;
14,16 → 14,16
 
 
package body MY_FUNCS is
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift > 0) then
for i in 1 to shift loop
ret := ret(val'high - 1 downto val'low) & '0';
end loop;
end if;
return ret;
end;
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift > 0) then
for i in 1 to shift loop
ret := ret(val'high - 1 downto val'low) & '0';
end loop;
end if;
return ret;
end;
function "srl"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
/ALU_INT.vhd
1,21 → 1,22
-- Package File Template
-- 16 bits ALU INTERFACE
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
-- Purpose: This package defines types and constants for interfacing with the 16 bits ALU.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package ALU_INT is
package ALU_INT is
-- Op codes of the ALU
type ALU_OPCODE is (bXOR, bAND, bOR, bNOT, SADD, UADD, SSUB, USUB, LSHIFT, RSHIFT, NOP);
-- Limits of a 16 bit representation
constant MAX_SIGNED:integer := (2**15)-1;
constant MIN_SIGNED:integer := -(2**15);
constant MAX_UNSIGNED:integer := (2**16)-1;
end ALU_INT;
 
package body ALU_INT is
end ALU_INT;
 
package body ALU_INT is
end ALU_INT;
 

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