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    /distributed_intelligence/trunk
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Rev 2 → Rev 3

/sum_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 21:11:24 11/05/2009
-- Design Name:
43,42 → 43,42
doAddSub: process (is_sub, is_signed, dataA, dataB)
begin
uresult <=(others => '-');
sresult <=(others => '-');
uresult <=(others => '-');
sresult <=(others => '-');
if is_signed = '0' then
if is_sub = '0' then
uresult <= unsigned('0' & dataA) + unsigned('0' & dataB);
else
uresult <= unsigned('0' & dataA) - unsigned('0' & dataB);
end if;
end if;
else
if is_sub = '0' then
sresult <= signed(dataA(15) & dataA) + signed(dataB(15) & dataB);
else
sresult <= signed(dataA(15) & dataA) - signed(dataB(15) & dataB);
end if;
end if;
end if;
end process;
setTRes: process (is_signed, uresult, sresult)
begin
setTRes: process (is_signed, uresult, sresult)
begin
if is_signed = '1' then
tRes <= std_logic_vector(sresult);
tRes <= std_logic_vector(sresult);
else
tRes <= std_logic_vector(uresult);
end if;
tRes <= std_logic_vector(uresult);
end if;
end process;
sum <= tRes(15 downto 0);
sum <= tRes(15 downto 0);
set_overflow_bit: process(is_signed, is_sub, tRes)
begin
if is_signed = '1' then
overflow <= tRes(16) xor tRes(15);
else
overflow <= tRes(16);
begin
if is_signed = '1' then
overflow <= tRes(16) xor tRes(15);
else
overflow <= tRes(16);
end if;
end process;
 
end Behavioral;
end Behavioral;
/tb_binary_counter_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 17:02:27 11/08/2009
-- Design Name:
86,7 → 86,7
 
-- Stimulus process
stim_proc: process
begin
begin
reset <= '0';
-- hold reset state for 10us.
wait for 10 us;
95,13 → 95,13
wait for clk_period*10;
inc <= '0';
wait for clk_period*10;
set_value <= std_logic_vector(to_unsigned(2**16 - 1, 16));
wait for clk_period*10;
set_value <= std_logic_vector(to_unsigned(2**16 - 1, 16));
set <= '1';
wait for clk_period;
set <= '0';
wait for clk_period;
set <= '0';
inc <= '1';
wait;
end process;
/bus_access_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 16:48:27 11/08/2009
-- Design Name:
36,16 → 36,16
 
architecture Behavioral of bus_access_x16 is
 
begin
process(clk, en, dataRead)
begin
process(clk, en, dataRead)
begin
if clk'event and clk = '1' then
if en = '1' then
dataWrite <= dataRead;
else
dataWrite <= (others => 'Z');
end if;
end if;
if clk'event and clk = '1' then
if en = '1' then
dataWrite <= dataRead;
else
dataWrite <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;
 
/tb_rdecal_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 22:06:57 11/04/2009
-- Design Name:
/tb_single_rdecal_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 22:18:23 11/04/2009
-- Design Name:
65,13 → 65,13
 
-- Stimulus process
stim_proc: process
begin
data <= x"ffff";
begin
data <= x"ffff";
op <= '0';
wait for 100 ns;
op <= '1';
wait for 100 ns;
op <= '0';
op <= '0';
wait for 100 ns;
data <= x"fafb";
/tb_generic_const_rdecal_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 22:18:23 11/04/2009
-- Design Name:
37,7 → 37,7
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT generic_const_rdecal_x16
COMPONENT generic_const_rdecal_x16
GENERIC( BIT_DECAL: natural range 0 to 15);
PORT(
data : IN std_logic_vector(15 downto 0);
/tb_ALU_simple.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 14:28:28 11/04/2009
-- Design Name:
25,13 → 25,13
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UNITTEST.all;
use work.ALU_INT.all;
use work.ALU_INT.all;
use work.MY_FUNCS.all;
 
ENTITY tb_ALU_simple IS
67,13 → 67,13
data1 => data1,
data2 => data2,
dataA => dataA,
op => op,
op => op,
overflow => overflow
);
 
-- Stimulus process
stim_proc: process
stim_proc: process
procedure testAdd(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
103,7 → 103,7
wait for delay;
 
 
 
assertOperationResult(to_integer(signed(dataA)), A+B, "signed sum", (A+B > MAX_SIGNED) or (A+B < MIN_SIGNED), overflow);
 
assertOperationResult(to_integer(unsigned(dataA)), A+B, "unsigned sum", A+B > MAX_UNSIGNED, overflow);
113,7 → 113,7
procedure testSub(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
begin
 
 
-- Fixe le signe
 
if(A < 0 or B < 0) then
124,7 → 124,7
else
signe := argSigne;
end if;
 
if signe = '1' then
op <= SSUB;
140,7 → 140,7
wait for delay;
 
 
 
assertOperationResult(to_integer(signed(dataA)), A-B, "signed subtraction", (A-B > MAX_SIGNED) or (A-B < MIN_SIGNED), overflow);
 
assertOperationResult(to_integer(unsigned(dataA)), A-B, "unsigned subtraction", (A-B > MAX_UNSIGNED) or (A-B < 0), overflow);
148,13 → 148,13
end procedure;
procedure testShift(A: in std_logic_vector(15 downto 0); argB: in integer; right: in std_logic := '-'; delay : in time := 50 ns) is
variable direction: std_logic;
variable direction: std_logic;
variable B: natural;
begin
 
 
if(argB < 0) then
direction := '1';
direction := '1';
B := -argB;
else
direction := '0';
181,7 → 181,7
else -- A droite
assertOperationResult(dataA, A srl B, "right shift", B > 15);
end if;
end procedure;
end procedure;
procedure testBinary(A, B: in std_logic_vector(15 downto 0); delay : in time := 50 ns) is
begin
221,16 → 221,16
end procedure;
begin
report "TEST BEGINS";
report "TEST BEGINS";
report "Testing binary ops ...";
-- Binary ops
-- Binary ops
testBinary(x"0000",x"0000");
testBinary(x"f610",x"00ff");
testBinary(x"ffff",x"aaaa");
testBinary(x"f00f",x"aa00");
testBinary(x"eeee",x"1111");
report "Testing shiftings ...";
-- LSHIFT
testShift(x"fafb", 1);
/tb_inverser_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 21:54:24 11/04/2009
-- Design Name:
64,15 → 64,15
 
-- Stimulus process
stim_proc: process
begin
data <= x"ff00";
inverse <= '0';
begin
data <= x"ff00";
inverse <= '0';
-- Init: 100 ns
wait for 100 ns;
inverse <= '1';
wait for 100 ns;
inverse <= '0';
inverse <= '0';
wait for 100 ns;
data <= x"afaf";
/ALU.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 14:12:50 11/04/2009
-- Design Name:
/binary_counter_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 16:51:22 11/08/2009
-- Design Name:
19,7 → 19,7
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
---- Uncomment the following library declaration if instantiating
28,7 → 28,7
--use UNISIM.VComponents.all;
 
entity binary_counter_x16 is
Port ( clk : in STD_LOGIC;
Port ( clk : in STD_LOGIC;
reset: in STD_LOGIC;
set : in STD_LOGIC;
inc : in STD_LOGIC;
39,23 → 39,23
architecture Behavioral of binary_counter_x16 is
signal cnt: unsigned(15 downto 0);
begin
doCountOrSet: process(clk, inc, set, set_value)
begin
if reset = '0' then
cnt <= to_unsigned(0,16);
else
if clk'event and clk = '1' then
doCountOrSet: process(clk, inc, set, set_value)
begin
if reset = '0' then
cnt <= to_unsigned(0,16);
else
if clk'event and clk = '1' then
if set = '1' then
cnt <= unsigned(set_value);
else
if inc = '1' then
cnt <= to_unsigned(to_integer(cnt) + 1, 16) ;
end if;
end if;
end if;
end if;
end process;
cnt <= unsigned(set_value);
else
if inc = '1' then
cnt <= to_unsigned(to_integer(cnt) + 1, 16) ;
end if;
end if;
end if;
end if;
end process;
count <= std_logic_vector(cnt);
end Behavioral;
 
/tb_add_sub_x16.vhd
1,6 → 1,6
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 17:35:34 11/07/2009
-- Design Name:
111,7 → 111,7
 
 
assertOperationResult(to_integer(signed(sum)), A+B, "signed sum",A+B > MAX_SIGNED or A+B < MIN_SIGNED, overflow);
 
 
assertOperationResult(to_integer(unsigned(sum)), A+B, "unsigned sum",A+B > MAX_UNSIGNED or A+B < 0, overflow);
end if;
end procedure;
/add_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 15:39:09 11/05/2009
-- Design Name:
/rdecal_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 19:21:58 11/04/2009
-- Design Name:
37,35 → 37,35
architecture BarrelShifter of rdecal_x16 is
signal din: STD_LOGIC_VECTOR (15 downto 0);
signal dout: STD_LOGIC_VECTOR (15 downto 0);
signal dout: STD_LOGIC_VECTOR (15 downto 0);
signal dec1: STD_LOGIC_VECTOR (15 downto 0);
signal dec2: STD_LOGIC_VECTOR (15 downto 0);
signal dec3: STD_LOGIC_VECTOR (15 downto 0);
signal dec3: STD_LOGIC_VECTOR (15 downto 0);
component generic_const_rdecal_x16
component generic_const_rdecal_x16
generic ( BIT_DECAL : natural range 0 to 15 );
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
en : in STD_LOGIC;
decal : out STD_LOGIC_VECTOR (15 downto 0));
decal : out STD_LOGIC_VECTOR (15 downto 0));
end component;
begin
d1 : generic_const_rdecal_x16
generic map(BIT_DECAL => 1)
d1 : generic_const_rdecal_x16
generic map(BIT_DECAL => 1)
port map( data => din, en => decal_lvl(0), decal => dec1);
d2 : generic_const_rdecal_x16
generic map(BIT_DECAL => 2)
d2 : generic_const_rdecal_x16
generic map(BIT_DECAL => 2)
port map( data => dec1, en => decal_lvl(1), decal => dec2);
d3 : generic_const_rdecal_x16
d3 : generic_const_rdecal_x16
generic map(BIT_DECAL => 4)
port map( data => dec2, en => decal_lvl(2), decal => dec3);
d4 : generic_const_rdecal_x16
d4 : generic_const_rdecal_x16
generic map(BIT_DECAL => 8)
port map( data => dec3, en => decal_lvl(3), decal => dout);
din <= data;
port map( data => dec3, en => decal_lvl(3), decal => dout);
din <= data;
decal <= dout;
end BarrelShifter;
end BarrelShifter;
/single_rdecal_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 19:34:28 11/04/2009
-- Design Name:
36,13 → 36,13
architecture Behavioral of single_rdecal_x16 is
 
begin
process(data, op)
begin
if op = '1' then
decal <= "0" & data(15 downto 1);
else
decal <= data;
end if;
process(data, op)
begin
if op = '1' then
decal <= "0" & data(15 downto 1);
else
decal <= data;
end if;
end process;
 
end Behavioral;
/generic_const_rdecal_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 14:34:40 11/05/2009
-- Design Name:
/inverser.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 19:50:24 11/04/2009
-- Design Name:
35,8 → 35,8
 
architecture Behavioral of inverser_x16 is
 
begin
process(data, inverse)
begin
process(data, inverse)
begin
if inverse = '1' then
data_out(15) <= data(0);
54,10 → 54,10
data_out(3) <= data(12);
data_out(2) <= data(13);
data_out(1) <= data(14);
data_out(0) <= data(15);
data_out(0) <= data(15);
else
data_out <= data;
end if;
data_out <= data;
end if;
end process;
 
end Behavioral;
/mini_uP_x16.vhd
1,6 → 1,6
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
 
--
-- Create Date: 16:00:40 11/08/2009
-- Design Name:
20,8 → 20,8
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
use work.ALU_INT.all;
 
---- Uncomment the following library declaration if instantiating
43,26 → 43,26
next_uP : out STD_LOGIC_VECTOR (7 downto 0));
end mini_uP_x16;
 
architecture Behavioral of mini_uP_x16 is
signal dataBus1, dataBus2: std_logic_vector(15 downto 0); -- For ALU data1 and data2
architecture Behavioral of mini_uP_x16 is
signal dataBus1, dataBus2: std_logic_vector(15 downto 0); -- For ALU data1 and data2
signal accumulator: std_logic_vector(15 downto 0);
signal mainDataBus: std_logic_vector(15 downto 0);
signal mainDataBus: std_logic_vector(15 downto 0);
signal opCode: ALU_OPCODE;
signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
signal stack_control : std_logic_vector(1 downto 0); -- en push/pop
signal PC_control : std_logic;
signal inc_PC: std_logic;
signal inc_PC: std_logic;
signal uP_id: std_logic_vector(7 downto 0);
signal watchdog_left: std_logic_vector(15 downto 0);
signal watchdog_rst_value: std_logic_vector(15 downto 0);
signal watchdog_rst: std_logic;
signal watchdog_control : std_logic_vector(1 downto 0);
signal watchdog_left: std_logic_vector(15 downto 0);
signal watchdog_rst_value: std_logic_vector(15 downto 0);
signal watchdog_rst: std_logic;
signal watchdog_control : std_logic_vector(1 downto 0);
component decoder_controler_x16
port ( clk: in std_logic;
reset: in std_logic;
75,52 → 75,52
watchdog_reset: out std_logic;
watchdog_control: out std_logic -- re we
);
end component;
component binary_counter_x16
port ( clk: in std_logic;
set: in std_logic;
set_value: in std_logic_vector(15 downto 0);
inc: in std_logic;
count: out std_logic_vector(15 downto 0));
end component;
end component;
component binary_counter_x16
port ( clk: in std_logic;
set: in std_logic;
set_value: in std_logic_vector(15 downto 0);
inc: in std_logic;
count: out std_logic_vector(15 downto 0));
end component;
component watchdog_identifier_x16
port ( clk : in std_logic;
reset : in std_logic;
prevId: in std_logic_vector(7 downto 0);
myId : out std_logic_vector(7 downto 0);
port ( clk : in std_logic;
reset : in std_logic;
prevId: in std_logic_vector(7 downto 0);
myId : out std_logic_vector(7 downto 0);
watchdog_left: out std_logic_vector(15 downto 0);
watchdog_rst_value: in std_logic_vector(15 downto 0);
watchdog_rst_value: in std_logic_vector(15 downto 0);
watchdog_rst: in std_logic);
end component;
component bus_access_x16
port ( clk: in std_logic;
en : in std_logic;
dataWrite: out std_logic_vector(15 downto 0);
dataRead : in std_logic_vector(15 downto 0));
end component;
component bus_register_x16
port ( clk: in std_logic;
re: in std_logic; -- read enable
we: in std_logic; -- write enable
reset: in std_logic;
dataport: inout std_logic_vector(15 downto 0));
end component;
component stack_x16
generic ( STACK_SIZE : natural);
port ( clk: in std_logic;
reset: in std_logic;
dataPort: inout std_logic_vector(15 downto 0);
push: in std_logic;
pop: in std_logic);
end component;
end component;
component bus_access_x16
port ( clk: in std_logic;
en : in std_logic;
dataWrite: out std_logic_vector(15 downto 0);
dataRead : in std_logic_vector(15 downto 0));
end component;
component bus_register_x16
port ( clk: in std_logic;
re: in std_logic; -- read enable
we: in std_logic; -- write enable
reset: in std_logic;
dataport: inout std_logic_vector(15 downto 0));
end component;
component stack_x16
generic ( STACK_SIZE : natural);
port ( clk: in std_logic;
reset: in std_logic;
dataPort: inout std_logic_vector(15 downto 0);
push: in std_logic;
pop: in std_logic);
end component;
component ALU
Port ( data1 : in STD_LOGIC_VECTOR (15 downto 0);
data2 : in STD_LOGIC_VECTOR (15 downto 0);
129,18 → 129,18
overflow: out STD_LOGIC );
end component;
begin
program_counter: binary_counter_x16
port map( clk => clk,
set => PC_control,
inc => inc_PC,
set_value => mainDataBus,
count => PC);
program_counter: binary_counter_x16
port map( clk => clk,
set => PC_control,
inc => inc_PC,
set_value => mainDataBus,
count => PC);
watchdog_re: bus_access_x16
port map ( clk => clk,
en => watchdog_control(1),
dataRead => mainDataBus,
dataWrite => watchdog_rst_value);
dataWrite => watchdog_rst_value);
watchdog_we: bus_access_x16
port map ( clk => clk,
147,8 → 147,8
en => watchdog_control(0),
dataRead => watchdog_left,
dataWrite => mainDataBus);
 
watchdog_id: watchdog_identifier_x16
 
watchdog_id: watchdog_identifier_x16
port map( clk => clk,
reset => reset,
prevId => prev_uP,
156,15 → 156,15
watchdog_left => watchdog_left,
watchdog_rst_value => watchdog_rst_value,
watchdog_rst => watchdog_rst);
stack: stack_x16
generic map( STACK_SIZE => 8)
port map( clk => clk,
reset => reset,
dataPort => mainDataBus,
push => stack_control(1),
pop => stack_control(0));
watchdog_rst => watchdog_rst);
stack: stack_x16
generic map( STACK_SIZE => 8)
port map( clk => clk,
reset => reset,
dataPort => mainDataBus,
push => stack_control(1),
pop => stack_control(0));
-- The 4 Registers
R1: bus_register_x16
port ( clk=>clk ,
171,7 → 171,7
re=>register_control(0),
we=>register_control(1),
reset=>reset,
dataport=> mainDataBus);
dataport=> mainDataBus);
R2: bus_register_x16
port ( clk=>clk ,
178,7 → 178,7
re=>register_control(2),
we=>register_control(3),
reset=>reset,
dataport=> mainDataBus);
dataport=> mainDataBus);
R3: bus_register_x16
port ( clk=>clk ,
185,7 → 185,7
re=>register_control(4),
we=>register_control(5),
reset=>reset,
dataport=> mainDataBus);
dataport=> mainDataBus);
R4: bus_register_x16
port ( clk=>clk ,
192,10 → 192,10
re=>register_control(6),
we=>register_control(7),
reset=>reset,
dataport=> mainDataBus);
-- The ALU
alu : ALU
dataport=> mainDataBus);
-- The ALU
alu : ALU
port( data1 => dataBus1;
data2 => dataBus2;
dataA => accumulator;

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