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URL https://opencores.org/ocsvn/distributed_intelligence/distributed_intelligence/trunk

Subversion Repositories distributed_intelligence

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    /distributed_intelligence/trunk
    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/mini_uP_x16.vhd File deleted
/ALU_INT.vhd File deleted
/tb_ALU_simple.vhd File deleted
/bus_access_x16.vhd File deleted
/tb_inverser_x16.vhd File deleted
/rdecal_x16.vhd File deleted
/binary_counter_x16.vhd File deleted
/add_x16.vhd File deleted
/inverser.vhd File deleted
/tb_single_rdecal_x16.vhd File deleted
/ALU.vhd File deleted
/tb_add_sub_x16.vhd File deleted
/registre.vhd File deleted
/MY_FUNCS.vhd File deleted
/tb_rdecal_x16.vhd File deleted
/generic_const_rdecal_x16.vhd File deleted
/single_rdecal_x16.vhd File deleted
/UnitTest.vhd File deleted
/tb_binary_counter_x16.vhd File deleted
/tb_generic_const_rdecal_x16.vhd File deleted
/sum_x16.vhd File deleted
/BENCH/tb_generic_const_rdecal_x16.vhd
0,0 → 1,112
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 22:18:23 11/04/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_generic_const_rdecal_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: generic_const_rdecal_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_generic_const_rdecal_x16 IS
END tb_generic_const_rdecal_x16;
ARCHITECTURE behavior OF tb_generic_const_rdecal_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT generic_const_rdecal_x16
GENERIC( BIT_DECAL: natural range 0 to 15);
PORT(
data : IN std_logic_vector(15 downto 0);
en : IN std_logic;
decal : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
--Inputs
signal data : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
 
--Outputs
signal decal1 : std_logic_vector(15 downto 0);
signal decal2 : std_logic_vector(15 downto 0);
signal decal3 : std_logic_vector(15 downto 0);
signal decal4 : std_logic_vector(15 downto 0);
signal decal5 : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: generic_const_rdecal_x16 generic map(BIT_DECAL => 1) PORT MAP (
data => data,
en => en,
decal => decal1
);
uut2: generic_const_rdecal_x16 generic map(BIT_DECAL => 2) PORT MAP (
data => data,
en => en,
decal => decal2
);
uut3: generic_const_rdecal_x16 generic map(BIT_DECAL => 3) PORT MAP (
data => data,
en => en,
decal => decal3
);
uut4: generic_const_rdecal_x16 generic map(BIT_DECAL => 4) PORT MAP (
data => data,
en => en,
decal => decal4
);
uut5: generic_const_rdecal_x16 generic map(BIT_DECAL => 5) PORT MAP (
data => data,
en => en,
decal => decal5
);
 
-- Stimulus process
stim_proc: process
begin
data <= x"ffff";
en <= '0';
wait for 100 ns;
en <= '1';
wait for 100 ns;
en <= '0';
wait for 100 ns;
data <= x"fafb";
en <= '0';
wait for 100 ns;
en <= '1';
wait for 100 ns;
en <= '0';
 
wait;
end process;
 
END;
/BENCH/tb_ALU_simple.vhd
0,0 → 1,303
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 14:28:28 11/04/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_ALU_simple.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UNITTEST.all;
use work.ALU_INT.all;
use work.MY_FUNCS.all;
 
ENTITY tb_ALU_simple IS
END tb_ALU_simple;
ARCHITECTURE behavior OF tb_ALU_simple IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
data1 : IN std_logic_vector(15 downto 0);
data2 : IN std_logic_vector(15 downto 0);
op : IN ALU_OPCODE;
dataA : OUT std_logic_vector(15 downto 0);
overflow: OUT std_logic
);
END COMPONENT;
 
--Inputs
signal data1 : std_logic_vector(15 downto 0) := (others => '0');
signal data2 : std_logic_vector(15 downto 0) := (others => '0');
signal op : ALU_OPCODE;
 
--Outputs
signal dataA : std_logic_vector(15 downto 0);
signal overflow: std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
data1 => data1,
data2 => data2,
dataA => dataA,
op => op,
overflow => overflow
);
 
-- Stimulus process
stim_proc: process
procedure testAdd(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
begin
 
 
if(A < 0 or B < 0) then
signe := '1';
else
signe := '0';
end if;
else
signe := argSigne;
end if;
if signe = '1' then
op <= SADD;
data1 <= std_logic_vector(to_signed(A, 16));
data2 <= std_logic_vector(to_signed(B, 16));
else
op <= UADD;
data1 <= std_logic_vector(to_unsigned(A, 16));
data2 <= std_logic_vector(to_unsigned(B, 16));
end if;
 
wait for delay;
 
 
assertOperationResult(to_integer(signed(dataA)), A+B, "signed sum", (A+B > MAX_SIGNED) or (A+B < MIN_SIGNED), overflow);
 
assertOperationResult(to_integer(unsigned(dataA)), A+B, "unsigned sum", A+B > MAX_UNSIGNED, overflow);
end if;
end procedure;
procedure testSub(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
begin
 
-- Fixe le signe
 
if(A < 0 or B < 0) then
signe := '1';
else
signe := '0';
end if;
else
signe := argSigne;
end if;
 
if signe = '1' then
op <= SSUB;
data1 <= std_logic_vector(to_signed(A, 16));
data2 <= std_logic_vector(to_signed(B, 16));
else
op <= USUB;
data1 <= std_logic_vector(to_unsigned(A, 16));
data2 <= std_logic_vector(to_unsigned(B, 16));
end if;
 
wait for delay;
 
 
assertOperationResult(to_integer(signed(dataA)), A-B, "signed subtraction", (A-B > MAX_SIGNED) or (A-B < MIN_SIGNED), overflow);
 
assertOperationResult(to_integer(unsigned(dataA)), A-B, "unsigned subtraction", (A-B > MAX_UNSIGNED) or (A-B < 0), overflow);
end if;
end procedure;
procedure testShift(A: in std_logic_vector(15 downto 0); argB: in integer; right: in std_logic := '-'; delay : in time := 50 ns) is
variable direction: std_logic;
variable B: natural;
begin
 
 
if(argB < 0) then
direction := '1';
B := -argB;
else
direction := '0';
end if;
else
direction := right;
end if;
if direction = '1' then
op <= LSHIFT;
else
op <= RSHIFT;
end if;
data1 <= A;
data2 <= std_logic_vector(to_unsigned(B, 16));
 
wait for delay;
 
if direction = '1' then -- A gauche
assertOperationResult(dataA, A sll B, "left shift", B > 15);
else -- A droite
assertOperationResult(dataA, A srl B, "right shift", B > 15);
end if;
end procedure;
procedure testBinary(A, B: in std_logic_vector(15 downto 0); delay : in time := 50 ns) is
begin
op <= bOR;
data1 <= A;
data2 <= B;
 
wait for delay;
 
assertOperationResult(dataA, A OR B, "boolean OR");
op <= bAND;
 
wait for delay;
 
assertOperationResult(dataA, A AND B, "boolean AND");
op <= bXOR;
 
wait for delay;
 
assertOperationResult(dataA, A XOR B, "boolean OR");
op <= bNOT;
 
wait for delay;
 
assertOperationResult(dataA, NOT A, "boolean NOT");
end procedure;
begin
report "TEST BEGINS";
report "Testing binary ops ...";
-- Binary ops
testBinary(x"0000",x"0000");
testBinary(x"f610",x"00ff");
testBinary(x"ffff",x"aaaa");
testBinary(x"f00f",x"aa00");
testBinary(x"eeee",x"1111");
report "Testing shiftings ...";
-- LSHIFT
testShift(x"fafb", 1);
testShift(x"fafb", 2);
testShift(x"fafb", 3);
testShift(x"fafb", 0);
testShift(x"fafb", 4);
testShift(x"fafb", 15);
testShift(x"fafb", 1);
-- RSHIFT
testShift(x"fafb", -1);
testShift(x"fafb", -2);
testShift(x"fafb", -3);
testShift(x"fafb", 0, '1');
testShift(x"fafb", -4);
testShift(x"fafb", -15);
testShift(x"fafb", -1);
report "Testing additions ...";
 
testAdd(10,15);
testAdd(5,0);
testAdd(2,30);
testAdd(MAX_UNSIGNED, 0);
testAdd(MAX_UNSIGNED-15, 15);
 
testAdd(0,-10);
testAdd(10,-10);
testAdd(11,-10);
testAdd(MAX_SIGNED, MIN_SIGNED);
-- Additions avec overflow
testAdd(MAX_UNSIGNED,1);
testAdd(MAX_UNSIGNED,MAX_UNSIGNED);
testAdd(MAX_SIGNED,MAX_SIGNED, '1');
testAdd(MIN_SIGNED, -1);
testAdd(MIN_SIGNED,MIN_SIGNED);
report "Testing subtractions ...";
 
testSub(10,9);
testSub(5,0);
testSub(2,30);
testSub(MAX_UNSIGNED, 0);
testSub(MAX_UNSIGNED-15, 15);
 
testSub(0,-10);
testSub(10,-10);
testSub(11,-10);
testSub(MAX_SIGNED, MIN_SIGNED);
testSub(MIN_SIGNED, -1);
-- Substractions avec overflow
testSub(MAX_UNSIGNED,1);
testSub(MAX_UNSIGNED,MAX_UNSIGNED);
testSub(MAX_SIGNED,MAX_SIGNED, '1');
testSub(MIN_SIGNED,MIN_SIGNED);
report "END OF TEST";
wait;
end process;
 
END;
/BENCH/tb_inverser_x16.vhd
0,0 → 1,89
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 21:54:24 11/04/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_inverser_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: inverser_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_inverser_x16 IS
END tb_inverser_x16;
ARCHITECTURE behavior OF tb_inverser_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT inverser_x16
PORT(
data : IN std_logic_vector(15 downto 0);
inverse : IN std_logic;
data_out : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
--Inputs
signal data : std_logic_vector(15 downto 0) := (others => '0');
signal inverse : std_logic := '0';
 
--Outputs
signal data_out : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: inverser_x16 PORT MAP (
data => data,
inverse => inverse,
data_out => data_out
);
 
-- Stimulus process
stim_proc: process
begin
data <= x"ff00";
inverse <= '0';
-- Init: 100 ns
wait for 100 ns;
inverse <= '1';
wait for 100 ns;
inverse <= '0';
wait for 100 ns;
data <= x"afaf";
inverse <= '0';
wait for 100 ns;
inverse <= '1';
wait for 100 ns;
inverse <= '0';
-- insert stimulus here
 
wait;
end process;
 
END;
/BENCH/tb_add_sub_x16.vhd
0,0 → 1,202
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 17:35:34 11/07/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_add_sub_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: add_sub_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UnitTest.ALL;
 
ENTITY tb_add_sub_x16 IS
END tb_add_sub_x16;
ARCHITECTURE behavior OF tb_add_sub_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT add_sub_x16
PORT(
dataA : IN std_logic_vector(15 downto 0);
dataB : IN std_logic_vector(15 downto 0);
sum : OUT std_logic_vector(15 downto 0);
is_signed : IN std_logic;
is_sub : IN std_logic;
overflow : OUT std_logic
);
END COMPONENT;
 
--Inputs
signal dataA : std_logic_vector(15 downto 0) := (others => '0');
signal dataB : std_logic_vector(15 downto 0) := (others => '0');
signal is_signed : std_logic := '0';
signal is_sub : std_logic := '0';
 
--Outputs
signal sum : std_logic_vector(15 downto 0);
signal overflow : std_logic;
constant MAX_SIGNED:integer := (2**15)-1;
constant MIN_SIGNED:integer := -(2**15);
constant MAX_UNSIGNED:integer := (2**16)-1;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: add_sub_x16 PORT MAP (
dataA => dataA,
dataB => dataB,
sum => sum,
is_signed => is_signed,
is_sub => is_sub,
overflow => overflow
);
 
-- Stimulus process
stim_proc: process
procedure testAdd(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
begin
 
 
if(A < 0 or B < 0) then
signe := '1';
else
signe := '0';
end if;
else
signe := argSigne;
end if;
is_sub <= '0';
is_signed <= signe;
if signe = '1' then
dataA <= std_logic_vector(to_signed(A, 16));
dataB <= std_logic_vector(to_signed(B, 16));
else
dataA <= std_logic_vector(to_unsigned(A, 16));
dataB <= std_logic_vector(to_unsigned(B, 16));
end if;
 
wait for delay;
 
 
assertOperationResult(to_integer(signed(sum)), A+B, "signed sum",A+B > MAX_SIGNED or A+B < MIN_SIGNED, overflow);
 
assertOperationResult(to_integer(unsigned(sum)), A+B, "unsigned sum",A+B > MAX_UNSIGNED or A+B < 0, overflow);
end if;
end procedure;
procedure testSub(A, B: in integer; argSigne: in std_logic := '-'; delay : in time := 50 ns) is
variable signe: std_logic;
begin
 
 
if(A < 0 or B < 0) then
signe := '1';
else
signe := '0';
end if;
else
signe := argSigne;
end if;
is_sub <= '1';
is_signed <= signe;
if signe = '1' then
dataA <= std_logic_vector(to_signed(A, 16));
dataB <= std_logic_vector(to_signed(B, 16));
else
dataA <= std_logic_vector(to_unsigned(A, 16));
dataB <= std_logic_vector(to_unsigned(B, 16));
end if;
 
wait for delay;
 
 
assertOperationResult(to_integer(signed(sum)), A-B, "signed subtraction", A-B > MAX_SIGNED or A-B < MIN_SIGNED, overflow);
 
assertOperationResult(to_integer(unsigned(sum)), A-B, "unsigned subtraction", A-B > MAX_UNSIGNED or A-B < 0, overflow);
end if;
end procedure;
begin
 
testAdd(10,15);
testAdd(5,0);
testAdd(2,30);
testAdd(MAX_UNSIGNED, 0);
testAdd(MAX_UNSIGNED-15, 15);
 
testAdd(0,-10);
testAdd(10,-10);
testAdd(11,-10);
testAdd(MAX_SIGNED, MIN_SIGNED);
-- Additions avec overflow
testAdd(MAX_UNSIGNED,1);
testAdd(MAX_UNSIGNED,MAX_UNSIGNED);
testAdd(MAX_SIGNED,MAX_SIGNED, '1');
testAdd(MIN_SIGNED, -1);
testAdd(MIN_SIGNED,MIN_SIGNED);
 
testSub(10,9);
testSub(5,0);
testSub(2,30);
testSub(MAX_UNSIGNED, 0);
testSub(MAX_UNSIGNED-15, 15);
 
testSub(0,-10);
testSub(10,-10);
testSub(11,-10);
testSub(MAX_SIGNED, MIN_SIGNED);
testSub(MIN_SIGNED, -1);
-- Additions avec overflow
testSub(MAX_UNSIGNED,1);
testSub(MAX_UNSIGNED,MAX_UNSIGNED);
testSub(MAX_SIGNED,MAX_SIGNED, '1');
testSub(MIN_SIGNED,MIN_SIGNED);
wait;
end process;
 
END;
/BENCH/tb_binary_counter_x16.vhd
0,0 → 1,109
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 17:02:27 11/08/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_binary_counter_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: binary_counter_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_binary_counter_x16 IS
END tb_binary_counter_x16;
ARCHITECTURE behavior OF tb_binary_counter_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT binary_counter_x16
PORT(
clk : IN std_logic;
reset : IN std_logic;
set : IN std_logic;
inc : IN std_logic;
set_value : IN std_logic_vector(15 downto 0);
count : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal set : std_logic := '0';
signal inc : std_logic := '0';
signal set_value : std_logic_vector(15 downto 0) := (others => '0');
 
--Outputs
signal count : std_logic_vector(15 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: binary_counter_x16 PORT MAP (
clk => clk,
reset => reset,
set => set,
inc => inc,
set_value => set_value,
count => count
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
reset <= '0';
-- hold reset state for 10us.
wait for 10 us;
reset <= '1';
inc <= '1';
wait for clk_period*10;
inc <= '0';
wait for clk_period*10;
set_value <= std_logic_vector(to_unsigned(2**16 - 1, 16));
set <= '1';
wait for clk_period;
set <= '0';
inc <= '1';
wait;
end process;
 
END;
/BENCH/tb_rdecal_x16.vhd
0,0 → 1,106
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 22:06:57 11/04/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_rdcal_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: rdecal_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_rdecal_x16 IS
END tb_rdecal_x16;
ARCHITECTURE behavior OF tb_rdecal_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rdecal_x16
PORT(
data : IN std_logic_vector(15 downto 0);
decal_lvl : IN std_logic_vector(3 downto 0);
decal : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
--Inputs
signal data : std_logic_vector(15 downto 0) := (others => '0');
signal decal_lvl : std_logic_vector(3 downto 0) := (others => '0');
 
--Outputs
signal decal : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rdecal_x16 PORT MAP (
data => data,
decal_lvl => decal_lvl,
decal => decal
);
stim_proc: process
begin
data <= x"fafb";
decal_lvl <= x"0";
wait for 100 ns;
decal_lvl <= x"0";
wait for 100 ns;
decal_lvl <= x"1";
wait for 100 ns;
decal_lvl <= x"2";
wait for 100 ns;
decal_lvl <= x"3";
wait for 100 ns;
decal_lvl <= x"4";
wait for 100 ns;
decal_lvl <= x"5";
wait for 100 ns;
decal_lvl <= x"6";
wait for 100 ns;
decal_lvl <= x"7";
wait for 100 ns;
decal_lvl <= x"8";
wait for 100 ns;
decal_lvl <= x"9";
wait for 100 ns;
decal_lvl <= x"a";
wait for 100 ns;
decal_lvl <= x"b";
wait for 100 ns;
decal_lvl <= x"c";
wait for 100 ns;
decal_lvl <= x"d";
wait for 100 ns;
decal_lvl <= x"e";
wait for 100 ns;
decal_lvl <= x"f";
 
wait;
end process;
 
END;
/BENCH/tb_single_rdecal_x16.vhd
0,0 → 1,87
--------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 22:18:23 11/04/2009
-- Design Name:
-- Module Name: C:/Users/microcon/tb_single_rdecal_x16.vhd
-- Project Name: microcon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: single_rdecal_x16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_single_rdecal_x16 IS
END tb_single_rdecal_x16;
ARCHITECTURE behavior OF tb_single_rdecal_x16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT single_rdecal_x16
PORT(
data : IN std_logic_vector(15 downto 0);
op : IN std_logic;
decal : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
 
--Inputs
signal data : std_logic_vector(15 downto 0) := (others => '0');
signal op : std_logic := '0';
 
--Outputs
signal decal : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: single_rdecal_x16 PORT MAP (
data => data,
op => op,
decal => decal
);
 
-- Stimulus process
stim_proc: process
begin
data <= x"ffff";
op <= '0';
wait for 100 ns;
op <= '1';
wait for 100 ns;
op <= '0';
wait for 100 ns;
data <= x"fafb";
op <= '0';
wait for 100 ns;
op <= '1';
wait for 100 ns;
op <= '0';
 
wait;
end process;
 
END;
/LIB/UnitTest.vhd
0,0 → 1,74
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
package UnitTest is
 
-- Declare constants
 
-- Declare functions and procedure
 
procedure assertEqual(current, expected: in integer; resultName: in string := "Result");
procedure assertEqual(current, expected: in std_logic; resultName: in string := "Result");
procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result");
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
procedure assertOperationResult( actual, expected : in std_logic_vector; opName: in string:= "operation"; overflowCond: boolean := false; overflowBit: std_logic := '-');
end UnitTest;
 
 
package body UnitTest is
procedure assertEqual(current, expected: in integer; resultName: in string := "Result") is
begin
assert current = expected
report resultName &" is incorrect. Expected: " & integer'image(expected) & " Current: " & integer'image(current)
severity ERROR;
end procedure;
procedure assertEqual(current, expected: in std_logic; resultName: in string := "Result") is
begin
assert current = expected
report resultName &" is incorrect. Expected: " & std_logic'image(expected) & " Current: " & std_logic'image(current)
severity ERROR;
end procedure;
 
procedure assertEqual(current, expected: in std_logic_vector; resultName: in string := "Result") is
begin
assertEqual(to_integer(unsigned(current)), to_integer(unsigned(expected)), resultName);
end procedure;
 
 
-- Automaticaly verifies that the result is correct, beeing given the boundaries of the calculator and that
-- overflow bit is correctly set in both cases
-- Arguments:
-- actual, expected: Actual and expected results
-- opName: Name of the operation
-- overflowCond: Condition for an overflow, ignored by default
-- overflowBit: Overflow bit set to 1 in case of overflow, no verification if set to '-' (default)
procedure assertOperationResult( actual, expected : in integer; opName: in string:= "operation";
overflowCond: boolean := false; overflowBit: std_logic := '-') is
begin
if overflowCond then
if overflowBit /= '-' then
assertEqual(overflowBit, '1', "Overflow bit for " & opName & " with result " & integer'image(actual));
end if;
else
if overflowBit /= '-' then
assertEqual(overflowBit, '0', "Overflow bit for " & opName & " with result " & integer'image(actual));
end if;
assertEqual(actual, expected , opName & " result");
end if;
end procedure;
procedure assertOperationResult( actual, expected : in std_logic_vector; opName: in string:= "operation";
overflowCond: boolean := false; overflowBit: std_logic := '-') is
begin
assertOperationResult(to_integer(unsigned(actual)), to_integer(unsigned(expected)), opName, overflowCond, overflowBit);
end procedure;
end UnitTest;
/LIB/MY_FUNCS.vhd
0,0 → 1,38
-- Package File Template
--
-- Purpose: This package defines useful functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package MY_FUNCS is
 
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector;
function "srl"(val : std_logic_vector; shift : integer) return std_logic_vector;
end MY_FUNCS;
 
 
package body MY_FUNCS is
function "sll"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift > 0) then
for i in 1 to shift loop
ret := ret(val'high - 1 downto val'low) & '0';
end loop;
end if;
return ret;
end;
function "srl"(val : std_logic_vector; shift : integer) return std_logic_vector is
variable ret : std_logic_vector(val'range) := val;
begin
if (shift > 0) then
for i in 1 to shift loop
ret := '0' & ret(val'high downto val'low + 1) ;
end loop;
end if;
return ret;
end;
end MY_FUNCS;
/LIB/ALU_INT.vhd
0,0 → 1,21
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package ALU_INT is
type ALU_OPCODE is (bXOR, bAND, bOR, bNOT, SADD, UADD, SSUB, USUB, LSHIFT, RSHIFT, NOP);
constant MAX_SIGNED:integer := (2**15)-1;
constant MIN_SIGNED:integer := -(2**15);
constant MAX_UNSIGNED:integer := (2**16)-1;
end ALU_INT;
 
package body ALU_INT is
end ALU_INT;
 
/SRC/binary_counter_x16.vhd
0,0 → 1,61
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 16:51:22 11/08/2009
-- Design Name:
-- Module Name: binary_counter_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity binary_counter_x16 is
Port ( clk : in STD_LOGIC;
reset: in STD_LOGIC;
set : in STD_LOGIC;
inc : in STD_LOGIC;
set_value : in STD_LOGIC_VECTOR (15 downto 0);
count : out STD_LOGIC_VECTOR (15 downto 0));
end binary_counter_x16;
 
architecture Behavioral of binary_counter_x16 is
signal cnt: unsigned(15 downto 0);
begin
doCountOrSet: process(clk, inc, set, set_value)
begin
if reset = '0' then
cnt <= to_unsigned(0,16);
else
if clk'event and clk = '1' then
if set = '1' then
cnt <= unsigned(set_value);
else
if inc = '1' then
cnt <= to_unsigned(to_integer(cnt) + 1, 16) ;
end if;
end if;
end if;
end if;
end process;
count <= std_logic_vector(cnt);
end Behavioral;
 
/SRC/ALU.vhd
0,0 → 1,149
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 14:12:50 11/04/2009
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ALU_INT.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
 
entity ALU is
Port ( data1 : in STD_LOGIC_VECTOR (15 downto 0);
data2 : in STD_LOGIC_VECTOR (15 downto 0);
dataA : out STD_LOGIC_VECTOR (15 downto 0);
op : in ALU_OPCODE;
overflow: out STD_LOGIC );
end ALU;
 
architecture Behavioral of ALU is
signal preA : STD_LOGIC_VECTOR(15 downto 0);
signal rdecal_in : STD_LOGIC_VECTOR(15 downto 0);
signal rdecal_out : STD_LOGIC_VECTOR(15 downto 0);
signal decal : STD_LOGIC_VECTOR(15 downto 0);
signal decal_l : STD_LOGIC;
signal signed_op : STD_LOGIC;
signal sub_op : std_logic;
signal sum : STD_LOGIC_VECTOR(15 downto 0);
component rdecal_x16
port ( data : in STD_LOGIC_VECTOR(15 downto 0);
decal_lvl : in STD_LOGIC_VECTOR(3 downto 0);
decal : out STD_LOGIC_VECTOR(15 downto 0));
end component;
component inverser_x16
port ( data : in STD_LOGIC_VECTOR(15 downto 0);
inverse : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(15 downto 0));
end component;
COMPONENT add_sub_x16
PORT(
dataA : IN std_logic_vector(15 downto 0);
dataB : IN std_logic_vector(15 downto 0);
is_signed : IN std_logic;
is_sub : IN std_logic;
sum : OUT std_logic_vector(15 downto 0);
overflow : OUT std_logic
);
END COMPONENT;
 
begin
dataA <= preA;
id1 : inverser_x16 port map( data => data1,
inverse => decal_l,
data_out => rdecal_in);
d1: rdecal_x16 port map( data => rdecal_in,
decal_lvl => data2(3 downto 0),
decal => rdecal_out);
id2 : inverser_x16 port map( data => rdecal_out,
inverse => decal_l,
data_out => decal);
summator: add_sub_x16 PORT MAP(
dataA => data1,
dataB => data2,
sum => sum,
is_signed => signed_op,
is_sub => sub_op,
overflow => overflow
);
makeOp: process(op, data1, data2, decal, sum)
begin
decal_l <= '-';
sub_op <= '-';
signed_op <= '-';
-- Logic op
case op is
--bXOR, bAND, , SADD, UADD, SSUB, USUB, LSHIFT, RSHIFT
when bOR => -- OR
preA <= data1 OR data2;
when bAND => -- AND
preA <= data1 AND data2;
when bXOR => -- XOR
preA <= data1 XOR data2;
when bNOT =>
preA <= NOT data1 ;
-- Shifting op
when RSHIFT => -- RSHIFT
preA <= decal;
decal_l <= '0';
when LSHIFT => -- LSHIFT
preA <= decal;
decal_l <= '1';
-- Signed op
when SADD => -- SADD signed ADD
signed_op <= '1';
sub_op <= '0';
preA <= sum;
when SSUB => -- SSUB signed SUB da = d1 - d2
signed_op <= '1';
sub_op <= '1';
preA <= sum;
-- Unsigned op
when UADD => -- UADD unsigned ADD
signed_op <= '0';
sub_op <= '0';
preA <= sum;
when USUB => -- USUB unsigned SUB da = d1 - d2
signed_op <= '0';
sub_op <= '1';
preA <= sum;
when others => -- NOP
preA <= (others => '-');
end case;
end process;
end Behavioral;
 
/SRC/sum_x16.vhd
0,0 → 1,84
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 21:11:24 11/05/2009
-- Design Name:
-- Module Name: add_sub_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity add_sub_x16 is
Port ( dataA : in STD_LOGIC_VECTOR (15 downto 0);
dataB : in STD_LOGIC_VECTOR (15 downto 0);
sum : out STD_LOGIC_VECTOR (15 downto 0);
is_signed : in STD_LOGIC;
is_sub : IN std_logic;
overflow : out STD_LOGIC);
end add_sub_x16;
 
architecture Behavioral of add_sub_x16 is
signal sresult : SIGNED (16 downto 0);
signal uresult : UNSIGNED (16 downto 0);
signal tRes: std_logic_vector (16 downto 0); -- somme sur 17 bits
begin
doAddSub: process (is_sub, is_signed, dataA, dataB)
begin
uresult <=(others => '-');
sresult <=(others => '-');
if is_signed = '0' then
if is_sub = '0' then
uresult <= unsigned('0' & dataA) + unsigned('0' & dataB);
else
uresult <= unsigned('0' & dataA) - unsigned('0' & dataB);
end if;
else
if is_sub = '0' then
sresult <= signed(dataA(15) & dataA) + signed(dataB(15) & dataB);
else
sresult <= signed(dataA(15) & dataA) - signed(dataB(15) & dataB);
end if;
end if;
end process;
setTRes: process (is_signed, uresult, sresult)
begin
if is_signed = '1' then
tRes <= std_logic_vector(sresult);
else
tRes <= std_logic_vector(uresult);
end if;
end process;
sum <= tRes(15 downto 0);
set_overflow_bit: process(is_signed, is_sub, tRes)
begin
if is_signed = '1' then
overflow <= tRes(16) xor tRes(15);
else
overflow <= tRes(16);
end if;
end process;
 
end Behavioral;
/SRC/registre.vhd
0,0 → 1,127
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file registre.vhd when simulating
-- the core, registre. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
 
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY registre IS
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
ssra: IN std_logic;
douta: OUT std_logic_VECTOR(0 downto 0));
END registre;
 
ARCHITECTURE registre_a OF registre IS
-- synthesis translate_off
component wrapped_registre
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(3 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
ssra: IN std_logic;
douta: OUT std_logic_VECTOR(0 downto 0));
end component;
 
-- Configuration specification
for all : wrapped_registre use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_prim_type => 1,
c_sinita_val => "0",
c_read_width_b => 1,
c_family => "spartan3",
c_read_width_a => 1,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "READ_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3",
c_has_mem_output_regs_a => 0,
c_write_depth_b => 16,
c_write_depth_a => 16,
c_has_ssrb => 0,
c_has_mux_output_regs_b => 0,
c_has_ssra => 1,
c_has_mux_output_regs_a => 0,
c_addra_width => 4,
c_addrb_width => 4,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 1,
c_write_width_a => 1,
c_read_depth_b => 16,
c_read_depth_a => 16,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_use_ramb16bwer_rst_bhv => 0,
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_registre
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
ssra => ssra,
douta => douta);
-- synthesis translate_on
 
END registre_a;
 
/SRC/add_x16.vhd
0,0 → 1,42
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 15:39:09 11/05/2009
-- Design Name:
-- Module Name: add_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity add_x16 is
Port ( data1 : in STD_LOGIC_VECTOR (15 downto 0);
data2 : in STD_LOGIC_VECTOR (15 downto 0);
sum : out STD_LOGIC_VECTOR (15 downto 0);
carry : out STD_LOGIC);
end add_x16;
 
architecture Behavioral of add_x16 is
 
begin
end Behavioral;
 
/SRC/bus_access_x16.vhd
0,0 → 1,51
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 16:48:27 11/08/2009
-- Design Name:
-- Module Name: bus_access_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity bus_access_x16 is
Port ( clk : in STD_LOGIC;
en : in STD_LOGIC;
dataRead : in STD_LOGIC_VECTOR (15 downto 0);
dataWrite : out STD_LOGIC_VECTOR (15 downto 0));
end bus_access_x16;
 
architecture Behavioral of bus_access_x16 is
 
begin
process(clk, en, dataRead)
begin
if clk'event and clk = '1' then
if en = '1' then
dataWrite <= dataRead;
else
dataWrite <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;
 
/SRC/rdecal_x16.vhd
0,0 → 1,71
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 19:21:58 11/04/2009
-- Design Name:
-- Module Name: rdecal_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity rdecal_x16 is
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
decal_lvl : in STD_LOGIC_VECTOR (3 downto 0);
decal : out STD_LOGIC_VECTOR (15 downto 0));
end rdecal_x16;
 
 
architecture BarrelShifter of rdecal_x16 is
signal din: STD_LOGIC_VECTOR (15 downto 0);
signal dout: STD_LOGIC_VECTOR (15 downto 0);
signal dec1: STD_LOGIC_VECTOR (15 downto 0);
signal dec2: STD_LOGIC_VECTOR (15 downto 0);
signal dec3: STD_LOGIC_VECTOR (15 downto 0);
component generic_const_rdecal_x16
generic ( BIT_DECAL : natural range 0 to 15 );
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
en : in STD_LOGIC;
decal : out STD_LOGIC_VECTOR (15 downto 0));
end component;
begin
d1 : generic_const_rdecal_x16
generic map(BIT_DECAL => 1)
port map( data => din, en => decal_lvl(0), decal => dec1);
d2 : generic_const_rdecal_x16
generic map(BIT_DECAL => 2)
port map( data => dec1, en => decal_lvl(1), decal => dec2);
d3 : generic_const_rdecal_x16
generic map(BIT_DECAL => 4)
port map( data => dec2, en => decal_lvl(2), decal => dec3);
d4 : generic_const_rdecal_x16
generic map(BIT_DECAL => 8)
port map( data => dec3, en => decal_lvl(3), decal => dout);
din <= data;
decal <= dout;
end BarrelShifter;
/SRC/single_rdecal_x16.vhd
0,0 → 1,49
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 19:34:28 11/04/2009
-- Design Name:
-- Module Name: single_rdecal_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity single_rdecal_x16 is
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
op : in STD_LOGIC ;
decal : out STD_LOGIC_VECTOR (15 downto 0));
end single_rdecal_x16;
 
architecture Behavioral of single_rdecal_x16 is
 
begin
process(data, op)
begin
if op = '1' then
decal <= "0" & data(15 downto 1);
else
decal <= data;
end if;
end process;
 
end Behavioral;
 
/SRC/generic_const_rdecal_x16.vhd
0,0 → 1,52
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 14:34:40 11/05/2009
-- Design Name:
-- Module Name: generic_const_rdecal_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity generic_const_rdecal_x16 is
generic
(
BIT_DECAL : natural range 0 to 15
);
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
en : in STD_LOGIC;
decal : out STD_LOGIC_VECTOR (15 downto 0));
end generic_const_rdecal_x16;
 
architecture Behavioral of generic_const_rdecal_x16 is
constant PADDING: STD_LOGIC_VECTOR(0 to BIT_DECAL-1) := (others => '0');
begin
process(data, en)
begin
if en = '1' then
decal <= PADDING & data(15 downto BIT_DECAL);
else
decal <= data;
end if;
end process;
end Behavioral;
 
/SRC/inverser.vhd
0,0 → 1,64
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 19:50:24 11/04/2009
-- Design Name:
-- Module Name: inverser_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity inverser_x16 is
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
inverse : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (15 downto 0));
end inverser_x16;
 
architecture Behavioral of inverser_x16 is
 
begin
process(data, inverse)
begin
if inverse = '1' then
data_out(15) <= data(0);
data_out(14) <= data(1);
data_out(13) <= data(2);
data_out(12) <= data(3);
data_out(11) <= data(4);
data_out(10) <= data(5);
data_out(9) <= data(6);
data_out(8) <= data(7);
data_out(7) <= data(8);
data_out(6) <= data(9);
data_out(5) <= data(10);
data_out(4) <= data(11);
data_out(3) <= data(12);
data_out(2) <= data(13);
data_out(1) <= data(14);
data_out(0) <= data(15);
else
data_out <= data;
end if;
end process;
 
end Behavioral;
 
/SRC/mini_uP_x16.vhd
0,0 → 1,206
----------------------------------------------------------------------------------
-- Company:
 
--
-- Create Date: 16:00:40 11/08/2009
-- Design Name:
-- Module Name: mini_uP_x16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
use work.ALU_INT.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity mini_uP_x16 is
Port ( Code : in STD_LOGIC_VECTOR (15 downto 0);
PC : out STD_LOGIC_VECTOR (15 downto 0);
SR : out STD_LOGIC_VECTOR (15 downto 0);
MemBuffer : inout STD_LOGIC_VECTOR (15 downto 0);
MemAddress : out STD_LOGIC_VECTOR (15 downto 0);
MemState : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
sleep : in STD_LOGIC;
prev_uP : in STD_LOGIC_VECTOR (7 downto 0);
next_uP : out STD_LOGIC_VECTOR (7 downto 0));
end mini_uP_x16;
 
architecture Behavioral of mini_uP_x16 is
signal dataBus1, dataBus2: std_logic_vector(15 downto 0); -- For ALU data1 and data2
signal accumulator: std_logic_vector(15 downto 0);
signal mainDataBus: std_logic_vector(15 downto 0);
signal opCode: ALU_OPCODE;
signal register_control: std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
signal stack_control : std_logic_vector(1 downto 0); -- en push/pop
signal PC_control : std_logic;
signal inc_PC: std_logic;
signal uP_id: std_logic_vector(7 downto 0);
signal watchdog_left: std_logic_vector(15 downto 0);
signal watchdog_rst_value: std_logic_vector(15 downto 0);
signal watchdog_rst: std_logic;
signal watchdog_control : std_logic_vector(1 downto 0);
component decoder_controler_x16
port ( clk: in std_logic;
reset: in std_logic;
code: in std_logic_vector(15 downto 0);
opCode: out ALU_OPCODE;
register_control: out std_logic_vector(7 downto 0); -- re1 we1 re2 we2 re3 we3 re4 we4
stack_control : out std_logic_vector(1 downto 0); -- en push/pop
PC_control : out std_logic;
inc_PC: out std_logic;
watchdog_reset: out std_logic;
watchdog_control: out std_logic -- re we
);
end component;
component binary_counter_x16
port ( clk: in std_logic;
set: in std_logic;
set_value: in std_logic_vector(15 downto 0);
inc: in std_logic;
count: out std_logic_vector(15 downto 0));
end component;
component watchdog_identifier_x16
port ( clk : in std_logic;
reset : in std_logic;
prevId: in std_logic_vector(7 downto 0);
myId : out std_logic_vector(7 downto 0);
watchdog_left: out std_logic_vector(15 downto 0);
watchdog_rst_value: in std_logic_vector(15 downto 0);
watchdog_rst: in std_logic);
end component;
component bus_access_x16
port ( clk: in std_logic;
en : in std_logic;
dataWrite: out std_logic_vector(15 downto 0);
dataRead : in std_logic_vector(15 downto 0));
end component;
component bus_register_x16
port ( clk: in std_logic;
re: in std_logic; -- read enable
we: in std_logic; -- write enable
reset: in std_logic;
dataport: inout std_logic_vector(15 downto 0));
end component;
component stack_x16
generic ( STACK_SIZE : natural);
port ( clk: in std_logic;
reset: in std_logic;
dataPort: inout std_logic_vector(15 downto 0);
push: in std_logic;
pop: in std_logic);
end component;
component ALU
Port ( data1 : in STD_LOGIC_VECTOR (15 downto 0);
data2 : in STD_LOGIC_VECTOR (15 downto 0);
dataA : out STD_LOGIC_VECTOR (15 downto 0);
op : in ALU_OPCODE;
overflow: out STD_LOGIC );
end component;
begin
program_counter: binary_counter_x16
port map( clk => clk,
set => PC_control,
inc => inc_PC,
set_value => mainDataBus,
count => PC);
watchdog_re: bus_access_x16
port map ( clk => clk,
en => watchdog_control(1),
dataRead => mainDataBus,
dataWrite => watchdog_rst_value);
watchdog_we: bus_access_x16
port map ( clk => clk,
en => watchdog_control(0),
dataRead => watchdog_left,
dataWrite => mainDataBus);
 
watchdog_id: watchdog_identifier_x16
port map( clk => clk,
reset => reset,
prevId => prev_uP,
myId => uP_id,
watchdog_left => watchdog_left,
watchdog_rst_value => watchdog_rst_value,
watchdog_rst => watchdog_rst);
stack: stack_x16
generic map( STACK_SIZE => 8)
port map( clk => clk,
reset => reset,
dataPort => mainDataBus,
push => stack_control(1),
pop => stack_control(0));
-- The 4 Registers
R1: bus_register_x16
port ( clk=>clk ,
re=>register_control(0),
we=>register_control(1),
reset=>reset,
dataport=> mainDataBus);
R2: bus_register_x16
port ( clk=>clk ,
re=>register_control(2),
we=>register_control(3),
reset=>reset,
dataport=> mainDataBus);
R3: bus_register_x16
port ( clk=>clk ,
re=>register_control(4),
we=>register_control(5),
reset=>reset,
dataport=> mainDataBus);
R4: bus_register_x16
port ( clk=>clk ,
re=>register_control(6),
we=>register_control(7),
reset=>reset,
dataport=> mainDataBus);
-- The ALU
alu : ALU
port( data1 => dataBus1;
data2 => dataBus2;
dataA => accumulator;
op => op;
overflow => overflow);
 
end Behavioral;
 
/.
. Property changes : Modified: svn:ignore ## -1,5 +1,10 ## -dataMem.vhd +/* +_xmsgs +bak +microcon_xdb netgen templates tmp +work xlnx_auto_0_xdb +xst

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