URL
https://opencores.org/ocsvn/dma_ahb/dma_ahb/trunk
Subversion Repositories dma_ahb
Compare Revisions
- This comparison shows the changes necessary to convert path
/dma_ahb/trunk
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/src/dma_ahb32/dma_ahb32_core0_ch_offsets.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_channels_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_reg.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_joint_stall.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_reg.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_reg_params.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_rawstat.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_channels.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_fifo.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/filelist.txt
0,0 → 1,46
|
dma_ahb32.v |
dma_ahb32_dual_core.v |
dma_ahb32_apb_mux.v |
dma_ahb32_reg.v |
dma_ahb32_reg_core0.v |
prgen_scatter8_1.v |
dma_ahb32_core0_top.v |
dma_ahb32_core0.v |
dma_ahb32_core0_wdt.v |
dma_ahb32_core0_arbiter.v |
dma_ahb32_core0_ctrl.v |
dma_ahb32_core0_ahbm_wr.v |
prgen_joint_stall.v |
prgen_fifo.v |
prgen_stall.v |
dma_ahb32_core0_ahbm_timeout.v |
dma_ahb32_core0_ahbm_rd.v |
dma_ahb32_core0_channels.v |
dma_ahb32_core0_channels_apb_mux.v |
dma_ahb32_core0_channels_mux.v |
prgen_or8.v |
prgen_mux8.v |
prgen_demux8.v |
dma_ahb32_core0_ch.v |
dma_ahb32_core0_ch_reg.v |
dma_ahb32_core0_ch_reg_size.v |
prgen_rawstat.v |
dma_ahb32_core0_ch_offsets.v |
dma_ahb32_core0_ch_remain.v |
dma_ahb32_core0_ch_outs.v |
dma_ahb32_core0_ch_calc.v |
dma_ahb32_core0_ch_calc_addr.v |
dma_ahb32_core0_ch_calc_size.v |
prgen_min3.v |
prgen_min2.v |
dma_ahb32_core0_ch_calc_joint.v |
dma_ahb32_core0_ch_periph_mux.v |
dma_ahb32_core0_ch_fifo_ctrl.v |
dma_ahb32_core0_ch_wr_slicer.v |
prgen_swap_32.v |
dma_ahb32_core0_ch_rd_slicer.v |
dma_ahb32_core0_ch_fifo_ptr.v |
dma_ahb32_core0_ch_fifo.v |
dma_ahb32_core0_ch_empty.v |
prgen_delay.v |
/src/dma_ahb32/dma_ahb32_core0_wdt.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_wr_slicer.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_apb_mux.v
1,65 → 1,93
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
//-- Invoked Fri Mar 25 23:31:21 2011 |
//-- |
//-- Source file: dma_apb_mux.v |
//--------------------------------------------------------- |
|
|
|
module dma_ahb32_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg); |
|
input clk; |
input reset; |
|
input pclken; |
input psel; |
input penable; |
input pwrite; |
input [12:11] paddr; |
output [31:0] prdata; |
output pslverr; |
output pready; |
|
output psel0; |
input [31:0] prdata0; |
input pslverr0; |
|
output psel1; |
input [31:0] prdata1; |
input pslverr1; |
|
output psel_reg; |
input [31:0] prdata_reg; |
input pslverr_reg; |
|
wire [31:0] prdata_pre; |
wire pslverr_pre; |
|
|
reg pready; |
|
|
assign psel0 = pclken & psel & (paddr[12:11] == 2'b00); |
assign psel1 = pclken & psel & (paddr[12:11] == 2'b01); |
assign psel_reg = pclken & psel & (paddr[12] == 1'b1); |
|
assign prdata_pre = prdata0 | prdata1 | prdata_reg; |
assign pslverr_pre = pslverr0 | pslverr1 | pslverr_reg; |
|
assign prdata = prdata_pre; |
assign pslverr = pslverr_pre; |
|
|
always @(posedge clk or posedge reset) |
if (reset) |
pready <= #1 1'b0; |
else if (pclken) |
pready <= #1 psel & (~penable); |
|
|
endmodule |
|
|
|
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
//-- Invoked Fri Mar 25 23:31:21 2011 |
//-- |
//-- Source file: dma_apb_mux.v |
//--------------------------------------------------------- |
|
|
|
module dma_ahb32_apb_mux (clk,reset,pclken,psel,penable,pwrite,paddr,prdata,pslverr,pready,psel0,prdata0,pslverr0,psel1,prdata1,pslverr1,psel_reg,prdata_reg,pslverr_reg); |
|
input clk; |
input reset; |
|
input pclken; |
input psel; |
input penable; |
input pwrite; |
input [12:11] paddr; |
output [31:0] prdata; |
output pslverr; |
output pready; |
|
output psel0; |
input [31:0] prdata0; |
input pslverr0; |
|
output psel1; |
input [31:0] prdata1; |
input pslverr1; |
|
output psel_reg; |
input [31:0] prdata_reg; |
input pslverr_reg; |
|
wire [31:0] prdata_pre; |
wire pslverr_pre; |
|
|
reg pready; |
|
|
assign psel0 = pclken & psel & (paddr[12:11] == 2'b00); |
assign psel1 = pclken & psel & (paddr[12:11] == 2'b01); |
assign psel_reg = pclken & psel & (paddr[12] == 1'b1); |
|
assign prdata_pre = prdata0 | prdata1 | prdata_reg; |
assign pslverr_pre = pslverr0 | pslverr1 | pslverr_reg; |
|
assign prdata = prdata_pre; |
assign pslverr = pslverr_pre; |
|
|
always @(posedge clk or posedge reset) |
if (reset) |
pready <= #1 1'b0; |
else if (pclken) |
pready <= #1 psel & (~penable); |
|
|
endmodule |
|
|
|
/src/dma_ahb32/dma_ahb32_core0_ctrl.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_outs.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_dual_core.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_calc_addr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_min2.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_min3.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_calc.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_reg_core0.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ahbm_timeout.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_calc_joint.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ahbm_wr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_scatter8_1.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_swap_32.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_fifo_ptr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_defines.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_remain.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_fifo.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_arbiter.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_periph_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ahbm_rd.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_delay.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_top.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_ch_reg_params.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_mux8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_channels_apb_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_calc_size.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_empty.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_or8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_demux8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_rd_slicer.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_reg_size.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/dma_ahb32_core0_ch_fifo_ctrl.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb32/prgen_stall.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ahbm_wr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_calc_joint.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_rd_slicer.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_joint_stall.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_fifo_ctrl.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_swap_64.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_fifo_ptr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_offsets.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_rawstat.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_channels_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_remain.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_defines.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_reg.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/filelist.txt
0,0 → 1,47
|
dma_ahb64.v |
dma_ahb64_dual_core.v |
dma_ahb64_apb_mux.v |
dma_ahb64_reg.v |
dma_ahb64_reg_core0.v |
prgen_scatter8_1.v |
dma_ahb64_core0_top.v |
dma_ahb64_core0.v |
dma_ahb64_core0_wdt.v |
dma_ahb64_core0_arbiter.v |
dma_ahb64_core0_ctrl.v |
dma_ahb64_core0_ahbm_wr.v |
prgen_joint_stall.v |
prgen_fifo.v |
prgen_stall.v |
dma_ahb64_core0_ahbm_timeout.v |
dma_ahb64_core0_ahbm_rd.v |
dma_ahb64_core0_channels.v |
dma_ahb64_core0_channels_apb_mux.v |
dma_ahb64_core0_channels_mux.v |
prgen_or8.v |
prgen_mux8.v |
prgen_demux8.v |
dma_ahb64_core0_ch.v |
dma_ahb64_core0_ch_reg.v |
dma_ahb64_core0_ch_reg_size.v |
prgen_rawstat.v |
dma_ahb64_core0_ch_offsets.v |
dma_ahb64_core0_ch_remain.v |
dma_ahb64_core0_ch_outs.v |
dma_ahb64_core0_ch_calc.v |
dma_ahb64_core0_ch_calc_addr.v |
dma_ahb64_core0_ch_calc_size.v |
prgen_min3.v |
prgen_min2.v |
dma_ahb64_core0_ch_calc_joint.v |
dma_ahb64_core0_ch_periph_mux.v |
dma_ahb64_core0_ch_fifo_ctrl.v |
dma_ahb64_core0_ch_wr_slicer.v |
prgen_swap_64.v |
prgen_swap_32.v |
dma_ahb64_core0_ch_rd_slicer.v |
dma_ahb64_core0_ch_fifo_ptr.v |
dma_ahb64_core0_ch_fifo.v |
dma_ahb64_core0_ch_empty.v |
prgen_delay.v |
/src/dma_ahb64/dma_ahb64.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_arbiter.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_reg_params.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_periph_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_channels.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ahbm_rd.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_ch_reg_params.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_top.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_min2.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_wr_slicer.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_min3.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ctrl.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_calc_addr.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_scatter8_1.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_swap_32.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ahbm_timeout.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_reg_size.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_fifo.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_reg.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_delay.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_fifo.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_wdt.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_mux8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_apb_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_outs.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_dual_core.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_channels_apb_mux.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_calc_size.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_or8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_empty.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_demux8.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_core0_ch_calc.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/dma_ahb64_reg_core0.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |
/src/dma_ahb64/prgen_stall.v
1,3 → 1,31
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//--------------------------------------------------------- |
//-- File generated by RobustVerilog parser |
//-- Version: 1.0 |