URL
https://opencores.org/ocsvn/dmt_tx/dmt_tx/trunk
Subversion Repositories dmt_tx
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- This comparison shows the changes necessary to convert path
/dmt_tx/trunk/myhdl/rtl
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/queue.py
0,0 → 1,59
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from myhdl import * |
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def queue(clk, reset, shift, d_i, d_o, qlen=3): |
'''Queue of specified length consists of registers that will shift |
their content and enter input data when the shift signal is activ. |
When inactive content of the current registers will be kept. |
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I/O pins: |
========= |
clk : shifting and registering input data happens synchronous to |
the clock signal |
reset : reset all registers to 0 |
shift : input data at d_i will be registered to the first register |
and content of each register will be shifted to the next |
register. The content of the last register will be dropped |
d_i : input data, will be registered to the first register if |
the shift signal is active |
d_o : output data, resembles the data of the last register |
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parameter: |
========== |
qlen : number of registers in the queue |
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''' |
m = 2**(len(d_i)-1) |
chain = [Signal(intbv(0, min=-m, max=m)) for i in range(qlen-1)] |
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reg_inst = [None for i in range(qlen)] |
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for i in range(qlen): |
if i == 0: |
reg_inst[i] = simple_reg(clk, reset, shift, d_i, chain[i]) |
elif i > 0 and i < (qlen-1): |
reg_inst[i] = simple_reg(clk, reset, shift, chain[i-1], chain[i]) |
elif i == (qlen-1): |
reg_inst[i] = simple_reg(clk, reset, shift, chain[i-1], d_o) |
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return instances() |
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def simple_reg(clk, reset, w_en, d_i, d_o): |
'''Simple register is the unit of the queue. It will register the |
input when w_en is active, remain the current value on inactive w_en |
and reset the value on active reset. |
''' |
@always (clk.posedge) |
def reg_logic(): |
if reset == 1: |
d_o.next = 0 |
else: |
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if w_en: |
d_o.next = d_i |
else: |
d_o.next = d_o |
return instances() |