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  • This comparison shows the changes necessary to convert path 
    /eco32/tags/eco32-0.22/stdalone/onetask/os
    from Rev 18 to Rev 21
    ↔ Reverse comparison
  •

Rev 18 → Rev 21

/start.h
0,0 → 1,21
/*
* start.h -- startup code
*/
 
 
#ifndef _START_H_
#define _START_H_
 
 
typedef void (*ISR)(int irq, unsigned int *registers);
 
 
void enable(void);
void disable(void);
ISR getISR(int irq);
void setISR(int irq, ISR isr);
void startTask(unsigned int physStackTop);
void setTLB(int index, unsigned int entryHi, unsigned int entryLo);
 
 
#endif /* _START_H_ */
/main.c
0,0 → 1,250
/*
* main.c -- start the ball rolling
*/
 
 
#include "stdarg.h"
#include "start.h"
 
 
/**************************************************************/
 
 
unsigned char taskCode[] = {
#include "task.dump"
};
 
 
/**************************************************************/
 
 
void putchar(char c) {
unsigned int *base;
 
if (c == '\n') {
putchar('\r');
}
base = (unsigned int *) 0xF0300000;
while ((*(base + 2) & 1) == 0) ;
*(base + 3) = c;
}
 
 
void puts(char *s) {
char c;
 
while ((c = *s++) != '\0') {
putchar(c);
}
}
 
 
void printn(int n) {
int a;
 
if (n < 0) {
putchar('-');
n = -n;
}
a = n / 10;
if (a != 0) {
printn(a);
}
putchar(n % 10 + '0');
}
 
 
void printu(unsigned int n, unsigned int b) {
unsigned int a;
 
a = n / b;
if (a != 0) {
printu(a, b);
}
putchar("0123456789ABCDEF"[n % b]);
}
 
 
void printf(char *fmt, ...) {
va_list ap;
char c;
int n;
unsigned int u;
char *s;
 
va_start(ap, fmt);
while (1) {
while ((c = *fmt++) != '%') {
if (c == '\0') {
va_end(ap);
return;
}
putchar(c);
}
c = *fmt++;
if (c == 'd') {
n = va_arg(ap, int);
printn(n);
} else
if (c == 'u' || c == 'o' || c == 'x') {
u = va_arg(ap, int);
printu(u, c == 'o' ? 8 : (c == 'x' ? 16 : 10));
} else
if (c == 's') {
s = va_arg(ap, char *);
puts(s);
} else {
putchar(c);
}
}
}
 
 
/**************************************************************/
 
 
static char *exceptionCause[32] = {
/* 00 */ "terminal 0 transmitter interrupt",
/* 01 */ "terminal 0 receiver interrupt",
/* 02 */ "terminal 1 transmitter interrupt",
/* 03 */ "terminal 1 receiver interrupt",
/* 04 */ "keyboard interrupt",
/* 05 */ "unknown interrupt",
/* 06 */ "unknown interrupt",
/* 07 */ "unknown interrupt",
/* 08 */ "disk interrupt",
/* 09 */ "unknown interrupt",
/* 10 */ "unknown interrupt",
/* 11 */ "unknown interrupt",
/* 12 */ "unknown interrupt",
/* 13 */ "unknown interrupt",
/* 14 */ "timer interrupt",
/* 15 */ "unknown interrupt",
/* 16 */ "bus timeout exception",
/* 17 */ "illegal instruction exception",
/* 18 */ "privileged instruction exception",
/* 19 */ "divide instruction exception",
/* 20 */ "trap instruction exception",
/* 21 */ "TLB miss exception",
/* 22 */ "TLB write exception",
/* 23 */ "TLB invalid exception",
/* 24 */ "illegal address exception",
/* 25 */ "privileged address exception",
/* 26 */ "unknown exception",
/* 27 */ "unknown exception",
/* 28 */ "unknown exception",
/* 29 */ "unknown exception",
/* 30 */ "unknown exception",
/* 31 */ "unknown exception"
};
 
 
void defaultISR(int irq, unsigned int *registers) {
printf("\n%s\n", exceptionCause[irq]);
}
 
 
void initInterrupts(void) {
int i;
 
for (i = 0; i < 32; i++) {
setISR(i, defaultISR);
}
}
 
 
/**************************************************************/
 
 
void loadTask(unsigned char *code,
int csize, unsigned int physCodeAddr,
int dsize, unsigned int physDataAddr,
int bsize) {
unsigned char *virtLoadAddr;
int i;
 
virtLoadAddr = (unsigned char *) (0xC0000000 | physCodeAddr);
for (i = 0; i < csize; i++) {
*virtLoadAddr++ = *code++;
}
virtLoadAddr = (unsigned char *) (0xC0000000 | physDataAddr);
for (i = 0; i < dsize; i++) {
*virtLoadAddr++ = *code++;
}
for (i = 0; i < bsize; i++) {
*virtLoadAddr++ = '\0';
}
}
 
 
/**************************************************************/
 
 
void trapISR(int irq, unsigned int *registers) {
/* 'putchar' is the only system call yet */
putchar(registers[4]);
/* skip the trap instruction */
registers[30] += 4;
}
 
 
/**************************************************************/
 
 
void flushTLB(void) {
unsigned int invalPage;
int i;
 
invalPage = 0xC0000000;
for (i = 0; i < 32; i++) {
setTLB(i, invalPage, 0);
invalPage += (1 << 12);
}
}
 
 
/**************************************************************/
 
 
unsigned int getNumber(unsigned char *p) {
return (unsigned int) *(p + 0) << 24 |
(unsigned int) *(p + 1) << 16 |
(unsigned int) *(p + 2) << 8 |
(unsigned int) *(p + 3) << 0;
}
 
 
void main(void) {
unsigned int magic;
unsigned int csize;
unsigned int dsize;
unsigned int bsize;
 
printf("\n");
printf("OS: initializing interrupts\n");
initInterrupts();
setISR(20, trapISR);
/* load code at 256 k, data at (256 + 16) k */
printf("OS: loading task\n");
magic = getNumber(taskCode + 0);
csize = getNumber(taskCode + 4);
dsize = getNumber(taskCode + 8);
bsize = getNumber(taskCode + 12);
if (magic != 0x1AA09232) {
printf("Error: Load module is not executable!\n");
while (1) ;
}
printf("(csize = 0x%x, dsize = 0x%x, bsize = 0x%x)\n",
csize, dsize, bsize);
loadTask(taskCode + 8 * sizeof(unsigned int),
csize, 64 << 12,
dsize, 68 << 12,
bsize);
printf("OS: presetting TLB\n");
flushTLB();
setTLB(5, 0x00000000, 64 << 12 | 0x01);
setTLB(27, (csize + 0x00000FFF) & 0xFFFFF000, 68 << 12 | 0x03);
setTLB(22, 0x7FFFF000, 80 << 12 | 0x03);
printf("OS: starting task\n");
startTask(80 << 12); /* stack at (256 + 64) k */
}
/end.s
0,0 → 1,19
;
; end.s -- end-of-segment labels
;
 
.export _ecode
.export _edata
.export _ebss
 
.code
.align 4
_ecode:
 
.data
.align 4
_edata:
 
.bss
.align 4
_ebss:
/stdarg.h
0,0 → 1,41
/*
* stdarg.h -- variable argument lists
*/
 
 
#ifndef _STDARG_H_
#define _STDARG_H_
 
 
typedef char *va_list;
 
 
static float __va_arg_tmp;
 
 
#define va_start(list, start) \
((void)((list) = (sizeof(start)<4 ? \
(char *)((int *)&(start)+1) : (char *)(&(start)+1))))
 
#define __va_arg(list, mode, n) \
(__typecode(mode)==1 && sizeof(mode)==4 ? \
(__va_arg_tmp = *(double *)(&(list += \
((sizeof(double)+n)&~n))[-(int)((sizeof(double)+n)&~n)]), \
*(mode *)&__va_arg_tmp) : \
*(mode *)(&(list += \
((sizeof(mode)+n)&~n))[-(int)((sizeof(mode)+n)&~n)]))
 
#define _bigendian_va_arg(list, mode, n) \
(sizeof(mode)==1 ? *(mode *)(&(list += 4)[-1]) : \
sizeof(mode)==2 ? *(mode *)(&(list += 4)[-2]) : \
__va_arg(list, mode, n))
 
#define va_end(list) ((void)0)
 
#define va_arg(list, mode) \
(sizeof(mode)==8 ? \
*(mode *)(&(list = (char*)(((int)list + 15)&~7U))[-8]) : \
_bigendian_va_arg(list, mode, 3U))
 
 
#endif /* _STDARG_H_ */
/Makefile
0,0 → 1,20
BUILD = ../../../build
 
SRC = start.s main.c end.s
BIN = onetask.bin
MAP = onetask.map
 
all: $(BIN)
 
run: $(BIN)
$(BUILD)/bin/sim -i -t 1 -l $(BIN)
 
$(BIN): $(SRC) task.dump
$(BUILD)/bin/lcc -A -Wo-kernel \
-Wl-m -Wl$(MAP) -o $(BIN) $(SRC)
 
task.dump:
../dump/dump ../task/task task.dump
 
clean:
rm -f *~ task.dump $(BIN) $(MAP)
/start.s
0,0 → 1,267
;
; start.s -- startup code
;
 
.import main
.import _ecode
.import _edata
.import _ebss
 
.export _bcode
.export _bdata
.export _bbss
 
.export enable
.export disable
.export getISR
.export setISR
.export startTask
.export setTLB
 
.code
_bcode:
 
.data
_bdata:
 
.bss
_bbss:
 
.code
 
; reset arrives here
reset:
j start
 
; interrupts arrive here
intrpt:
j isr
 
; user TLB misses arrive here
userMiss:
j userMiss
 
isr:
add $26,$29,$0 ; sp -> $26
add $27,$1,$0 ; $1 -> $27
add $29,$0,istack ; setup interrupt stack
sub $29,$29,128 ; save registers
stw $2,$29,8
stw $3,$29,12
stw $4,$29,16
stw $5,$29,20
stw $6,$29,24
stw $7,$29,28
stw $8,$29,32
stw $9,$29,36
stw $10,$29,40
stw $11,$29,44
stw $12,$29,48
stw $13,$29,52
stw $14,$29,56
stw $15,$29,60
stw $16,$29,64
stw $17,$29,68
stw $18,$29,72
stw $19,$29,76
stw $20,$29,80
stw $21,$29,84
stw $22,$29,88
stw $23,$29,92
stw $24,$29,96
stw $25,$29,100
stw $26,$29,116 ; this is the task's sp
stw $27,$29,4 ; this is the task's $1
stw $30,$29,120 ; this is the task's resumption address
stw $31,$29,124
add $5,$29,$0 ; $5 = pointer to register array
mvfs $4,0 ; $4 = IRQ number
slr $4,$4,16
and $4,$4,0x1F
sll $26,$4,2 ; $26 = 4 * IRQ number
ldw $26,$26,irqsrv ; get addr of service routine
jalr $26 ; call service routine
j resume ; resume interrupted task if ISR returns
 
; resume a task
resume:
ldw $2,$29,8 ; restore registers
ldw $3,$29,12
ldw $4,$29,16
ldw $5,$29,20
ldw $6,$29,24
ldw $7,$29,28
ldw $8,$29,32
ldw $9,$29,36
ldw $10,$29,40
ldw $11,$29,44
ldw $12,$29,48
ldw $13,$29,52
ldw $14,$29,56
ldw $15,$29,60
ldw $16,$29,64
ldw $17,$29,68
ldw $18,$29,72
ldw $19,$29,76
ldw $20,$29,80
ldw $21,$29,84
ldw $22,$29,88
ldw $23,$29,92
ldw $24,$29,96
ldw $25,$29,100
ldw $26,$29,116 ; this is the task's sp
ldw $27,$29,4 ; this is the task's $1
ldw $30,$29,120 ; this is the task's resumption address
ldw $31,$29,124
add $1,$27,$0 ; $27 -> $1
add $29,$26,$0 ; $26 -> sp
rfx ; return from exception
 
start:
mvfs $8,0
or $8,$8,1 << 27 ; let vector point to RAM
mvts $8,0
add $29,$0,stack ; set sp
add $10,$0,_bdata ; copy data segment
add $8,$0,_edata
sub $9,$8,$10
add $9,$9,_ecode
j cpytest
cpyloop:
ldw $11,$9,0
stw $11,$8,0
cpytest:
sub $8,$8,4
sub $9,$9,4
bgeu $8,$10,cpyloop
add $8,$0,_bbss ; clear bss
add $9,$0,_ebss
j clrtest
clrloop:
stw $0,$8,0
add $8,$8,4
clrtest:
bltu $8,$9,clrloop
jal main ; call 'main'
start1:
j start1 ; loop
 
enable:
mvfs $8,0
or $8,$8,1 << 23
mvts $8,0
jr $31
 
disable:
mvfs $8,0
and $8,$8,~(1 << 23)
mvts $8,0
jr $31
 
getISR:
sll $4,$4,2
ldw $2,$4,irqsrv
jr $31
 
setISR:
sll $4,$4,2
stw $5,$4,irqsrv
jr $31
 
startTask:
or $29,$4,0xC0000000
sub $29,$29,128
stw $0,$29,0 ; preset registers
stw $0,$29,4
stw $0,$29,8
stw $0,$29,12
stw $0,$29,16
stw $0,$29,20
stw $0,$29,24
stw $0,$29,28
stw $0,$29,32
stw $0,$29,36
stw $0,$29,40
stw $0,$29,44
stw $0,$29,48
stw $0,$29,52
stw $0,$29,56
stw $0,$29,60
stw $0,$29,64
stw $0,$29,68
stw $0,$29,72
stw $0,$29,76
stw $0,$29,80
stw $0,$29,84
stw $0,$29,88
stw $0,$29,92
stw $0,$29,96
stw $0,$29,100
stw $0,$29,104
stw $0,$29,108
stw $0,$29,112
add $8,$0,0x80000000
stw $8,$29,116 ; sp
stw $0,$29,120 ; task starts at virtual address 0
stw $0,$29,124
mvfs $8,0
or $8,$8,1 << 25 ; set previous mode to 'user'
mvts $8,0
j resume
 
setTLB:
mvts $4,1 ; set index
mvts $5,2 ; set entryHi
mvts $6,3 ; set entryLo
tbwi ; write TLB entry at index
jr $31
 
.data
 
; interrupt service routine table
 
.align 4
 
irqsrv:
.word 0 ; 00: terminal 0 transmitter interrupt
.word 0 ; 01: terminal 0 receiver interrupt
.word 0 ; 02: terminal 1 transmitter interrupt
.word 0 ; 03: terminal 1 receiver interrupt
.word 0 ; 04: keyboard interrupt
.word 0 ; 05: unused
.word 0 ; 06: unused
.word 0 ; 07: unused
.word 0 ; 08: disk interrupt
.word 0 ; 09: unused
.word 0 ; 10: unused
.word 0 ; 11: unused
.word 0 ; 12: unused
.word 0 ; 13: unused
.word 0 ; 14: timer interrupt
.word 0 ; 15: unused
.word 0 ; 16: bus timeout exception
.word 0 ; 17: illegal instruction exception
.word 0 ; 18: privileged instruction exception
.word 0 ; 19: divide instruction exception
.word 0 ; 20: trap instruction exception
.word 0 ; 21: TLB miss exception
.word 0 ; 22: TLB write exception
.word 0 ; 23: TLB invalid exception
.word 0 ; 24: illegal address exception
.word 0 ; 25: privileged address exception
.word 0 ; 26: unused
.word 0 ; 27: unused
.word 0 ; 28: unused
.word 0 ; 29: unused
.word 0 ; 30: unused
.word 0 ; 31: unused
 
.bss
 
.align 4
.space 0x800
stack:
 
.align 4
.space 0x800
istack:

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