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URL https://opencores.org/ocsvn/eco32/eco32/trunk

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  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/fpga/mc/boards/xsa-xst-3/doc
    from Rev 236 to Rev 288
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Rev 236 → Rev 288

/README
0,0 → 1,22
 
Notes
-----
 
1. The configuration bitstring for the FPGA is stored in the
topmost quadrant of the Flash ROM (which is quadrant 3, with
starting address 0x180000). The DIP switch setting required
to access this quadrant during autoload on power-up is thus
SW1-1 = OFF, SW1-2 = OFF.
 
2. The machine monitor is also stored in the Flash ROM, starting
at address 0x000000. The ECO32 CPU can access the machine
monitor at virtual address 0xE0000000. The monitor's size
must not exceed 24 * 64 KB (3 quadrants of the Flash ROM).
 
3. Here is the command which burns the monitor as well as the
configuration bitstring into the Flash ROM:
~/fpgalab-0.3/build/bin/xsload \
-usb \
-fwrite ../../monitor/xsa-xst-3/monitor.exo ./eco32.exo \
-autoload
 
/dac/dac_test.cfg
0,0 → 1,19
[timestart] 20170
[size] 1023 693
[pos] -1 -1
*-9.000000 20583 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
@28
dac_test.clk
dac_test.reset
@22
dac_test.sample_l[15:0]
dac_test.sample_r[15:0]
dac_test.dac_1.timing[9:0]
dac_test.dac_1.sr[63:0]
@28
dac_test.dac_1.shift
dac_test.next
dac_test.mclk
dac_test.sclk
dac_test.lrck
dac_test.sdti
/dac/dac_test.v
0,0 → 1,51
//
// dac_test.v -- test bench for DAC control circuit
//
 
`include "dac.v"
 
`timescale 1ns/1ns
 
module dac_test;
 
reg clk; // system clock (50 MHz)
reg reset_in; // reset, input
reg reset_s1; // reset, first synchronizer
reg reset; // reset, second synchronizer
reg [15:0] sample_l;
reg [15:0] sample_r;
wire next;
wire mclk;
wire sclk;
wire lrck;
wire sdti;
 
// instantiate the controller
dac dac_1(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
 
// simulation control
initial begin
#0 $dumpfile("dump.vcd");
$dumpvars(0, dac_test);
sample_l = 16'h0FF0;
sample_r = 16'hAA55;
clk = 1;
reset_in = 1;
#145 reset_in = 0;
#90000 $finish;
end
 
// clock generator
always begin
#10 clk = ~clk; // 20 nsec cycle time
end
 
// reset synchronizer
always @(posedge clk) begin
reset_s1 <= reset_in;
reset <= reset_s1;
end
 
endmodule
/dac/dac.v
0,0 → 1,59
//
// dac.v -- DAC control circuit
//
 
`timescale 1ns/1ns
 
module dac(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
input clk;
input reset;
input [15:0] sample_l;
input [15:0] sample_r;
output next;
output mclk;
output sclk;
output lrck;
output sdti;
 
reg [9:0] timing;
reg [63:0] sr;
wire shift;
 
always @(posedge clk) begin
if (reset) begin
timing <= 10'h0;
end else begin
timing <= timing + 1;
end
end
 
assign mclk = timing[1];
assign sclk = timing[3];
assign lrck = timing[9];
 
assign next = (timing[9:0] == 10'h1FF) ? 1 : 0;
assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
 
always @(posedge clk) begin
if (reset) begin
sr <= 64'h0;
end else begin
if (next) begin
sr[63:52] <= 12'h000;
sr[51:32] <= { sample_l[15:0], 4'h0 };
sr[31:20] <= 12'h000;
sr[19: 0] <= { sample_r[15:0], 4'h0 };
end else begin
if (shift) begin
sr[63:1] <= sr[62:0];
sr[0] <= 1'b0;
end
end
end
end
 
assign sdti = sr[63];
 
endmodule
/dac/Makefile
0,0 → 1,20
#
# Makefile for DAC control circuit test
#
 
all: dac_test
 
dac_test: dac.v dac_test.v
iverilog -Wall -o dac_test dac_test.v
 
run: dac_test
./dac_test
 
dump.vcd: dac_test
./dac_test
 
show: dump.vcd
gtkwave dump.vcd dac_test.cfg
 
clean:
rm -f *~ dac_test dump.vcd
/dac/README
0,0 → 1,15
 
Timing Parameters
-----------------
 
clk = 50 MHz (20 nsec)
mclk = clk / 4 = 12.5 MHz (80 nsec)
sclk = mclk / 4 = 3.125 MHz (320 nsec)
lrck = sclk / 64 = 48.828 kHz (20.48 usec)
 
==>
 
fs = 48.828 kHz
mclk = 256 * fs = 12.5 MHz
sclk = 64 * fs = 3.125 MHz
 

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