OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/fpga/mc/boards/xsa-xst-3
    from Rev 289 to Rev 290
    ↔ Reverse comparison
  •

Rev 289 → Rev 290

/build/eco32.xise
9,15 → 9,15
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="../src/toplevel/eco32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../src/toplevel/eco32.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
24,111 → 24,115
</file>
<file xil_pn:name="../src/clk_rst/clk_rst.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/cpu/cpu_bus.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/ram/sdr/ram.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/cpu/cpu_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../src/ram/sdr/ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../src/ram/sdr/sdramcntl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../src/rom/S29AL016M/rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../src/tmr/tmr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp9/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp9/display.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../src/dsp/common/timing.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/dsp/bpp9/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../src/dsp/common/dspmem.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/dsp/bpp9/pixel.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../src/dsp/common/chrgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp9/pixel.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<file xil_pn:name="../../../src/dsp/common/dspmem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../src/dsp/common/timing.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../src/kbd/kbd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../src/ser/ser.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<file xil_pn:name="../../../src/ser/rcv.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../src/ser/rcv.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../src/ser/xmtbuf.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/ser/ser.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../src/ser/xmt.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../src/dsk/dsk.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/ser/xmtbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/dsk/atabuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../src/dsk/atabuf.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../../src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../src/dsk/ataio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../src/dsk/dsk.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../../src/fms/fms.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../src/dac/dac.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../src/bio/bio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
</files>
 
429,8 → 433,8
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-22T10:39:41" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0E400F2973EFF942A896ED4FF3200B80" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-05-15T10:26:12" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8946D63AC439550A5CA559067A64D086" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
/build/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/doc/dac/dac_test.v
2,10 → 2,14
// dac_test.v -- test bench for DAC control circuit
//
 
 
`include "dac.v"
 
 
`timescale 1ns/1ns
`default_nettype none
 
 
module dac_test;
 
reg clk; // system clock (50 MHz)
/doc/dac/dac.v
2,8 → 2,11
// dac.v -- DAC control circuit
//
 
 
`timescale 1ns/1ns
`default_nettype none
 
 
module dac(clk, reset,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
/src/busctrl/busctrl.v File deleted
/src/clk_rst/clk_rst.v
3,16 → 3,20
//
 
 
module clk_rst(clk_in, reset_inout_n,
`timescale 1ns/10ps
`default_nettype none
 
 
module clk_rst(clk_in, rst_inout_n,
sdram_clk, sdram_fb,
clk, clk_ok, reset);
clk, clk_ok, rst);
input clk_in;
inout reset_inout_n;
inout rst_inout_n;
output sdram_clk;
input sdram_fb;
output clk;
output clk_ok;
output reset;
output rst;
 
wire clk_in_buf;
wire int_clk;
21,10 → 25,10
wire ext_fb;
wire ext_locked;
 
reg reset_p_n;
reg reset_s_n;
reg [23:0] reset_counter;
wire reset_counting;
reg rst_p_n;
reg rst_s_n;
reg [23:0] rst_counter;
wire rst_counting;
 
//------------------------------------------------------------
 
79,21 → 83,21
 
//------------------------------------------------------------
 
assign reset_counting = (reset_counter == 24'hFFFFFF) ? 0 : 1;
assign reset_inout_n = (reset_counter[23] == 0) ? 1'b0 : 1'bz;
assign rst_counting = (rst_counter == 24'hFFFFFF) ? 0 : 1;
assign rst_inout_n = (rst_counter[23] == 0) ? 1'b0 : 1'bz;
 
always @(posedge clk_in_buf) begin
reset_p_n <= reset_inout_n;
reset_s_n <= reset_p_n;
if (reset_counting == 1) begin
reset_counter <= reset_counter + 1;
rst_p_n <= rst_inout_n;
rst_s_n <= rst_p_n;
if (rst_counting) begin
rst_counter <= rst_counter + 1;
end else begin
if (~reset_s_n | ~clk_ok) begin
reset_counter <= 24'h000000;
if (~rst_s_n | ~clk_ok) begin
rst_counter <= 24'h000000;
end
end
end
 
assign reset = reset_counting;
assign rst = rst_counting;
 
endmodule
/src/dac/dac.v
3,11 → 3,15
//
 
 
module dac(clk, reset,
`timescale 1ns/10ps
`default_nettype none
 
 
module dac(clk, rst,
sample_l, sample_r, next,
mclk, sclk, lrck, sdti);
input clk;
input reset;
input rst;
input [15:0] sample_l;
input [15:0] sample_r;
output next;
21,7 → 25,7
wire shift;
 
always @(posedge clk) begin
if (reset) begin
if (rst) begin
timing <= 10'h0;
end else begin
timing <= timing + 1;
36,7 → 40,7
assign shift = (timing[3:0] == 4'hF) ? 1 : 0;
 
always @(posedge clk) begin
if (reset) begin
if (rst) begin
sr <= 64'h0;
end else begin
if (next) begin
/src/bio/bio.v
3,22 → 3,26
//
 
 
module bio(clk, reset,
en, wr, addr,
`timescale 1ns/10ps
`default_nettype none
 
 
module bio(clk, rst,
stb, we, addr,
data_in, data_out,
wt,
ack,
sw1_1, sw1_2,
sw1_3, sw1_4,
sw2_n, sw3_n);
// internal interface
input clk;
input reset;
input en;
input wr;
input rst;
input stb;
input we;
input addr;
input [31:0] data_in;
output [31:0] data_out;
output wt;
output ack;
// external interface
input sw1_1;
input sw1_2;
44,10 → 48,10
reg sw3_s_n;
 
always @(posedge clk) begin
if (reset) begin
if (rst) begin
bio_out[31:0] <= 32'h0;
end else begin
if (en & wr & ~addr) begin
if (stb & we & ~addr) begin
bio_out[31:0] <= data_in[31:0];
end
end
55,7 → 59,7
 
assign data_out[31:0] =
(addr == 0) ? bio_out[31:0] : bio_in[31:0];
assign wt = 0;
assign ack = stb;
 
always @(posedge clk) begin
sw1_1_p <= sw1_1;
/src/toplevel/eco32.v
3,8 → 3,12
//
 
 
`timescale 1ns/10ps
`default_nettype none
 
 
module eco32(clk_in,
reset_inout_n,
rst_inout_n,
sdram_clk,
sdram_fb,
sdram_cke,
59,7 → 63,7
 
// clock and reset
input clk_in;
inout reset_inout_n;
inout rst_inout_n;
// SDRAM
output sdram_clk;
input sdram_fb;
126,249 → 130,112
input sw3_n;
 
// clk_rst
wire clk;
wire clk_ok;
wire reset;
wire clk; // system clock
wire clk_ok; // clock is stable
wire rst; // system reset
// cpu
wire cpu_en;
wire cpu_wr;
wire [1:0] cpu_size;
wire [31:0] cpu_addr;
wire [31:0] cpu_data_in;
wire [31:0] cpu_data_out;
wire cpu_wt;
wire [15:0] cpu_irq;
wire bus_stb; // bus strobe
wire bus_we; // bus write enable
wire [31:2] bus_addr; // bus address (word address)
wire [31:0] bus_din; // bus data input, for reads
wire [31:0] bus_dout; // bus data output, for writes
wire bus_ack; // bus acknowledge
wire [15:0] bus_irq; // bus interrupt requests
// ram
wire ram_en;
wire ram_wr;
wire [1:0] ram_size;
wire [24:0] ram_addr;
wire [31:0] ram_data_in;
wire [31:0] ram_data_out;
wire ram_wt;
wire ram_stb; // ram strobe
wire [31:0] ram_dout; // ram data output
wire ram_ack; // ram acknowledge
// rom
wire rom_en;
wire rom_wr;
wire [1:0] rom_size;
wire [20:0] rom_addr;
wire [31:0] rom_data_out;
wire rom_wt;
wire rom_stb; // rom strobe
wire [31:0] rom_dout; // rom data output
wire rom_ack; // rom acknowledge
// i/o
wire i_o_stb; // i/o strobe
// tmr0
wire tmr0_en;
wire tmr0_wr;
wire [3:2] tmr0_addr;
wire [31:0] tmr0_data_in;
wire [31:0] tmr0_data_out;
wire tmr0_wt;
wire tmr0_irq;
wire tmr0_stb; // tmr 0 strobe
wire [31:0] tmr0_dout; // tmr 0 data output
wire tmr0_ack; // tmr 0 acknowledge
wire tmr0_irq; // tmr 0 interrupt request
// tmr1
wire tmr1_en;
wire tmr1_wr;
wire [3:2] tmr1_addr;
wire [31:0] tmr1_data_in;
wire [31:0] tmr1_data_out;
wire tmr1_wt;
wire tmr1_irq;
wire tmr1_stb; // tmr 1 strobe
wire [31:0] tmr1_dout; // tmr 1 data output
wire tmr1_ack; // tmr 1 acknowledge
wire tmr1_irq; // tmr 1 interrupt request
// dsp
wire dsp_en;
wire dsp_wr;
wire [13:2] dsp_addr;
wire [15:0] dsp_data_in;
wire [15:0] dsp_data_out;
wire dsp_wt;
wire dsp_stb; // dsp strobe
wire [15:0] dsp_dout; // dsp data output
wire dsp_ack; // dsp acknowledge
// kbd
wire kbd_en;
wire kbd_wr;
wire kbd_addr;
wire [7:0] kbd_data_in;
wire [7:0] kbd_data_out;
wire kbd_wt;
wire kbd_irq;
wire kbd_stb; // kbd strobe
wire [7:0] kbd_dout; // kbd data output
wire kbd_ack; // kbd acknowledge
wire kbd_irq; // kbd interrupt request
// ser0
wire ser0_en;
wire ser0_wr;
wire [3:2] ser0_addr;
wire [7:0] ser0_data_in;
wire [7:0] ser0_data_out;
wire ser0_wt;
wire ser0_irq_r;
wire ser0_irq_t;
wire ser0_stb; // ser 0 strobe
wire [7:0] ser0_dout; // ser 0 data output
wire ser0_ack; // ser 0 acknowledge
wire ser0_irq_r; // ser 0 rcv interrupt request
wire ser0_irq_t; // ser 0 xmt interrupt request
// ser1
wire ser1_en;
wire ser1_wr;
wire [3:2] ser1_addr;
wire [7:0] ser1_data_in;
wire [7:0] ser1_data_out;
wire ser1_wt;
wire ser1_irq_r;
wire ser1_irq_t;
wire ser1_stb; // ser 1 strobe
wire [7:0] ser1_dout; // ser 1 data output
wire ser1_ack; // ser 1 acknowledge
wire ser1_irq_r; // ser 1 rcv interrupt request
wire ser1_irq_t; // ser 1 xmt interrupt request
// dsk
wire dsk_en;
wire dsk_wr;
wire [19:2] dsk_addr;
wire [31:0] dsk_data_in;
wire [31:0] dsk_data_out;
wire dsk_wt;
wire dsk_irq;
wire dsk_stb; // dsk strobe
wire [31:0] dsk_dout; // dsk data output
wire dsk_ack; // dsk acknowledge
wire dsk_irq; // dsk interrupt request
// fms
wire fms_en;
wire fms_wr;
wire [11:2] fms_addr;
wire [31:0] fms_data_in;
wire [31:0] fms_data_out;
wire fms_wt;
wire fms_stb; // fms strobe
wire [31:0] fms_dout; // fms data output
wire fms_ack; // fms acknowledge
// dac
wire [15:0] dac_sample_l;
wire [15:0] dac_sample_r;
wire dac_next;
wire [15:0] dac_sample_l; // dac sample value, left
wire [15:0] dac_sample_r; // dac sample value, right
wire dac_next; // dac next sample request
// bio
wire bio_en;
wire bio_wr;
wire bio_addr;
wire [31:0] bio_data_in;
wire [31:0] bio_data_out;
wire bio_wt;
wire bio_stb; // bio strobe
wire [31:0] bio_dout; // bio data output
wire bio_ack; // bio acknowledge
 
clk_rst clk_rst1(
//--------------------------------------
// module instances
//--------------------------------------
 
clk_rst clk_rst_1(
.clk_in(clk_in),
.reset_inout_n(reset_inout_n),
.rst_inout_n(rst_inout_n),
.sdram_clk(sdram_clk),
.sdram_fb(sdram_fb),
.clk(clk),
.clk_ok(clk_ok),
.reset(reset)
.rst(rst)
);
 
busctrl busctrl1(
// cpu
.cpu_en(cpu_en),
.cpu_wr(cpu_wr),
.cpu_size(cpu_size[1:0]),
.cpu_addr(cpu_addr[31:0]),
.cpu_data_in(cpu_data_in[31:0]),
.cpu_data_out(cpu_data_out[31:0]),
.cpu_wt(cpu_wt),
// ram
.ram_en(ram_en),
.ram_wr(ram_wr),
.ram_size(ram_size[1:0]),
.ram_addr(ram_addr[24:0]),
.ram_data_in(ram_data_in[31:0]),
.ram_data_out(ram_data_out[31:0]),
.ram_wt(ram_wt),
// rom
.rom_en(rom_en),
.rom_wr(rom_wr),
.rom_size(rom_size[1:0]),
.rom_addr(rom_addr[20:0]),
.rom_data_out(rom_data_out[31:0]),
.rom_wt(rom_wt),
// tmr0
.tmr0_en(tmr0_en),
.tmr0_wr(tmr0_wr),
.tmr0_addr(tmr0_addr[3:2]),
.tmr0_data_in(tmr0_data_in[31:0]),
.tmr0_data_out(tmr0_data_out[31:0]),
.tmr0_wt(tmr0_wt),
// tmr1
.tmr1_en(tmr1_en),
.tmr1_wr(tmr1_wr),
.tmr1_addr(tmr1_addr[3:2]),
.tmr1_data_in(tmr1_data_in[31:0]),
.tmr1_data_out(tmr1_data_out[31:0]),
.tmr1_wt(tmr1_wt),
// dsp
.dsp_en(dsp_en),
.dsp_wr(dsp_wr),
.dsp_addr(dsp_addr[13:2]),
.dsp_data_in(dsp_data_in[15:0]),
.dsp_data_out(dsp_data_out[15:0]),
.dsp_wt(dsp_wt),
// kbd
.kbd_en(kbd_en),
.kbd_wr(kbd_wr),
.kbd_addr(kbd_addr),
.kbd_data_in(kbd_data_in[7:0]),
.kbd_data_out(kbd_data_out[7:0]),
.kbd_wt(kbd_wt),
// ser0
.ser0_en(ser0_en),
.ser0_wr(ser0_wr),
.ser0_addr(ser0_addr[3:2]),
.ser0_data_in(ser0_data_in[7:0]),
.ser0_data_out(ser0_data_out[7:0]),
.ser0_wt(ser0_wt),
// ser1
.ser1_en(ser1_en),
.ser1_wr(ser1_wr),
.ser1_addr(ser1_addr[3:2]),
.ser1_data_in(ser1_data_in[7:0]),
.ser1_data_out(ser1_data_out[7:0]),
.ser1_wt(ser1_wt),
// dsk
.dsk_en(dsk_en),
.dsk_wr(dsk_wr),
.dsk_addr(dsk_addr[19:2]),
.dsk_data_in(dsk_data_in[31:0]),
.dsk_data_out(dsk_data_out[31:0]),
.dsk_wt(dsk_wt),
// fms
.fms_en(fms_en),
.fms_wr(fms_wr),
.fms_addr(fms_addr[11:2]),
.fms_data_in(fms_data_in[31:0]),
.fms_data_out(fms_data_out[31:0]),
.fms_wt(fms_wt),
// bio
.bio_en(bio_en),
.bio_wr(bio_wr),
.bio_addr(bio_addr),
.bio_data_in(bio_data_in[31:0]),
.bio_data_out(bio_data_out[31:0]),
.bio_wt(bio_wt)
);
 
cpu cpu1(
cpu cpu_1(
.clk(clk),
.reset(reset),
.bus_en(cpu_en),
.bus_wr(cpu_wr),
.bus_size(cpu_size[1:0]),
.bus_addr(cpu_addr[31:0]),
.bus_data_in(cpu_data_in[31:0]),
.bus_data_out(cpu_data_out[31:0]),
.bus_wt(cpu_wt),
.irq(cpu_irq[15:0])
.rst(rst),
.bus_stb(bus_stb),
.bus_we(bus_we),
.bus_addr(bus_addr[31:2]),
.bus_din(bus_din[31:0]),
.bus_dout(bus_dout[31:0]),
.bus_ack(bus_ack),
.bus_irq(bus_irq[15:0])
);
 
assign cpu_irq[15] = tmr1_irq;
assign cpu_irq[14] = tmr0_irq;
assign cpu_irq[13] = 1'b0;
assign cpu_irq[12] = 1'b0;
assign cpu_irq[11] = 1'b0;
assign cpu_irq[10] = 1'b0;
assign cpu_irq[ 9] = 1'b0;
assign cpu_irq[ 8] = dsk_irq;
assign cpu_irq[ 7] = 1'b0;
assign cpu_irq[ 6] = 1'b0;
assign cpu_irq[ 5] = 1'b0;
assign cpu_irq[ 4] = kbd_irq;
assign cpu_irq[ 3] = ser1_irq_r;
assign cpu_irq[ 2] = ser1_irq_t;
assign cpu_irq[ 1] = ser0_irq_r;
assign cpu_irq[ 0] = ser0_irq_t;
 
ram ram1(
ram ram_1(
.clk(clk),
.clk_ok(clk_ok),
.reset(reset),
.en(ram_en),
.wr(ram_wr),
.size(ram_size[1:0]),
.addr(ram_addr[24:0]),
.data_in(ram_data_in[31:0]),
.data_out(ram_data_out[31:0]),
.wt(ram_wt),
.rst(rst),
.stb(ram_stb),
.we(bus_we),
.addr(bus_addr[24:2]),
.data_in(bus_dout[31:0]),
.data_out(ram_dout[31:0]),
.ack(ram_ack),
.sdram_cke(sdram_cke),
.sdram_cs_n(sdram_cs_n),
.sdram_ras_n(sdram_ras_n),
381,15 → 248,14
.sdram_dq(sdram_dq[15:0])
);
 
rom rom1(
rom rom_1(
.clk(clk),
.reset(reset),
.en(rom_en),
.wr(rom_wr),
.size(rom_size[1:0]),
.addr(rom_addr[20:0]),
.data_out(rom_data_out[31:0]),
.wt(rom_wt),
.rst(rst),
.stb(rom_stb),
.we(bus_we),
.addr(bus_addr[20:2]),
.data_out(rom_dout[31:0]),
.ack(rom_ack),
.ce_n(flash_ce_n),
.oe_n(flash_oe_n),
.we_n(flash_we_n),
399,39 → 265,39
.d(flash_d[15:0])
);
 
tmr tmr1_0(
tmr tmr_1(
.clk(clk),
.reset(reset),
.en(tmr0_en),
.wr(tmr0_wr),
.addr(tmr0_addr[3:2]),
.data_in(tmr0_data_in[31:0]),
.data_out(tmr0_data_out[31:0]),
.wt(tmr0_wt),
.rst(rst),
.stb(tmr0_stb),
.we(bus_we),
.addr(bus_addr[3:2]),
.data_in(bus_dout[31:0]),
.data_out(tmr0_dout[31:0]),
.ack(tmr0_ack),
.irq(tmr0_irq)
);
 
tmr tmr1_1(
tmr tmr_2(
.clk(clk),
.reset(reset),
.en(tmr1_en),
.wr(tmr1_wr),
.addr(tmr1_addr[3:2]),
.data_in(tmr1_data_in[31:0]),
.data_out(tmr1_data_out[31:0]),
.wt(tmr1_wt),
.rst(rst),
.stb(tmr1_stb),
.we(bus_we),
.addr(bus_addr[3:2]),
.data_in(bus_dout[31:0]),
.data_out(tmr1_dout[31:0]),
.ack(tmr1_ack),
.irq(tmr1_irq)
);
 
dsp dsp1(
dsp dsp_1(
.clk(clk),
.reset(reset),
.en(dsp_en),
.wr(dsp_wr),
.addr(dsp_addr[13:2]),
.data_in(dsp_data_in[15:0]),
.data_out(dsp_data_out[15:0]),
.wt(dsp_wt),
.rst(rst),
.stb(dsp_stb),
.we(bus_we),
.addr(bus_addr[13:2]),
.data_in(bus_dout[15:0]),
.data_out(dsp_dout[15:0]),
.ack(dsp_ack),
.hsync(vga_hsync),
.vsync(vga_vsync),
.r(vga_r[2:0]),
439,29 → 305,29
.b(vga_b[2:0])
);
 
kbd kbd1(
kbd kbd_1(
.clk(clk),
.reset(reset),
.en(kbd_en),
.wr(kbd_wr),
.addr(kbd_addr),
.data_in(kbd_data_in[7:0]),
.data_out(kbd_data_out[7:0]),
.wt(kbd_wt),
.rst(rst),
.stb(kbd_stb),
.we(bus_we),
.addr(bus_addr[2]),
.data_in(bus_dout[7:0]),
.data_out(kbd_dout[7:0]),
.ack(kbd_ack),
.irq(kbd_irq),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data)
);
 
ser ser1_0(
ser ser_1(
.clk(clk),
.reset(reset),
.en(ser0_en),
.wr(ser0_wr),
.addr(ser0_addr[3:2]),
.data_in(ser0_data_in[7:0]),
.data_out(ser0_data_out[7:0]),
.wt(ser0_wt),
.rst(rst),
.stb(ser0_stb),
.we(bus_we),
.addr(bus_addr[3:2]),
.data_in(bus_dout[7:0]),
.data_out(ser0_dout[7:0]),
.ack(ser0_ack),
.irq_r(ser0_irq_r),
.irq_t(ser0_irq_t),
.rxd(rs232_0_rxd),
468,15 → 334,15
.txd(rs232_0_txd)
);
 
ser ser1_1(
ser ser_2(
.clk(clk),
.reset(reset),
.en(ser1_en),
.wr(ser1_wr),
.addr(ser1_addr[3:2]),
.data_in(ser1_data_in[7:0]),
.data_out(ser1_data_out[7:0]),
.wt(ser1_wt),
.rst(rst),
.stb(ser1_stb),
.we(bus_we),
.addr(bus_addr[3:2]),
.data_in(bus_dout[7:0]),
.data_out(ser1_dout[7:0]),
.ack(ser1_ack),
.irq_r(ser1_irq_r),
.irq_t(ser1_irq_t),
.rxd(rs232_1_rxd),
483,15 → 349,17
.txd(rs232_1_txd)
);
 
dsk dsk1(
assign pbus_a[4:3] = 2'b00;
 
dsk dsk_1(
.clk(clk),
.reset(reset),
.en(dsk_en),
.wr(dsk_wr),
.addr(dsk_addr[19:2]),
.data_in(dsk_data_in[31:0]),
.data_out(dsk_data_out[31:0]),
.wt(dsk_wt),
.rst(rst),
.stb(dsk_stb),
.we(bus_we),
.addr(bus_addr[19:2]),
.data_in(bus_dout[31:0]),
.data_out(dsk_dout[31:0]),
.ack(dsk_ack),
.irq(dsk_irq),
.ata_d(pbus_d[15:0]),
.ata_a(pbus_a[2:0]),
505,23 → 373,23
.ata_iordy(ata_iordy)
);
 
fms fms1(
fms fms_1(
.clk(clk),
.reset(reset),
.en(fms_en),
.wr(fms_wr),
.addr(fms_addr[11:2]),
.data_in(fms_data_in[31:0]),
.data_out(fms_data_out[31:0]),
.wt(fms_wt),
.rst(rst),
.stb(fms_stb),
.we(bus_we),
.addr(bus_addr[11:2]),
.data_in(bus_dout[31:0]),
.data_out(fms_dout[31:0]),
.ack(fms_ack),
.next(dac_next),
.sample_l(dac_sample_l[15:0]),
.sample_r(dac_sample_r[15:0])
);
 
dac dac1(
dac dac_1(
.clk(clk),
.reset(reset),
.rst(rst),
.sample_l(dac_sample_l[15:0]),
.sample_r(dac_sample_r[15:0]),
.next(dac_next),
531,20 → 399,19
.sdti(dac_sdti)
);
 
assign pbus_a[4:3] = 2'b00;
assign slot1_cs_n = 1;
assign slot2_cs_n = 1;
assign ether_cs_n = 1;
assign slot1_cs_n = 1'b1;
assign slot2_cs_n = 1'b1;
assign ether_cs_n = 1'b1;
 
bio bio1(
bio bio_1(
.clk(clk),
.reset(reset),
.en(bio_en),
.wr(bio_wr),
.addr(bio_addr),
.data_in(bio_data_in[31:0]),
.data_out(bio_data_out[31:0]),
.wt(bio_wt),
.rst(rst),
.stb(bio_stb),
.we(bus_we),
.addr(bus_addr[2]),
.data_in(bus_dout[31:0]),
.data_out(bio_dout[31:0]),
.ack(bio_ack),
.sw1_1(flash_a[19]),
.sw1_2(flash_a[18]),
.sw1_3(sw1_3),
553,4 → 420,101
.sw3_n(sw3_n)
);
 
//--------------------------------------
// address decoder
//--------------------------------------
 
// RAM: architectural limit = 512 MB
// implementation limit = 32 MB
assign ram_stb =
(bus_stb == 1 && bus_addr[31:29] == 3'b000
&& bus_addr[28:25] == 4'b0000) ? 1 : 0;
 
// ROM: architectural limit = 256 MB
// implementation limit = 2 MB
assign rom_stb =
(bus_stb == 1 && bus_addr[31:28] == 4'b0010
&& bus_addr[27:21] == 7'b0000000) ? 1 : 0;
 
// I/O: architectural limit = 256 MB
assign i_o_stb =
(bus_stb == 1 && bus_addr[31:28] == 4'b0011) ? 1 : 0;
assign tmr0_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h00
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
assign tmr1_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h00
&& bus_addr[19:12] == 8'h01) ? 1 : 0;
assign dsp_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h01) ? 1 : 0;
assign kbd_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h02) ? 1 : 0;
assign ser0_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h03
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
assign ser1_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h03
&& bus_addr[19:12] == 8'h01) ? 1 : 0;
assign dsk_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h04) ? 1 : 0;
assign fms_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h05
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
assign bio_stb =
(i_o_stb == 1 && bus_addr[27:20] == 8'h10
&& bus_addr[19:12] == 8'h00) ? 1 : 0;
 
//--------------------------------------
// data and acknowledge multiplexers
//--------------------------------------
 
assign bus_din[31:0] =
(ram_stb == 1) ? ram_dout[31:0] :
(rom_stb == 1) ? rom_dout[31:0] :
(tmr0_stb == 1) ? tmr0_dout[31:0] :
(tmr1_stb == 1) ? tmr1_dout[31:0] :
(dsp_stb == 1) ? { 16'h0000, dsp_dout[15:0] } :
(kbd_stb == 1) ? { 24'h000000, kbd_dout[7:0] } :
(ser0_stb == 1) ? { 24'h000000, ser0_dout[7:0] } :
(ser1_stb == 1) ? { 24'h000000, ser1_dout[7:0] } :
(dsk_stb == 1) ? dsk_dout[31:0] :
(fms_stb == 1) ? fms_dout[31:0] :
(bio_stb == 1) ? bio_dout[31:0] :
32'h00000000;
 
assign bus_ack =
(ram_stb == 1) ? ram_ack :
(rom_stb == 1) ? rom_ack :
(tmr0_stb == 1) ? tmr0_ack :
(tmr1_stb == 1) ? tmr1_ack :
(dsp_stb == 1) ? dsp_ack :
(kbd_stb == 1) ? kbd_ack :
(ser0_stb == 1) ? ser0_ack :
(ser1_stb == 1) ? ser1_ack :
(dsk_stb == 1) ? dsk_ack :
(fms_stb == 1) ? fms_ack :
(bio_stb == 1) ? bio_ack :
0;
 
//--------------------------------------
// bus interrupt request assignments
//--------------------------------------
 
assign bus_irq[15] = tmr1_irq;
assign bus_irq[14] = tmr0_irq;
assign bus_irq[13] = 0;
assign bus_irq[12] = 0;
assign bus_irq[11] = 0;
assign bus_irq[10] = 0;
assign bus_irq[ 9] = 0;
assign bus_irq[ 8] = dsk_irq;
assign bus_irq[ 7] = 0;
assign bus_irq[ 6] = 0;
assign bus_irq[ 5] = 0;
assign bus_irq[ 4] = kbd_irq;
assign bus_irq[ 3] = ser1_irq_r;
assign bus_irq[ 2] = ser1_irq_t;
assign bus_irq[ 1] = ser0_irq_r;
assign bus_irq[ 0] = ser0_irq_t;
 
endmodule
/src/toplevel/eco32.ucf
7,7 → 7,7
#
NET "clk_in" PERIOD = 20.0ns HIGH 40%;
NET "clk_in" LOC = "p8";
NET "reset_inout_n" LOC = "d15";
NET "rst_inout_n" LOC = "d15";
 
#
# SDRAM

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