OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/fpga
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/xsa-xst-3-copy/eco32.xise File deleted
/xsa-xst-3-copy/eco32.ucf File deleted
/xsa-xst-3/eco32-29.xise File deleted
/xsa-xst-3/eco32.xise
0,0 → 1,160
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
 
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="src/eco32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/eco32.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="src/clk_reset/clk_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ram/ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ram/sdramcntl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/rom/rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ser/rcv.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ser/ser.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ser/xmt.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/ser/xmtbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsk/atabuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsk/ataio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsk/dsk.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/kbd/kbd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/tmr/tmr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/chrgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/display.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/dspmem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/pixel.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
<file xil_pn:name="src/dsp/timing.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation"/>
<association xil_pn:name="BehavioralSimulation"/>
</file>
</files>
 
<properties>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Float"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Float"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Float"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Float"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Float"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Float"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Text Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="JTAG Clock"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|eco32"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/eco32"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Float"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Float"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Float"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Float"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="eco32-29"/>
<property xil_pn:name="Package" xil_pn:value="ft256"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Simulator" xil_pn:value="Other Verilog"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
</properties>
 
<bindings/>
 
<libraries/>
 
<partitions>
<partition xil_pn:name="/eco32"/>
</partitions>
 
</project>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.