OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/fpga
    from Rev 33 to Rev 67
    ↔ Reverse comparison
  •

Rev 33 → Rev 67

/src/eco32.v
138,7 → 138,7
// tmr
wire tmr_en;
wire tmr_wr;
wire tmr_addr2;
wire tmr_addr;
wire [31:0] tmr_data_in;
wire [31:0] tmr_data_out;
wire tmr_wt;
153,7 → 153,7
// kbd
wire kbd_en;
wire kbd_wr;
wire kbd_addr2;
wire kbd_addr;
wire [7:0] kbd_data_in;
wire [7:0] kbd_data_out;
wire kbd_wt;
222,7 → 222,7
// tmr
.tmr_en(tmr_en),
.tmr_wr(tmr_wr),
.tmr_addr2(tmr_addr2),
.tmr_addr(tmr_addr),
.tmr_data_in(tmr_data_in[31:0]),
.tmr_data_out(tmr_data_out[31:0]),
.tmr_wt(tmr_wt),
236,7 → 236,7
// kbd
.kbd_en(kbd_en),
.kbd_wr(kbd_wr),
.kbd_addr2(kbd_addr2),
.kbd_addr(kbd_addr),
.kbd_data_in(kbd_data_in[7:0]),
.kbd_data_out(kbd_data_out[7:0]),
.kbd_wt(kbd_wt),
339,7 → 339,7
.reset(reset),
.en(tmr_en),
.wr(tmr_wr),
.addr2(tmr_addr2),
.addr(tmr_addr),
.data_in(tmr_data_in[31:0]),
.data_out(tmr_data_out[31:0]),
.wt(tmr_wt),
369,7 → 369,7
.reset(reset),
.en(kbd_en),
.wr(kbd_wr),
.addr2(kbd_addr2),
.addr(kbd_addr),
.data_in(kbd_data_in[7:0]),
.data_out(kbd_data_out[7:0]),
.wt(kbd_wt),
/src/kbd/kbd.v
1,6 → 1,6
module kbd(ps2_clk, ps2_data,
clk, reset,
en, wr, addr2,
en, wr, addr,
data_in, data_out,
wt, irq);
input ps2_clk;
9,7 → 9,7
input reset;
input en;
input wr;
input addr2;
input addr;
input [7:0] data_in;
output [7:0] data_out;
output wt;
40,10 → 40,10
data <= keyboard_data;
end
if (keyboard_rdy == 1 ||
(en == 1 && wr == 0 && addr2 == 1)) begin
(en == 1 && wr == 0 && addr == 1)) begin
rdy <= keyboard_rdy;
end
if (en == 1 && wr == 1 && addr2 == 0) begin
if (en == 1 && wr == 1 && addr == 0) begin
rdy <= data_in[0];
ien <= data_in[1];
end
51,7 → 51,7
end
 
assign data_out =
(addr2 == 0) ? { 6'b000000, ien, rdy } : data;
(addr == 0) ? { 6'b000000, ien, rdy } : data;
assign wt = 1'b0;
assign irq = ien & rdy;
 
/src/tmr/tmr.v
1,5 → 1,5
module tmr(clk, reset,
en, wr, addr2,
en, wr, addr,
data_in, data_out,
wt, irq);
input clk;
6,7 → 6,7
input reset;
input en;
input wr;
input addr2;
input addr;
input [31:0] data_in;
output [31:0] data_out;
output wt;
65,11 → 65,11
if (expired == 1) begin
alarm <= 1;
end else begin
if (en == 1 && wr == 1 && addr2 == 0) begin
if (en == 1 && wr == 1 && addr == 0) begin
alarm <= data_in[0];
ien <= data_in[1];
end
if (en == 1 && wr == 1 && addr2 == 1) begin
if (en == 1 && wr == 1 && addr == 1) begin
divisor <= data_in;
divisor_loaded <= 1;
end else begin
80,7 → 80,7
end
 
assign data_out =
(addr2 == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
(addr == 0) ? { 28'h0000000, 2'b00, ien, alarm } :
divisor;
assign wt = 0;
assign irq = ien & alarm;
/src/busctrl/busctrl.v
1,12 → 1,25
module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr, cpu_data_out, cpu_data_in, cpu_wt,
ram_en, ram_wr, ram_size, ram_addr, ram_data_in, ram_data_out, ram_wt,
rom_en, rom_wr, rom_size, rom_addr, rom_data_out, rom_wt,
tmr_en, tmr_wr, tmr_addr2, tmr_data_in, tmr_data_out, tmr_wt,
dsp_en, dsp_wr, dsp_addr, dsp_data_in, dsp_data_out, dsp_wt,
kbd_en, kbd_wr, kbd_addr2, kbd_data_in, kbd_data_out, kbd_wt,
ser0_en, ser0_wr, ser0_addr, ser0_data_in, ser0_data_out, ser0_wt,
ser1_en, ser1_wr, ser1_addr, ser1_data_in, ser1_data_out, ser1_wt,
dsk_en, dsk_wr, dsk_addr, dsk_data_in, dsk_data_out, dsk_wt);
//
// busctrl.v -- bus controller
//
 
module busctrl(cpu_en, cpu_wr, cpu_size, cpu_addr,
cpu_data_out, cpu_data_in, cpu_wt,
ram_en, ram_wr, ram_size, ram_addr,
ram_data_in, ram_data_out, ram_wt,
rom_en, rom_wr, rom_size, rom_addr,
rom_data_out, rom_wt,
tmr_en, tmr_wr, tmr_addr,
tmr_data_in, tmr_data_out, tmr_wt,
dsp_en, dsp_wr, dsp_addr,
dsp_data_in, dsp_data_out, dsp_wt,
kbd_en, kbd_wr, kbd_addr,
kbd_data_in, kbd_data_out, kbd_wt,
ser0_en, ser0_wr, ser0_addr,
ser0_data_in, ser0_data_out, ser0_wt,
ser1_en, ser1_wr, ser1_addr,
ser1_data_in, ser1_data_out, ser1_wt,
dsk_en, dsk_wr, dsk_addr,
dsk_data_in, dsk_data_out, dsk_wt);
// cpu
input cpu_en;
input cpu_wr;
33,7 → 46,7
// tmr
output tmr_en;
output tmr_wr;
output tmr_addr2;
output tmr_addr;
output [31:0] tmr_data_in;
input [31:0] tmr_data_out;
input tmr_wt;
47,7 → 60,7
// kbd
output kbd_en;
output kbd_wr;
output kbd_addr2;
output kbd_addr;
output [7:0] kbd_data_in;
input [7:0] kbd_data_out;
input kbd_wt;
75,13 → 88,20
 
wire i_o_en;
 
// decoder
//
// address decoder
//
// RAM: architectural limit = 512 MB
// board limit = 32 MB
assign ram_en =
(cpu_en == 1 && cpu_addr[31:29] == 3'b000
&& cpu_addr[28:25] == 4'b0000) ? 1 : 0;
// ROM: architectural limit = 256 MB
// board limit = 2 MB
assign rom_en =
(cpu_en == 1 && cpu_addr[31:28] == 4'b0010
&& cpu_addr[27:21] == 7'b0000000) ? 1 : 0;
// I/O: architectural limit = 256 MB
assign i_o_en =
(cpu_en == 1 && cpu_addr[31:28] == 4'b0011) ? 1 : 0;
assign tmr_en =
92,10 → 112,10
(i_o_en == 1 && cpu_addr[27:20] == 8'h02) ? 1 : 0;
assign ser0_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h03
&& cpu_addr[ 5: 4] == 2'b00) ? 1 : 0;
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
assign ser1_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h03
&& cpu_addr[ 5: 4] == 2'b01) ? 1 : 0;
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsk_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
 
134,7 → 154,7
 
// to tmr
assign tmr_wr = cpu_wr;
assign tmr_addr2 = cpu_addr[2];
assign tmr_addr = cpu_addr[2];
assign tmr_data_in[31:0] = cpu_data_out[31:0];
 
// to dsp
144,7 → 164,7
 
// to kbd
assign kbd_wr = cpu_wr;
assign kbd_addr2 = cpu_addr[2];
assign kbd_addr = cpu_addr[2];
assign kbd_data_in[7:0] = cpu_data_out[7:0];
 
// to ser0
/xsa-xst-3/eco32.ucf
1,6 → 1,7
#PACE: Start of Constraints generated by PACE
#
# eco32.ucf -- ECO32 user constraints for XSA-3S1000 + XST-3 board
#
 
#PACE: Start of PACE I/O Pin Assignments
NET "ata_cs0_n" LOC = "g15" ;
NET "ata_cs1_n" LOC = "g14" ;
NET "ata_dmack_n" LOC = "k1" ;
133,9 → 134,3
NET "slot1_cs_n" LOC = "e15" ;
NET "slot2_cs_n" LOC = "d16" ;
NET "vsync" LOC = "d8" ;
 
#PACE: Start of PACE Area Constraints
 
#PACE: Start of PACE Prohibit Constraints
 
#PACE: End of Constraints generated by PACE

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.