URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32/trunk/fpga
- from Rev 67 to Rev 68
- ↔ Reverse comparison
Rev 67 → Rev 68
/src/eco32.v
1,5 → 1,5
// |
// eco32.v -- toplevel description of the ECO32 system |
// eco32.v -- ECO32 top-level description |
// |
|
|
24,11 → 24,11
flash_byte_n, |
flash_a, |
flash_d, |
hsync, |
vsync, |
r, |
g, |
b, |
vga_hsync, |
vga_vsync, |
vga_r, |
vga_g, |
vga_b, |
ps2_clk, |
ps2_data, |
rs232_0_rxd, |
74,11 → 74,11
output [19:0] flash_a; |
input [15:0] flash_d; |
// VGA display |
output hsync; |
output vsync; |
output [2:0] r; |
output [2:0] g; |
output [2:0] b; |
output vga_hsync; |
output vga_vsync; |
output [2:0] vga_r; |
output [2:0] vga_g; |
output [2:0] vga_b; |
// keyboard |
input ps2_clk; |
input ps2_data; |
355,11 → 355,11
.data_in(dsp_data_in[15:0]), |
.data_out(dsp_data_out[15:0]), |
.wt(dsp_wt), |
.hsync(hsync), |
.vsync(vsync), |
.r(r[2:0]), |
.g(g[2:0]), |
.b(b[2:0]) |
.hsync(vga_hsync), |
.vsync(vga_vsync), |
.r(vga_r[2:0]), |
.g(vga_g[2:0]), |
.b(vga_b[2:0]) |
); |
|
kbd kbd1( |
/src/tmr/tmr.v
1,3 → 1,8
// |
// tmr.v -- programmable timer |
// |
|
|
module tmr(clk, reset, |
en, wr, addr, |
data_in, data_out, |
12,7 → 17,7
output wt; |
output irq; |
|
reg [15:0] prescaler; |
reg [5:0] prescaler; |
reg tick; |
reg [31:0] counter; |
reg [31:0] divisor; |
23,11 → 28,11
|
always @(posedge clk) begin |
if (reset == 1) begin |
prescaler <= 16'd50000; |
prescaler <= 6'd50; |
tick <= 0; |
end else begin |
if (prescaler == 16'd1) begin |
prescaler <= 16'd50000; |
if (prescaler == 6'd1) begin |
prescaler <= 6'd50; |
tick <= 1; |
end else begin |
prescaler <= prescaler - 1; |
/xsa-xst-3/eco32.ucf
8,9 → 8,9
NET "ata_dmarq" LOC = "l4" ; |
NET "ata_intrq" LOC = "h15" ; |
NET "ata_iordy" LOC = "l2" ; |
NET "b<0>" LOC = "c9" ; |
NET "b<1>" LOC = "e7" ; |
NET "b<2>" LOC = "d5" ; |
NET "vga_b<0>" LOC = "c9" ; |
NET "vga_b<1>" LOC = "e7" ; |
NET "vga_b<2>" LOC = "d5" ; |
NET "clk_in" LOC = "p8" ; |
NET "ether_cs_n" LOC = "g13" ; |
NET "flash_a<0>" LOC = "n5" ; |
54,10 → 54,10
NET "flash_oe_n" LOC = "p5" ; |
NET "flash_rst_n" LOC = "p16" ; |
NET "flash_we_n" LOC = "m13" ; |
NET "g<0>" LOC = "a8" ; |
NET "g<1>" LOC = "a5" ; |
NET "g<2>" LOC = "c3" ; |
NET "hsync" LOC = "b7" ; |
NET "vga_g<0>" LOC = "a8" ; |
NET "vga_g<1>" LOC = "a5" ; |
NET "vga_g<2>" LOC = "c3" ; |
NET "vga_hsync" LOC = "b7" ; |
NET "pbus_a<0>" LOC = "l5" ; |
NET "pbus_a<1>" LOC = "n2" ; |
NET "pbus_a<2>" LOC = "m3" ; |
83,9 → 83,9
NET "pbus_write_n" LOC = "r1" ; |
NET "ps2_clk" LOC = "b16" ; |
NET "ps2_data" LOC = "e13" ; |
NET "r<0>" LOC = "c8" ; |
NET "r<1>" LOC = "d6" ; |
NET "r<2>" LOC = "b1" ; |
NET "vga_r<0>" LOC = "c8" ; |
NET "vga_r<1>" LOC = "d6" ; |
NET "vga_r<2>" LOC = "b1" ; |
NET "reset_inout_n" LOC = "d15" ; |
NET "rs232_0_rxd" LOC = "g5" ; |
NET "rs232_0_txd" LOC = "j2" ; |
133,4 → 133,4
NET "sdram_we_n" LOC = "b10" ; |
NET "slot1_cs_n" LOC = "e15" ; |
NET "slot2_cs_n" LOC = "d16" ; |
NET "vsync" LOC = "d8" ; |
NET "vga_vsync" LOC = "d8" ; |