URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32/trunk/monitor/monitor
- from Rev 180 to Rev 88
- ↔ Reverse comparison
Rev 180 → Rev 88
/common/mmu.c
14,7 → 14,6
static Word tlbEntryHi; |
static Word tlbEntryLo; |
static Word badAddress; |
static Word badAccess; |
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Word mmuReadWord(Word vAddr) { |
87,16 → 86,6
} |
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Word mmuGetBadAccs(void) { |
return badAccess; |
} |
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void mmuSetBadAccs(Word value) { |
badAccess = value; |
} |
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TLB_Entry mmuGetTLB(int index) { |
Word hi; |
Word lo; |
/common/start.h
14,7 → 14,6
Word tlbHi; /* TLB EntryHi register */ |
Word tlbLo; /* TLB EntryLo register */ |
Word badAddr; /* bad address register */ |
Word badAccs; /* bad access register */ |
} UserContext; |
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typedef struct { |
/common/mmu.h
15,14 → 15,7
#define TLB_WRITE (1 << 1) /* write bit in EntryLo */ |
#define TLB_VALID (1 << 0) /* valid bit in EntryLo */ |
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#define MMU_ACCS_MASK 0x07 /* bits used in BadAccs */ |
#define MMU_ACCS_READ 0x00 /* access type = read */ |
#define MMU_ACCS_WRITE 0x04 /* access type = write */ |
#define MMU_ACCS_BYTE 0x00 /* access width = byte */ |
#define MMU_ACCS_HALF 0x01 /* access width = half */ |
#define MMU_ACCS_WORD 0x02 /* access width = word */ |
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typedef struct { |
Word page; /* 20 high-order bits of virtual address */ |
Word frame; /* 20 high-order bits of physical address */ |
46,8 → 39,6
void mmuSetEntryLo(Word value); |
Word mmuGetBadAddr(void); |
void mmuSetBadAddr(Word value); |
Word mmuGetBadAccs(void); |
void mmuSetBadAccs(Word value); |
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TLB_Entry mmuGetTLB(int index); |
void mmuSetTLB(int index, TLB_Entry tlbEntry); |
/common/command.c
706,10 → 706,8
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static void doTLB(char *tokens[], int n) { |
static char *mmuAccsWidth[4] = { "byte", "half", "word", "????" }; |
int index; |
TLB_Entry tlbEntry; |
Word mmuAccs; |
Word data; |
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if (n == 1) { |
720,15 → 718,10
tlbEntry.write ? 'w' : '-', |
tlbEntry.valid ? 'v' : '-'); |
} |
printf("Index (1) %08X\n", mmuGetIndex()); |
printf("EntryHi (2) %08X\n", mmuGetEntryHi()); |
printf("EntryLo (3) %08X\n", mmuGetEntryLo()); |
printf("BadAddr (4) %08X\n", mmuGetBadAddr()); |
mmuAccs = mmuGetBadAccs(); |
printf("BadAccs (5) %08X (%s %s)\n", |
mmuAccs, |
(mmuAccs & MMU_ACCS_WRITE) ? "write" : "read", |
mmuAccsWidth[mmuAccs & 0x03]); |
printf("Index(1) %08X\n", mmuGetIndex()); |
printf("EntryHi(2) %08X\n", mmuGetEntryHi()); |
printf("EntryLo(3) %08X\n", mmuGetEntryLo()); |
printf("BadAddr(4) %08X\n", mmuGetBadAddr()); |
} else if (n == 2) { |
if (!getDecNumber(tokens[1], &index) || index < 0 || index >= TLB_SIZE) { |
printf("illegal TLB index\n"); |
/common/cpu.c
268,7 → 268,6
userContext.tlbHi = mmuGetEntryHi(); |
userContext.tlbLo = mmuGetEntryLo(); |
userContext.badAddr = mmuGetBadAddr(); |
userContext.badAccs = mmuGetBadAccs(); |
if (saveState(&stepState)) { |
origReturn = monitorReturn; |
monitorReturn = &stepState; |
284,7 → 283,6
mmuSetEntryHi(userContext.tlbHi); |
mmuSetEntryLo(userContext.tlbLo); |
mmuSetBadAddr(userContext.badAddr); |
mmuSetBadAccs(userContext.badAccs); |
mmuWriteWord(nextAddr, nextInstr); |
if (nextAddr == pc) { |
return; |
333,7 → 331,6
userContext.tlbHi = mmuGetEntryHi(); |
userContext.tlbLo = mmuGetEntryLo(); |
userContext.badAddr = mmuGetBadAddr(); |
userContext.badAccs = mmuGetBadAccs(); |
if (saveState(&runState)) { |
origReturn = monitorReturn; |
monitorReturn = &runState; |
349,7 → 346,6
mmuSetEntryHi(userContext.tlbHi); |
mmuSetEntryLo(userContext.tlbLo); |
mmuSetBadAddr(userContext.badAddr); |
mmuSetBadAccs(userContext.badAccs); |
if (breakSet) { |
mmuWriteWord(breakAddr, instr); |
} |
/boards/xsa-xst-3/start.s
14,9 → 14,8
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo |
.set TLB_ENTRIES,32 ; number of TLB entries |
.set BAD_ADDRESS,4 ; reg # of bad address reg |
.set BAD_ACCESS,5 ; reg # of bad access reg |
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.set USER_CONTEXT_SIZE,38*4 ; size of user context |
.set USER_CONTEXT_SIZE,37*4 ; size of user context |
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;*************************************************************** |
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359,8 → 358,6
mvts $8,TLB_ENTRY_LO |
ldw $8,$28,36*4 ; badAddress |
mvts $8,BAD_ADDRESS |
ldw $8,$28,37*4 ; badAccess |
mvts $8,BAD_ACCESS |
;ldw $0,$28,0*4 ; registers |
ldw $1,$28,1*4 |
ldw $2,$28,2*4 |
447,7 → 444,5
stw $8,$28,35*4 ; tlbEntryLo |
mvfs $8,BAD_ADDRESS |
stw $8,$28,36*4 ; badAddress |
mvfs $8,BAD_ACCESS |
stw $8,$28,37*4 ; badAccess |
.syn |
j loadState |
/boards/s3e-500/start.s
14,9 → 14,8
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo |
.set TLB_ENTRIES,32 ; number of TLB entries |
.set BAD_ADDRESS,4 ; reg # of bad address reg |
.set BAD_ACCESS,5 ; reg # of bad access reg |
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.set USER_CONTEXT_SIZE,38*4 ; size of user context |
.set USER_CONTEXT_SIZE,37*4 ; size of user context |
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.set BIO_OUT,0xF1000000 ; board I/O output port |
.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit |
367,8 → 366,6
mvts $8,TLB_ENTRY_LO |
ldw $8,$28,36*4 ; badAddress |
mvts $8,BAD_ADDRESS |
ldw $8,$28,37*4 ; badAccess |
mvts $8,BAD_ACCESS |
;ldw $0,$28,0*4 ; registers |
ldw $1,$28,1*4 |
ldw $2,$28,2*4 |
455,7 → 452,5
stw $8,$28,35*4 ; tlbEntryLo |
mvfs $8,BAD_ADDRESS |
stw $8,$28,36*4 ; badAddress |
mvfs $8,BAD_ACCESS |
stw $8,$28,37*4 ; badAccess |
.syn |
j loadState |