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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /eco32/trunk/monitor
    from Rev 88 to Rev 180
    Reverse comparison

Rev 88 → Rev 180

/monitor/common/mmu.c
14,6 → 14,7
static Word tlbEntryHi;
static Word tlbEntryLo;
static Word badAddress;
static Word badAccess;
 
 
Word mmuReadWord(Word vAddr) {
86,6 → 87,16
}
 
 
Word mmuGetBadAccs(void) {
return badAccess;
}
 
 
void mmuSetBadAccs(Word value) {
badAccess = value;
}
 
 
TLB_Entry mmuGetTLB(int index) {
Word hi;
Word lo;
/monitor/common/start.h
14,6 → 14,7
Word tlbHi; /* TLB EntryHi register */
Word tlbLo; /* TLB EntryLo register */
Word badAddr; /* bad address register */
Word badAccs; /* bad access register */
} UserContext;
 
typedef struct {
/monitor/common/mmu.h
15,7 → 15,14
#define TLB_WRITE (1 << 1) /* write bit in EntryLo */
#define TLB_VALID (1 << 0) /* valid bit in EntryLo */
 
#define MMU_ACCS_MASK 0x07 /* bits used in BadAccs */
#define MMU_ACCS_READ 0x00 /* access type = read */
#define MMU_ACCS_WRITE 0x04 /* access type = write */
#define MMU_ACCS_BYTE 0x00 /* access width = byte */
#define MMU_ACCS_HALF 0x01 /* access width = half */
#define MMU_ACCS_WORD 0x02 /* access width = word */
 
 
typedef struct {
Word page; /* 20 high-order bits of virtual address */
Word frame; /* 20 high-order bits of physical address */
39,6 → 46,8
void mmuSetEntryLo(Word value);
Word mmuGetBadAddr(void);
void mmuSetBadAddr(Word value);
Word mmuGetBadAccs(void);
void mmuSetBadAccs(Word value);
 
TLB_Entry mmuGetTLB(int index);
void mmuSetTLB(int index, TLB_Entry tlbEntry);
/monitor/common/command.c
706,8 → 706,10
 
 
static void doTLB(char *tokens[], int n) {
static char *mmuAccsWidth[4] = { "byte", "half", "word", "????" };
int index;
TLB_Entry tlbEntry;
Word mmuAccs;
Word data;
 
if (n == 1) {
718,10 → 720,15
tlbEntry.write ? 'w' : '-',
tlbEntry.valid ? 'v' : '-');
}
printf("Index(1) %08X\n", mmuGetIndex());
printf("EntryHi(2) %08X\n", mmuGetEntryHi());
printf("EntryLo(3) %08X\n", mmuGetEntryLo());
printf("BadAddr(4) %08X\n", mmuGetBadAddr());
printf("Index (1) %08X\n", mmuGetIndex());
printf("EntryHi (2) %08X\n", mmuGetEntryHi());
printf("EntryLo (3) %08X\n", mmuGetEntryLo());
printf("BadAddr (4) %08X\n", mmuGetBadAddr());
mmuAccs = mmuGetBadAccs();
printf("BadAccs (5) %08X (%s %s)\n",
mmuAccs,
(mmuAccs & MMU_ACCS_WRITE) ? "write" : "read",
mmuAccsWidth[mmuAccs & 0x03]);
} else if (n == 2) {
if (!getDecNumber(tokens[1], &index) || index < 0 || index >= TLB_SIZE) {
printf("illegal TLB index\n");
/monitor/common/cpu.c
268,6 → 268,7
userContext.tlbHi = mmuGetEntryHi();
userContext.tlbLo = mmuGetEntryLo();
userContext.badAddr = mmuGetBadAddr();
userContext.badAccs = mmuGetBadAccs();
if (saveState(&stepState)) {
origReturn = monitorReturn;
monitorReturn = &stepState;
283,6 → 284,7
mmuSetEntryHi(userContext.tlbHi);
mmuSetEntryLo(userContext.tlbLo);
mmuSetBadAddr(userContext.badAddr);
mmuSetBadAccs(userContext.badAccs);
mmuWriteWord(nextAddr, nextInstr);
if (nextAddr == pc) {
return;
331,6 → 333,7
userContext.tlbHi = mmuGetEntryHi();
userContext.tlbLo = mmuGetEntryLo();
userContext.badAddr = mmuGetBadAddr();
userContext.badAccs = mmuGetBadAccs();
if (saveState(&runState)) {
origReturn = monitorReturn;
monitorReturn = &runState;
346,6 → 349,7
mmuSetEntryHi(userContext.tlbHi);
mmuSetEntryLo(userContext.tlbLo);
mmuSetBadAddr(userContext.badAddr);
mmuSetBadAccs(userContext.badAccs);
if (breakSet) {
mmuWriteWord(breakAddr, instr);
}
/monitor/boards/xsa-xst-3/start.s
14,8 → 14,9
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
.set TLB_ENTRIES,32 ; number of TLB entries
.set BAD_ADDRESS,4 ; reg # of bad address reg
.set BAD_ACCESS,5 ; reg # of bad access reg
 
.set USER_CONTEXT_SIZE,37*4 ; size of user context
.set USER_CONTEXT_SIZE,38*4 ; size of user context
 
;***************************************************************
 
358,6 → 359,8
mvts $8,TLB_ENTRY_LO
ldw $8,$28,36*4 ; badAddress
mvts $8,BAD_ADDRESS
ldw $8,$28,37*4 ; badAccess
mvts $8,BAD_ACCESS
;ldw $0,$28,0*4 ; registers
ldw $1,$28,1*4
ldw $2,$28,2*4
444,5 → 447,7
stw $8,$28,35*4 ; tlbEntryLo
mvfs $8,BAD_ADDRESS
stw $8,$28,36*4 ; badAddress
mvfs $8,BAD_ACCESS
stw $8,$28,37*4 ; badAccess
.syn
j loadState
/monitor/boards/s3e-500/start.s
14,8 → 14,9
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
.set TLB_ENTRIES,32 ; number of TLB entries
.set BAD_ADDRESS,4 ; reg # of bad address reg
.set BAD_ACCESS,5 ; reg # of bad access reg
 
.set USER_CONTEXT_SIZE,37*4 ; size of user context
.set USER_CONTEXT_SIZE,38*4 ; size of user context
 
.set BIO_OUT,0xF1000000 ; board I/O output port
.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit
366,6 → 367,8
mvts $8,TLB_ENTRY_LO
ldw $8,$28,36*4 ; badAddress
mvts $8,BAD_ADDRESS
ldw $8,$28,37*4 ; badAccess
mvts $8,BAD_ACCESS
;ldw $0,$28,0*4 ; registers
ldw $1,$28,1*4
ldw $2,$28,2*4
452,5 → 455,7
stw $8,$28,35*4 ; tlbEntryLo
mvfs $8,BAD_ADDRESS
stw $8,$28,36*4 ; badAddress
mvfs $8,BAD_ACCESS
stw $8,$28,37*4 ; badAccess
.syn
j loadState

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