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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

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  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/monitor
    from Rev 49 to Rev 50
    ↔ Reverse comparison
  •

Rev 49 → Rev 50

/monitor-digilent/start.h
42,6 → 42,11
int dskcap(int dskno);
int dskio(int dskno, char cmd, int sct, Word addr, int nscts);
 
void setISR(Word ptr);
void setUMSR(Word ptr);
extern Word isrPtr;
extern Word umsrPtr;
 
Word getTLB_HI(int index);
Word getTLB_LO(int index);
void setTLB(int index, Word entryHi, Word entryLo);
/monitor-digilent/start.s
3,9 → 3,12
;
 
.set dmapaddr,0xC0000000 ; base of directly mapped addresses
.set stacktop,0xC4000000 ; monitor stack is at top of memory
.set stacktop,0xC0010000 ; monitor stack is at top of 64K
 
.set PSW,0 ; reg # of PSW
.set V_SHIFT,27 ; interrupt vector ctrl bit
.set V,1 << V_SHIFT
 
.set TLB_INDEX,1 ; reg # of TLB Index
.set TLB_ENTRY_HI,2 ; reg # of TLB EntryHi
.set TLB_ENTRY_LO,3 ; reg # of TLB EntryLo
13,6 → 16,9
 
.set USER_CONTEXT_SIZE,36*4 ; size of user context
 
.set BIO_OUT,0xF1000000 ; board I/O output port
.set SPI_EN,0x80000000 ; SPI bus enable ctrl bit
 
;***************************************************************
 
.import _ecode
55,6 → 61,11
.export dskcap
.export dskio
 
.export setISR
.export setUMSR
.export isrPtr
.export umsrPtr
 
.export getTLB_HI
.export getTLB_LO
.export setTLB
129,6 → 140,21
dskio:
j dio
 
reserved1:
j reserved1
 
reserved2:
j reserved2
 
reserved3:
j reserved3
 
setISR:
j setISR1
 
setUMSR:
j setUMSR1
 
;***************************************************************
 
.code
135,9 → 161,15
.align 4
 
start:
; force CPU into a defined state
mvts $0,PSW ; disable interrupts and user mode
; let irq/exc vectors point to RAM
add $8,$0,V
mvts $8,PSW
 
; disable flash ROM, enable SPI bus
add $8,$0,BIO_OUT
add $9,$0,SPI_EN
stw $9,$8,0
 
; initialize TLB
mvts $0,TLB_ENTRY_LO ; invalidate all TLB entries
add $8,$0,dmapaddr ; by impossible virtual page number
187,6 → 219,9
 
;***************************************************************
 
.code
.align 4
 
; Word getTLB_HI(int index)
getTLB_HI:
mvts $4,TLB_INDEX
211,6 → 246,9
 
;***************************************************************
 
.code
.align 4
 
; int dskcap(int dskno)
dcap:
bne $4,$0,dcapser
238,6 → 276,30
.code
.align 4
 
; void setISR(Word ptr)
setISR1:
stw $4,$0,isrPtr
jr $31
 
; void setUMSR(Word ptr)
setUMSR1:
stw $4,$0,umsrPtr
jr $31
 
.data
.align 4
 
isrPtr:
.word 0
 
umsrPtr:
.word 0
 
;***************************************************************
 
.code
.align 4
 
; Bool saveState(MonitorState *msp)
; always return 'true' here
saveState:
297,7 → 359,7
.nosyn
ldw $8,$28,33*4 ; tlbIndex
mvts $8,TLB_INDEX
ldw $8,$28,34*4 ; tlbWntryHi
ldw $8,$28,34*4 ; tlbEntryHi
mvts $8,TLB_ENTRY_HI
ldw $8,$28,35*4 ; tlbEntryLo
mvts $8,TLB_ENTRY_LO
/monitor-digilent/load.c
172,7 → 172,7
case '3':
/* S3 record: 4 byte load address + data (load data) */
addr = (getByte( 4) << 24) |
(getByte( 6) << 26) |
(getByte( 6) << 16) |
(getByte( 8) << 8) |
(getByte(10) << 0);
addr |= 0xC0000000;
187,7 → 187,7
case '7':
/* S7 record: 4 byte start address (set PC, stop loading) */
addr = (getByte( 4) << 24) |
(getByte( 6) << 26) |
(getByte( 6) << 16) |
(getByte( 8) << 8) |
(getByte(10) << 0);
addr |= 0xC0000000;
/monitor-digilent/cpu.c
87,10 → 87,10
 
 
static char *cause[32] = {
/* 0 */ "terminal 0 transmitter interrupt",
/* 1 */ "terminal 0 receiver interrupt",
/* 2 */ "terminal 1 transmitter interrupt",
/* 3 */ "terminal 1 receiver interrupt",
/* 0 */ "serial line 0 xmt interrupt",
/* 1 */ "serial line 0 rcv interrupt",
/* 2 */ "serial line 1 xmt interrupt",
/* 3 */ "serial line 1 rcv interrupt",
/* 4 */ "keyboard interrupt",
/* 5 */ "unknown interrupt",
/* 6 */ "unknown interrupt",
206,6 → 206,7
}
break;
default:
/* this should never happen */
printf("cannot compute condition code %d\n", cc);
break;
}
213,13 → 214,12
}
 
 
Bool cpuStep(void) {
void cpuStep(void) {
Word instr;
int opcode;
int reg1, reg2;
Half immed;
Word offset;
Bool canStep;
Word nextAddr;
Word nextInstr;
int i;
232,10 → 232,9
reg2 = (instr >> 16) & 0x1F;
immed = instr & 0x0000FFFF;
offset = instr & 0x03FFFFFF;
canStep = true;
switch (stepType[opcode]) {
case 1:
/* next instruction follows current one */
/* next instruction follows current one immediately */
nextAddr = pc + 4;
break;
case 2:
251,17 → 250,13
break;
case 4:
/* next instruction reached by jump to register contents */
nextAddr = RR(reg1);
nextAddr = RR(reg1) & 0xFFFFFFFC;
break;
default:
printf("cannot single-step instruction with opcode 0x%02X\n",
opcode);
canStep = false;
break;
return;
}
if (!canStep) {
return false;
}
nextInstr = mmuReadWord(nextAddr);
mmuWriteWord(nextAddr, BREAK);
for (i = 0; i < 32; i++) {
268,7 → 263,7
userContext.reg[i] = RR(i);
}
userContext.reg[30] = pc;
userContext.psw = psw & ~PSW_V;
userContext.psw = psw;
userContext.tlbIndex = mmuGetIndex();
userContext.tlbHi = mmuGetEntryHi();
userContext.tlbLo = mmuGetEntryLo();
282,30 → 277,35
WR(i, userContext.reg[i]);
}
pc = userContext.reg[30];
psw = userContext.psw | (psw & PSW_V);
psw = userContext.psw;
mmuSetIndex(userContext.tlbIndex);
mmuSetEntryHi(userContext.tlbHi);
mmuSetEntryLo(userContext.tlbLo);
mmuWriteWord(nextAddr, nextInstr);
if (nextAddr == pc) {
return true;
return;
}
if ((psw & PSW_V) == 0) {
printf("unexpected %s occurred\n",
exceptionToString((psw & PSW_PRIO_MASK) >> 16));
return false;
}
if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
(mmuGetEntryHi() & 0x80000000) == 0) {
pc = 0xC0000008;
/* TLB user miss */
if (umsrPtr == 0x00000000) {
printf("unexpected TLB user miss exception occurred\n");
return;
}
pc = umsrPtr;
} else {
pc = 0xC0000004;
/* any other exception */
if (isrPtr == 0x00000000) {
printf("unexpected %s occurred\n",
exceptionToString((psw & PSW_PRIO_MASK) >> 16));
return;
}
pc = isrPtr;
}
return true;
}
 
 
Bool cpuRun(void) {
void cpuRun(void) {
Word instr;
int i;
MonitorState runState;
313,9 → 313,7
 
if (breakSet && breakAddr == pc) {
/* single-step one instruction */
if (!cpuStep()) {
return false;
}
cpuStep();
}
while (1) {
if (breakSet) {
326,7 → 324,7
userContext.reg[i] = RR(i);
}
userContext.reg[30] = pc;
userContext.psw = psw & ~PSW_V;
userContext.psw = psw;
userContext.tlbIndex = mmuGetIndex();
userContext.tlbHi = mmuGetEntryHi();
userContext.tlbLo = mmuGetEntryLo();
340,7 → 338,7
WR(i, userContext.reg[i]);
}
pc = userContext.reg[30];
psw = userContext.psw | (psw & PSW_V);
psw = userContext.psw;
mmuSetIndex(userContext.tlbIndex);
mmuSetEntryHi(userContext.tlbHi);
mmuSetEntryLo(userContext.tlbLo);
348,20 → 346,24
mmuWriteWord(breakAddr, instr);
}
if (breakSet && breakAddr == pc) {
return true;
return;
}
if ((psw & PSW_V) == 0) {
printf("unexpected %s occurred\n",
exceptionToString((psw & PSW_PRIO_MASK) >> 16));
return false;
}
if ((psw & PSW_PRIO_MASK) >> 16 == 21 &&
(mmuGetEntryHi() & 0x80000000) == 0) {
pc = 0xC0000008;
/* TLB user miss */
if (umsrPtr == 0x00000000) {
printf("unexpected TLB user miss exception occurred\n");
return;
}
pc = umsrPtr;
} else {
pc = 0xC0000004;
/* any other exception */
if (isrPtr == 0x00000000) {
printf("unexpected %s occurred\n",
exceptionToString((psw & PSW_PRIO_MASK) >> 16));
return;
}
pc = isrPtr;
}
}
/* never reached */
return false;
}
/monitor-digilent/copy/copy.s
0,0 → 1,34
;
; copy.s -- copy a program from ROM to RAM before executing it
;
 
.set dst,0xC0000000 ; destination is start of RAM
.set len,0x0000C000 ; number of bytes to be copied
 
.set PSW,0 ; reg # of PSW
 
reset:
j start
 
interrupt:
j interrupt ; we better have no interrupts
 
userMiss:
j userMiss ; and no user TLB misses
 
start:
mvts $0,PSW ; disable interrupts and user mode
add $8,$0,src
add $9,$0,dst
add $10,$9,len
loop:
ldw $11,$8,0 ; copy word
stw $11,$9,0
add $8,$8,4 ; bump pointers
add $9,$9,4
bltu $9,$10,loop ; more?
add $8,$0,dst ; start execution
jr $8
 
; the program to be copied follows immediately
src:
/monitor-digilent/copy/Makefile
0,0 → 1,19
#
# Makefile for ROM-to-RAM copy program
#
 
BUILD = ../../../build
 
.PHONY: all clean
 
all: copy.bin
 
copy.bin: copy.o
$(BUILD)/bin/ld -o copy.bin -m copy.map \
-h -rc 0xE0000000 copy.o
 
copy.o: copy.s
$(BUILD)/bin/as -o copy.o copy.s
 
clean:
rm -f *~ copy.o copy.bin copy.map
/monitor-digilent/cpu.h
33,8 → 33,8
 
char *exceptionToString(int exception);
 
Bool cpuStep(void);
Bool cpuRun(void);
void cpuStep(void);
void cpuRun(void);
 
 
#endif /* _CPU_H_ */
/monitor-digilent/Makefile
11,21 → 11,29
 
.PHONY: all install clean
 
all: monitor.bin monitor.exo
all: monitor.bin monitor.mcs
 
install: monitor.bin monitor.exo
install: monitor.bin monitor.mcs
mkdir -p $(BUILD)/monitor
cp monitor.bin $(BUILD)/monitor
cp monitor.exo $(BUILD)/monitor
cp monitor.mcs $(BUILD)/monitor
 
monitor.exo: monitor.bin
$(BUILD)/bin/bin2exo -S2 0 monitor.bin monitor.exo
monitor.mcs: monitor.bin
$(BUILD)/bin/bin2mcs 0x00000000 monitor.bin monitor.mcs
 
monitor.bin: $(SRC)
$(BUILD)/bin/lcc -A -Wo-rom -Wl-rd -Wl0xC3FFC000 \
-Wl-m -Wlmonitor.map -o monitor.bin $(SRC)
monitor.bin: copy/copy.bin $(SRC)
$(BUILD)/bin/lcc -A -Wo-rom -Wl-rc -Wl0xC0000000 \
-Wl-rd -Wl0xC000C000 \
-Wl-m -Wlmonitor.map \
-o prelim.bin $(SRC)
cat copy/copy.bin prelim.bin >monitor.bin
rm prelim.bin
 
copy/copy.bin:
$(MAKE) -C copy all
 
clean:
rm -f *~
rm -f monitor.map monitor.bin
rm -f monitor.exo
rm -f monitor.mcs
$(MAKE) -C copy clean
/monitor-digilent/command.c
192,7 → 192,7
Word brk;
 
brk = cpuGetBreak();
printf("Brk ");
printf("brk ");
if (cpuTestBreak()) {
printf("%08X", brk);
} else {
383,7 → 383,7
cpuRun();
}
addr = cpuGetPC();
printf("Break at %08X\n", addr);
printf("break at %08X\n", addr);
showPC();
}
 
/monitor-digilent/main.c
15,9 → 15,10
int main(void) {
char *line;
 
printf("\n\nECO32 Machine Monitor 1.1\n\n");
printf("\n\nECO32 Machine Monitor 1.3\n\n");
initInstrTable();
cpuSetPC(0xC0000000);
cpuSetPC(0xC0010000);
cpuSetPSW(0x08000000);
while (1) {
line = getLine("ECO32 > ");
addHist(line);

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