OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk/sim
    from Rev 82 to Rev 83
    ↔ Reverse comparison
  •

Rev 82 → Rev 83

/command.c
327,7 → 327,7
num4 = num1 - num2;
cPrintf("add = %08X, sub = %08X\n", num3, num4);
} else {
help();
help01();
}
}
 
348,7 → 348,7
return;
}
} else {
help();
help02();
return;
}
addr &= ~0x00000003;
399,7 → 399,7
return;
}
} else {
help();
help03();
return;
}
addr &= ~0x00000003;
432,7 → 432,7
cpuSetBreak(addr);
showBreakAndTotal();
} else {
help();
help04();
}
}
 
449,7 → 449,7
return;
}
} else {
help();
help05();
return;
}
cPrintf("CPU is running, press ^C to interrupt...\n");
473,7 → 473,7
return;
}
} else {
help();
help06();
return;
}
for (i = 0; i < count; i++) {
497,7 → 497,7
cpuSetPC(addr);
showPC();
} else {
help();
help07();
}
}
 
557,7 → 557,7
showIRQ();
explainPSW(data);
} else {
help();
help08();
}
}
 
598,7 → 598,7
}
cpuSetReg(reg, data);
} else {
help();
help09();
}
}
 
633,7 → 633,7
return;
}
} else {
help();
help10();
return;
}
psw = cpuGetPSW();
707,7 → 707,7
data = tmpData;
mmuWriteWord(addr, data, psw & PSW_UM);
} else {
help();
help11();
}
}
 
742,7 → 742,7
data = (Half) tmpData;
mmuWriteHalf(addr, data, psw & PSW_UM);
} else {
help();
help12();
}
}
 
777,7 → 777,7
data = (Byte) tmpData;
mmuWriteByte(addr, data, psw & PSW_UM);
} else {
help();
help13();
}
}
 
810,7 → 810,7
tlbEntry.write ? 'w' : '-',
tlbEntry.valid ? 'v' : '-');
} else if (n == 3) {
help();
help14();
} else if (n == 4) {
if (!getDecNumber(tokens[1], &index) || index < 0 || index >= TLB_SIZE) {
cPrintf("illegal TLB index\n");
838,7 → 838,7
tlbEntry.write ? 'w' : '-',
tlbEntry.valid ? 'v' : '-');
} else {
help();
help14();
}
}
 
857,7 → 857,7
mmuReset();
cpuReset();
} else {
help();
help15();
}
}
 
866,7 → 866,7
if (n == 1) {
quit = true;
} else {
help();
help16();
}
}
 

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