OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /eco32/trunk
    from Rev 189 to Rev 190
    ↔ Reverse comparison
  •

Rev 189 → Rev 190

/fpga/src/eco32.v
106,6 → 106,8
output slot2_cs_n;
// ethernet
output ether_cs_n;
// board I/O
//!!!!!
 
// clk_reset
wire clk;
192,6 → 194,13
wire [31:0] dsk_data_out;
wire dsk_wt;
wire dsk_irq;
// bio
wire bio_en;
wire bio_wr;
wire bio_addr;
wire [31:0] bio_data_in;
wire [31:0] bio_data_out;
wire bio_wt;
 
clk_reset clk_reset1(
.clk_in(clk_in),
275,7 → 284,14
.dsk_addr(dsk_addr[19:2]),
.dsk_data_in(dsk_data_in[31:0]),
.dsk_data_out(dsk_data_out[31:0]),
.dsk_wt(dsk_wt)
.dsk_wt(dsk_wt),
// bio
.bio_en(bio_en),
.bio_wr(bio_wr),
.bio_addr(bio_addr),
.bio_data_in(bio_data_in[31:0]),
.bio_data_out(bio_data_out[31:0]),
.bio_wt(bio_wt)
);
 
cpu cpu1(
460,4 → 476,15
assign slot2_cs_n = 1;
assign ether_cs_n = 1;
 
bio bio1(
.clk(clk),
.reset(reset),
.en(bio_en),
.wr(bio_wr),
.addr(bio_addr),
.data_in(bio_data_in[31:0]),
.data_out(bio_data_out[31:0]),
.wt(bio_wt)
);
 
endmodule
/fpga/src/bio/bio.v
0,0 → 1,40
//
// bio.v -- board specific I/O
//
 
 
module bio(clk, reset,
en, wr, addr,
data_in, data_out,
wt);
// internal interface
input clk;
input reset;
input en;
input wr;
input addr;
input [31:0] data_in;
output [31:0] data_out;
output wt;
// external interface
 
reg [31:0] bio_out;
wire [31:0] bio_in;
 
always @(posedge clk) begin
if (reset) begin
bio_out[31:0] <= 32'h0;
end else begin
if (en & wr & ~addr) begin
bio_out[31:0] <= data_in[31:0];
end
end
end
 
assign data_out[31:0] =
(addr == 0) ? bio_out[31:0] : bio_in[31:0];
assign wt = 0;
 
assign bio_in[31:0] = { 28'h0, 4'h0 };
 
endmodule
/fpga/src/busctrl/busctrl.v
22,7 → 22,9
ser1_en, ser1_wr, ser1_addr,
ser1_data_in, ser1_data_out, ser1_wt,
dsk_en, dsk_wr, dsk_addr,
dsk_data_in, dsk_data_out, dsk_wt);
dsk_data_in, dsk_data_out, dsk_wt,
bio_en, bio_wr, bio_addr,
bio_data_in, bio_data_out, bio_wt);
// cpu
input cpu_en;
input cpu_wr;
95,6 → 97,13
output [31:0] dsk_data_in;
input [31:0] dsk_data_out;
input dsk_wt;
// bio
output bio_en;
output bio_wr;
output bio_addr;
output [31:0] bio_data_in;
input [31:0] bio_data_out;
input bio_wt;
 
wire i_o_en;
 
132,6 → 141,9
&& cpu_addr[19:12] == 8'h01) ? 1 : 0;
assign dsk_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h04) ? 1 : 0;
assign bio_en =
(i_o_en == 1 && cpu_addr[27:20] == 8'h10
&& cpu_addr[19:12] == 8'h00) ? 1 : 0;
 
// to cpu
assign cpu_wt =
144,6 → 156,7
(ser0_en == 1) ? ser0_wt :
(ser1_en == 1) ? ser1_wt :
(dsk_en == 1) ? dsk_wt :
(bio_en == 1) ? bio_wt :
1;
assign cpu_data_in[31:0] =
(ram_en == 1) ? ram_data_out[31:0] :
155,6 → 168,7
(ser0_en == 1) ? { 24'h000000, ser0_data_out[7:0] } :
(ser1_en == 1) ? { 24'h000000, ser1_data_out[7:0] } :
(dsk_en == 1) ? dsk_data_out[31:0] :
(bio_en == 1) ? bio_data_out[31:0] :
32'h00000000;
 
// to ram
203,4 → 217,9
assign dsk_addr[19:2] = cpu_addr[19:2];
assign dsk_data_in[31:0] = cpu_data_out[31:0];
 
// to bio
assign bio_wr = cpu_wr;
assign bio_addr = cpu_addr[2];
assign bio_data_in[31:0] = cpu_data_out[31:0];
 
endmodule
/fpga/xsa-xst-3/eco32.xise
17,7 → 17,7
<files>
<file xil_pn:name="../src/eco32.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../src/clk_reset/clk_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
115,6 → 115,10
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../src/bio/bio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="eco32.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
/fpga/xsa-xst-3/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.