URL
https://opencores.org/ocsvn/eco32/eco32/trunk
Subversion Repositories eco32
Compare Revisions
- This comparison shows the changes necessary to convert path
/eco32/trunk
- from Rev 216 to Rev 217
- ↔ Reverse comparison
Rev 216 → Rev 217
/fpga/boards/xsa-xst-3/build/eco32.xise
15,111 → 15,111
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../src/eco32.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../toplevel/eco32.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> |
</file> |
<file xil_pn:name="../src/clk_reset/clk_reset.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/clk_reset/clk_reset.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> |
</file> |
<file xil_pn:name="../src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/busctrl/busctrl.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> |
</file> |
<file xil_pn:name="../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> |
</file> |
<file xil_pn:name="../src/ram/ram.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ram/ram.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> |
</file> |
<file xil_pn:name="../src/ram/sdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<file xil_pn:name="../../../src/ram/sdramcntl.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
</file> |
<file xil_pn:name="../src/rom/rom.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/rom/rom.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> |
</file> |
<file xil_pn:name="../src/ser/rcv.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ser/rcv.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="../src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
</file> |
<file xil_pn:name="../src/ser/ser.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ser/ser.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> |
</file> |
<file xil_pn:name="../src/ser/xmt.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ser/xmt.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="../src/ser/xmtbuf.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/ser/xmtbuf.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
</file> |
<file xil_pn:name="../src/dsk/atabuf.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsk/atabuf.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
</file> |
<file xil_pn:name="../src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsk/atactrl.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
</file> |
<file xil_pn:name="../src/dsk/ataio.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsk/ataio.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
</file> |
<file xil_pn:name="../src/dsk/dsk.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsk/dsk.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> |
</file> |
<file xil_pn:name="../src/kbd/kbd.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/kbd/kbd.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> |
</file> |
<file xil_pn:name="../src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
</file> |
<file xil_pn:name="../src/tmr/tmr.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/tmr/tmr.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> |
</file> |
<file xil_pn:name="../src/dsp/chrgen.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/common/chrgen.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
</file> |
<file xil_pn:name="../src/dsp/display.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/bpp9/display.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
</file> |
<file xil_pn:name="../src/dsp/dsp.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/bpp9/dsp.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> |
</file> |
<file xil_pn:name="../src/dsp/dspmem.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/common/dspmem.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
</file> |
<file xil_pn:name="../src/dsp/pixel.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/bpp9/pixel.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
</file> |
<file xil_pn:name="../src/dsp/timing.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/dsp/common/timing.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
</file> |
<file xil_pn:name="../src/bio/bio.v" xil_pn:type="FILE_VERILOG"> |
<file xil_pn:name="../../../src/bio/bio.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> |
</file> |
<file xil_pn:name="eco32.ucf" xil_pn:type="FILE_UCF"> |
<file xil_pn:name="../toplevel/eco32.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
</files> |
223,7 → 223,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Module|eco32" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/eco32.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../toplevel/eco32.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/eco32" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
430,12 → 430,12
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
<file xil_pn:name="../src/dsp/chrgenlo.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../src/dsp/chrgenhi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../src/dsp/dspatthi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../src/dsp/dspattlo.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../src/dsp/dspchrhi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../src/dsp/dspchrlo.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/chrgenlo.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/chrgenhi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/dspatthi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/dspattlo.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/dspchrhi.init" xil_pn:type="FILE_VERILOG"/> |
<file xil_pn:name="../../../src/dsp/common/dspchrlo.init" xil_pn:type="FILE_VERILOG"/> |
</autoManagedFiles> |
|
</project> |
/fpga/boards/xsa-xst-3/build/eco32.bit
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/fpga/boards/xsa-xst-3/Makefile
0,0 → 1,24
# |
# Makefile for ECO32 on XESS XSA-XST-3 board |
# |
|
BUILD = ../../../build |
|
.PHONY: all install clean |
|
all: build/eco32.bit |
|
install: build/eco32.bit |
$(BUILD)/bin/bit2exo 0x180000 \ |
build/eco32.bit build/eco32.exo |
mkdir -p $(BUILD)/eco32/xsa-xst-3 |
cp build/eco32.bit $(BUILD)/eco32/xsa-xst-3 |
cp build/eco32.exo $(BUILD)/eco32/xsa-xst-3 |
|
clean: |
mv build/eco32.xise . |
mv build/eco32.bit . |
rm -rf build/* |
mv eco32.xise build |
mv eco32.bit build |
rm -f *~ |
/fpga/boards/s3e-500/Makefile
0,0 → 1,28
# |
# Makefile for FPGA implementations of ECO32 |
# |
|
BUILD = ../../../build |
|
.PHONY: all install clean |
|
all: |
#all: xsa-xst-3/eco32.bit |
|
install: |
#install: xsa-xst-3/eco32.bit |
# $(BUILD)/bin/bit2exo 0x180000 \ |
# xsa-xst-3/eco32.bit xsa-xst-3/eco32.exo |
# mkdir -p $(BUILD)/eco32/xsa-xst-3 |
# cp xsa-xst-3/eco32.bit $(BUILD)/eco32/xsa-xst-3 |
# cp xsa-xst-3/eco32.exo $(BUILD)/eco32/xsa-xst-3 |
|
clean: |
# mv xsa-xst-3/eco32.ucf . |
# mv xsa-xst-3/eco32.xise . |
# mv xsa-xst-3/eco32.bit . |
# rm -rf xsa-xst-3/* |
# mv eco32.ucf xsa-xst-3 |
# mv eco32.xise xsa-xst-3 |
# mv eco32.bit xsa-xst-3 |
rm -f *~ |
/fpga/boards/Makefile
0,0 → 1,25
# |
# Makefile for FPGA implementations of ECO32 |
# |
|
BUILD = ../../build |
|
DIRS = xsa-xst-3 s3e-500 |
|
.PHONY: all install clean |
|
all: |
for i in $(DIRS) ; do \ |
$(MAKE) -C $$i all ; \ |
done |
|
install: |
for i in $(DIRS) ; do \ |
$(MAKE) -C $$i install ; \ |
done |
|
clean: |
for i in $(DIRS) ; do \ |
$(MAKE) -C $$i clean ; \ |
done |
rm -f *~ |
/fpga/Makefile
6,21 → 6,12
|
.PHONY: all install clean |
|
all: xsa-xst-3/eco32.bit |
all: |
$(MAKE) -C boards all |
|
install: xsa-xst-3/eco32.bit |
$(BUILD)/bin/bit2exo 0x180000 \ |
xsa-xst-3/eco32.bit xsa-xst-3/eco32.exo |
mkdir -p $(BUILD)/eco32/xsa-xst-3 |
cp xsa-xst-3/eco32.bit $(BUILD)/eco32/xsa-xst-3 |
cp xsa-xst-3/eco32.exo $(BUILD)/eco32/xsa-xst-3 |
install: |
$(MAKE) -C boards install |
|
clean: |
mv xsa-xst-3/eco32.ucf . |
mv xsa-xst-3/eco32.xise . |
mv xsa-xst-3/eco32.bit . |
rm -rf xsa-xst-3/* |
mv eco32.ucf xsa-xst-3 |
mv eco32.xise xsa-xst-3 |
mv eco32.bit xsa-xst-3 |
$(MAKE) -C boards clean |
rm -f *~ |