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URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

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  • This comparison shows the changes necessary to convert path 
    /eco32/trunk
    from Rev 228 to Rev 229
    ↔ Reverse comparison
  •

Rev 228 → Rev 229

/fpga/src/spi/spi.v File deleted
/fpga/boards/s3e-500/build/eco32.xise
32,11 → 32,11
</file>
<file xil_pn:name="../../../src/cpu/cpu.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../../src/ram/ddr/ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../src/ram/ddr/ddr_sdram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
44,7 → 44,7
</file>
<file xil_pn:name="../../../src/rom/28F128J3/rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../src/tmr/tmr.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
52,7 → 52,7
</file>
<file xil_pn:name="../../../src/dsp/bpp3/dsp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../src/dsp/bpp3/display.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
76,7 → 76,7
</file>
<file xil_pn:name="../../../src/kbd/kbd.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/kbd/keyboard.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
84,7 → 84,7
</file>
<file xil_pn:name="../../../src/ser/ser.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../../src/ser/rcvbuf.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
104,11 → 104,11
</file>
<file xil_pn:name="../../../src/fms/fms.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/spi/spi.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../spi/spi.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../bio/bio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
/fpga/boards/s3e-500/build/eco32.bit Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/fpga/boards/s3e-500/spi/spi.v
0,0 → 1,136
//
// spi.v -- SPI bus controller
//
 
 
module spi(clk, reset, spi_en,
dac_sample_l, dac_sample_r, dac_next,
spi_sck, spi_mosi,
dac_cs_n, dac_clr_n,
amp_cs_n, amp_shdn,
ad_conv);
// internal interface
input clk;
input reset;
input spi_en;
// DAC controller interface
input [15:0] dac_sample_l;
input [15:0] dac_sample_r;
output dac_next;
// external interface
output spi_sck;
output spi_mosi;
output dac_cs_n;
output dac_clr_n;
output amp_cs_n;
output amp_shdn;
output ad_conv;
 
//------------------------------------------------------------
 
//
// SPI timing and clock generator
//
 
reg [9:0] timing;
 
always @(posedge clk) begin
if (reset) begin
timing <= 10'h0;
end else begin
if (spi_en == 1'b0 && timing == 10'h0) begin
// put SPI on hold in state 0 if disabled
timing <= timing;
end else begin
// else step through the command cycle
timing <= timing + 1;
end
end
end
 
assign spi_sck = timing[0];
 
//------------------------------------------------------------
 
//
// DAC controller
//
 
reg dac_ld;
reg [47:0] dac_sr;
wire dac_shift;
 
assign dac_next = (timing[9:0] == 10'h001) ? 1 : 0;
 
always @(posedge clk) begin
if (reset) begin
dac_ld <= 1'b1;
end else begin
if (timing[9:0] == 10'h001) begin
dac_ld <= 1'b0;
end
if (timing[9:0] == 10'h031) begin
dac_ld <= 1'b1;
end
if (timing[9:0] == 10'h033) begin
dac_ld <= 1'b0;
end
if (timing[9:0] == 10'h063) begin
dac_ld <= 1'b1;
end
end
end
 
assign dac_shift = spi_sck & ~dac_ld;
 
always @(posedge clk) begin
if (reset) begin
dac_sr <= 48'h0;
end else begin
if (dac_next) begin
dac_sr[47:44] <= 4'b0011;
dac_sr[43:40] <= 4'b0000;
dac_sr[39:24] <= { ~dac_sample_l[15],
dac_sample_l[14:0] };
dac_sr[23:20] <= 4'b0011;
dac_sr[19:16] <= 4'b0001;
dac_sr[15: 0] <= { ~dac_sample_r[15],
dac_sample_r[14:0] };
end else begin
if (dac_shift) begin
dac_sr[47:1] <= dac_sr[46:0];
dac_sr[0] <= 1'b0;
end
end
end
end
 
assign dac_cs_n = dac_ld;
assign dac_clr_n = ~reset;
 
//------------------------------------------------------------
 
//
// amplifier controller
//
 
assign amp_cs_n = 1;
assign amp_shdn = reset;
 
//------------------------------------------------------------
 
//
// ADC controller
//
 
assign ad_conv = 0;
 
//------------------------------------------------------------
 
//
// SPI data output
//
 
assign spi_mosi = dac_sr[47];
 
endmodule

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